i965/miptree: Replace is_lossless_compressed with mt->aux_usage checks

[mesa.git] / src / mesa / drivers / dri / i965 / brw_curbe.c

diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c b/src/mesa/drivers/dri/i965/brw_curbe.c
index 45bdab19b7fbbdfbdee5ed9b09d19341633e1e73..139a3bcdf86753d8d267a79c2ca3a72a228b946b 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -41,7 +41,7 @@
  * quickly at thread setup time.  Each individual fixed function unit's state
  * (brw_vs_state.c for example) tells the hardware which subset of the CURBE
  * it wants in its register space, and we calculate those areas here under the
- * BRW_NEW_CURBE_OFFSETS state flag.  The brw_urb.c allocation will control
+ * BRW_NEW_PUSH_CONSTANT_ALLOCATION state flag.  The brw_urb.c allocation will control
  * how many CURBEs can be loaded into the hardware at once before a pipeline
  * stall occurs at CMD_CONST_BUFFER time.
  *
@@ -50,6 +50,7 @@
  */
 
 
+#include "compiler/nir/nir.h"
 #include "main/context.h"
 #include "main/macros.h"
 #include "main/enums.h"
@@ -76,7 +77,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
 {
    struct gl_context *ctx = &brw->ctx;
    /* BRW_NEW_FS_PROG_DATA */
-   const GLuint nr_fp_regs = (brw->wm.prog_data->base.nr_params + 15) / 16;
+   const GLuint nr_fp_regs = (brw->wm.base.prog_data->nr_params + 15) / 16;
 
    /* BRW_NEW_VS_PROG_DATA */
    const GLuint nr_vp_regs = (brw->vs.base.prog_data->nr_params + 15) / 16;
@@ -134,7 +135,7 @@ static void calculate_curbe_offsets( struct brw_context *brw )
                  brw->curbe.vs_start,
                  brw->curbe.vs_size );
 
-      brw->ctx.NewDriverState |= BRW_NEW_CURBE_OFFSETS;
+      brw->ctx.NewDriverState |= BRW_NEW_PUSH_CONSTANT_ALLOCATION;
    }
 }
 
@@ -195,7 +196,7 @@ static void
 brw_upload_constant_buffer(struct brw_context *brw)
 {
    struct gl_context *ctx = &brw->ctx;
-   /* BRW_NEW_CURBE_OFFSETS */
+   /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
    const GLuint sz = brw->curbe.total_size;
    const GLuint bufsz = sz * 16 * sizeof(GLfloat);
    gl_constant_value *buf;
@@ -213,14 +214,14 @@ brw_upload_constant_buffer(struct brw_context *brw)
 
    /* fragment shader constants */
    if (brw->curbe.wm_size) {
-      _mesa_load_state_parameters(ctx, brw->fragment_program->Base.Parameters);
+      _mesa_load_state_parameters(ctx, brw->fragment_program->Parameters);
 
-      /* BRW_NEW_CURBE_OFFSETS */
+      /* BRW_NEW_PUSH_CONSTANT_ALLOCATION */
       GLuint offset = brw->curbe.wm_start * 16;
 
       /* BRW_NEW_FS_PROG_DATA | _NEW_PROGRAM_CONSTANTS: copy uniform values */
-      for (i = 0; i < brw->wm.prog_data->base.nr_params; i++) {
-        buf[offset + i] = *brw->wm.prog_data->base.param[i];
+      for (i = 0; i < brw->wm.base.prog_data->nr_params; i++) {
+        buf[offset + i] = *brw->wm.base.prog_data->param[i];
       }
    }
 
@@ -255,7 +256,7 @@ brw_upload_constant_buffer(struct brw_context *brw)
 
    /* vertex shader constants */
    if (brw->curbe.vs_size) {
-      _mesa_load_state_parameters(ctx, brw->vertex_program->Base.Parameters);
+      _mesa_load_state_parameters(ctx, brw->vertex_program->Parameters);
 
       GLuint offset = brw->curbe.vs_start * 16;
 
@@ -324,7 +325,7 @@ emit:
     * BRW_NEW_FRAGMENT_PROGRAM
     */
    if (brw->gen == 4 && !brw->is_g4x &&
-       (brw->fragment_program->Base.InputsRead & (1 << VARYING_SLOT_POS))) {
+       (brw->fragment_program->info.inputs_read & (1 << VARYING_SLOT_POS))) {
       BEGIN_BATCH(2);
       OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2));
       OUT_BATCH(0);
@@ -337,7 +338,7 @@ const struct brw_tracked_state brw_constant_buffer = {
       .mesa = _NEW_PROGRAM_CONSTANTS,
       .brw  = BRW_NEW_BATCH |
               BRW_NEW_BLORP |
-              BRW_NEW_CURBE_OFFSETS |
+              BRW_NEW_PUSH_CONSTANT_ALLOCATION |
               BRW_NEW_FRAGMENT_PROGRAM |
               BRW_NEW_FS_PROG_DATA |
               BRW_NEW_PSP | /* Implicit - hardware requires this, not used above */