#define GEN7_SAMPLER_LOD_BIAS_MASK INTEL_MASK(13, 1)
#define GEN7_SAMPLER_LOD_BIAS_SHIFT 1
-#define GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORIHTM (1 << 0)
+#define GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHM (1 << 0)
/* SAMPLER_STATE DW1 */
#define GEN4_SAMPLER_MIN_LOD_MASK INTEL_MASK(31, 22)
#define BRW_DEPENDENCY_NOTCHECKED 2
#define BRW_DEPENDENCY_DISABLE 3
-#define BRW_EXECUTE_1 0
-#define BRW_EXECUTE_2 1
-#define BRW_EXECUTE_4 2
-#define BRW_EXECUTE_8 3
-#define BRW_EXECUTE_16 4
-#define BRW_EXECUTE_32 5
+enum PACKED brw_execution_size {
+ BRW_EXECUTE_1 = 0,
+ BRW_EXECUTE_2 = 1,
+ BRW_EXECUTE_4 = 2,
+ BRW_EXECUTE_8 = 3,
+ BRW_EXECUTE_16 = 4,
+ BRW_EXECUTE_32 = 5,
+};
-#define BRW_HORIZONTAL_STRIDE_0 0
-#define BRW_HORIZONTAL_STRIDE_1 1
-#define BRW_HORIZONTAL_STRIDE_2 2
-#define BRW_HORIZONTAL_STRIDE_4 3
+enum PACKED brw_horizontal_stride {
+ BRW_HORIZONTAL_STRIDE_0 = 0,
+ BRW_HORIZONTAL_STRIDE_1 = 1,
+ BRW_HORIZONTAL_STRIDE_2 = 2,
+ BRW_HORIZONTAL_STRIDE_4 = 3,
+};
#define BRW_INSTRUCTION_NORMAL 0
#define BRW_INSTRUCTION_SATURATE 1
BRW_OPCODE_MSAVE = 44, /**< Pre-Gen6 */
BRW_OPCODE_MRESTORE = 45, /**< Pre-Gen6 */
BRW_OPCODE_PUSH = 46, /**< Pre-Gen6 */
+ BRW_OPCODE_GOTO = 46, /**< Gen8+ */
BRW_OPCODE_POP = 47, /**< Pre-Gen6 */
BRW_OPCODE_WAIT = 48,
BRW_OPCODE_SEND = 49,
BRW_OPCODE_PLN = 90, /**< G45+ */
BRW_OPCODE_MAD = 91, /**< Gen6+ */
BRW_OPCODE_LRP = 92, /**< Gen6+ */
+ BRW_OPCODE_NENOP = 125, /**< G45 only */
BRW_OPCODE_NOP = 126,
/* These are compiler backend opcodes that get translated into other
SHADER_OPCODE_GEN4_SCRATCH_WRITE,
SHADER_OPCODE_GEN7_SCRATCH_READ,
- FS_OPCODE_DDX,
- FS_OPCODE_DDY,
+ SHADER_OPCODE_URB_WRITE_SIMD8,
+
+ VEC4_OPCODE_PACK_BYTES,
+ VEC4_OPCODE_UNPACK_UNIFORM,
+
+ FS_OPCODE_DDX_COARSE,
+ FS_OPCODE_DDX_FINE,
+ /**
+ * Compute dFdy(), dFdyCoarse(), or dFdyFine().
+ * src1 is an immediate storing the key->render_to_fbo boolean.
+ */
+ FS_OPCODE_DDY_COARSE,
+ FS_OPCODE_DDY_FINE,
FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y,
FS_OPCODE_CINTERP,
*/
GS_OPCODE_URB_WRITE,
+ /**
+ * Write geometry shader output data to the URB and request a new URB
+ * handle (gen6).
+ *
+ * This opcode doesn't do an implied move from R0 to the first MRF.
+ */
+ GS_OPCODE_URB_WRITE_ALLOCATE,
+
/**
* Terminate the geometry shader thread by doing an empty URB write.
*
GS_OPCODE_SET_VERTEX_COUNT,
/**
- * Set DWORD 2 of dst to the immediate value in src. Used by geometry
- * shaders to initialize DWORD 2 of R0, which needs to be 0 in order for
- * scratch reads and writes to operate correctly.
+ * Set DWORD 2 of dst to the value in src.
*/
- GS_OPCODE_SET_DWORD_2_IMMED,
+ GS_OPCODE_SET_DWORD_2,
/**
* Prepare the dst register for storage in the "Channel Mask" fields of a
* - dst is the GRF for gl_InvocationID.
*/
GS_OPCODE_GET_INSTANCE_ID,
-};
-enum brw_derivative_quality {
- BRW_DERIVATIVE_BY_HINT = 0,
- BRW_DERIVATIVE_FINE = 1,
- BRW_DERIVATIVE_COARSE = 2,
+ /**
+ * Send a FF_SYNC message to allocate initial URB handles (gen6).
+ *
+ * - dst will be used as the writeback register for the FF_SYNC operation.
+ *
+ * - src0 is the number of primitives written.
+ *
+ * - src1 is the value to hold in M0.0: number of SO vertices to write
+ * and number of SO primitives needed. Its value will be overwritten
+ * with the SVBI values if transform feedback is enabled.
+ *
+ * Note: This opcode uses an implicit MRF register for the ff_sync message
+ * header, so the caller is expected to set inst->base_mrf and initialize
+ * that MRF register to r0. This opcode will also write to this MRF register
+ * to include the allocated URB handle so it can then be reused directly as
+ * the header in the URB write operation we are allocating the handle for.
+ */
+ GS_OPCODE_FF_SYNC,
+
+ /**
+ * Move r0.1 (which holds PrimitiveID information in gen6) to a separate
+ * register.
+ *
+ * - dst is the GRF where PrimitiveID information will be moved.
+ */
+ GS_OPCODE_SET_PRIMITIVE_ID,
+
+ /**
+ * Write transform feedback data to the SVB by sending a SVB WRITE message.
+ * Used in gen6.
+ *
+ * - dst is the MRF register containing the message header.
+ *
+ * - src0 is the register where the vertex data is going to be copied from.
+ *
+ * - src1 is the destination register when write commit occurs.
+ */
+ GS_OPCODE_SVB_WRITE,
+
+ /**
+ * Set destination index in the SVB write message payload (M0.5). Used
+ * in gen6 for transform feedback.
+ *
+ * - dst is the header to save the destination indices for SVB WRITE.
+ * - src is the register that holds the destination indices value.
+ */
+ GS_OPCODE_SVB_SET_DST_INDEX,
+
+ /**
+ * Prepare Mx.0 subregister for being used in the FF_SYNC message header.
+ * Used in gen6 for transform feedback.
+ *
+ * - dst will hold the register with the final Mx.0 value.
+ *
+ * - src0 has the number of vertices emitted in SO (NumSOVertsToWrite)
+ *
+ * - src1 has the number of needed primitives for SO (NumSOPrimsNeeded)
+ *
+ * - src2 is the value to hold in M0: number of SO vertices to write
+ * and number of SO primitives needed.
+ */
+ GS_OPCODE_FF_SYNC_SET_PRIMITIVES,
};
enum brw_urb_write_flags {
#define BRW_THREAD_ATOMIC 1
#define BRW_THREAD_SWITCH 2
-#define BRW_VERTICAL_STRIDE_0 0
-#define BRW_VERTICAL_STRIDE_1 1
-#define BRW_VERTICAL_STRIDE_2 2
-#define BRW_VERTICAL_STRIDE_4 3
-#define BRW_VERTICAL_STRIDE_8 4
-#define BRW_VERTICAL_STRIDE_16 5
-#define BRW_VERTICAL_STRIDE_32 6
-#define BRW_VERTICAL_STRIDE_64 7
-#define BRW_VERTICAL_STRIDE_128 8
-#define BRW_VERTICAL_STRIDE_256 9
-#define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF
-
-#define BRW_WIDTH_1 0
-#define BRW_WIDTH_2 1
-#define BRW_WIDTH_4 2
-#define BRW_WIDTH_8 3
-#define BRW_WIDTH_16 4
+enum PACKED brw_vertical_stride {
+ BRW_VERTICAL_STRIDE_0 = 0,
+ BRW_VERTICAL_STRIDE_1 = 1,
+ BRW_VERTICAL_STRIDE_2 = 2,
+ BRW_VERTICAL_STRIDE_4 = 3,
+ BRW_VERTICAL_STRIDE_8 = 4,
+ BRW_VERTICAL_STRIDE_16 = 5,
+ BRW_VERTICAL_STRIDE_32 = 6,
+ BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL = 0xF,
+};
+
+enum PACKED brw_width {
+ BRW_WIDTH_1 = 0,
+ BRW_WIDTH_2 = 1,
+ BRW_WIDTH_4 = 2,
+ BRW_WIDTH_8 = 3,
+ BRW_WIDTH_16 = 4,
+};
#define BRW_STATELESS_BUFFER_BOUNDARY_1K 0
#define BRW_STATELESS_BUFFER_BOUNDARY_2K 1
#define BRW_URB_OPCODE_WRITE_HWORD 0
#define BRW_URB_OPCODE_WRITE_OWORD 1
+#define GEN8_URB_OPCODE_SIMD8_WRITE 7
#define BRW_URB_SWIZZLE_NONE 0
#define BRW_URB_SWIZZLE_INTERLEAVE 1
# define GEN7_URB_ENTRY_SIZE_SHIFT 16
# define GEN7_URB_STARTING_ADDRESS_SHIFT 25
-/* "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
+/* Gen7 "GS URB Entry Allocation Size" is a U9-1 field, so the maximum gs_size
* is 2^9, or 512. It's counted in multiples of 64 bytes.
*/
-#define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
+#define GEN7_MAX_GS_URB_ENTRY_SIZE_BYTES (512*64)
+/* Gen6 "GS URB Entry Allocation Size" is defined as a number of 1024-bit
+ * (128 bytes) URB rows and the maximum allowed value is 5 rows.
+ */
+#define GEN6_MAX_GS_URB_ENTRY_SIZE_BYTES (5*128)
#define _3DSTATE_PUSH_CONSTANT_ALLOC_VS 0x7912 /* GEN7+ */
#define _3DSTATE_PUSH_CONSTANT_ALLOC_GS 0x7915 /* GEN7+ */
# define GEN6_VS_STATISTICS_ENABLE (1 << 10)
# define GEN6_VS_CACHE_DISABLE (1 << 1)
# define GEN6_VS_ENABLE (1 << 0)
+/* Gen8+ DW7 */
+# define GEN8_VS_SIMD8_ENABLE (1 << 2)
/* Gen8+ DW8 */
# define GEN8_VS_URB_ENTRY_OUTPUT_OFFSET_SHIFT 21
# define GEN8_VS_URB_OUTPUT_LENGTH_SHIFT 16
# define GEN6_SF_SWIZZLE_ENABLE (1 << 21)
# define GEN6_SF_POINT_SPRITE_UPPERLEFT (0 << 20)
# define GEN6_SF_POINT_SPRITE_LOWERLEFT (1 << 20)
+# define GEN9_SF_LINE_WIDTH_SHIFT 12 /* U11.7 */
# define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT 11
# define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT 4
/* DW2 */
/* DW12: attr 0-7 wrap shortest enables */
/* DW13: attr 8-16 wrap shortest enables */
+/* DW4-5: Attribute active components (gen9) */
+#define GEN9_SBE_ACTIVE_COMPONENT_NONE 0
+#define GEN9_SBE_ACTIVE_COMPONENT_XY 1
+#define GEN9_SBE_ACTIVE_COMPONENT_XYZ 2
+#define GEN9_SBE_ACTIVE_COMPONENT_XYZW 3
+
#define _3DSTATE_SBE_SWIZ 0x7851 /* GEN8+ */
#define _3DSTATE_RASTER 0x7850 /* GEN8+ */
/* DW1 */
+# define GEN9_RASTER_VIEWPORT_Z_FAR_CLIP_TEST_ENABLE (1 << 26)
# define GEN8_RASTER_FRONT_WINDING_CCW (1 << 21)
# define GEN8_RASTER_CULL_BOTH (0 << 16)
# define GEN8_RASTER_CULL_NONE (1 << 16)
# define GEN8_RASTER_LINE_AA_ENABLE (1 << 2)
# define GEN8_RASTER_SCISSOR_ENABLE (1 << 1)
# define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE (1 << 0)
+# define GEN9_RASTER_VIEWPORT_Z_NEAR_CLIP_TEST_ENABLE (1 << 0)
/* Gen8 BLEND_STATE */
/* DW0 */
# define GEN8_WM_DS_BF_STENCIL_TEST_MASK_SHIFT 8
# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_SHIFT 0
+/* DW3 */
+# define GEN9_WM_DS_STENCIL_REF_MASK INTEL_MASK(15, 8)
+# define GEN9_WM_DS_STENCIL_REF_SHIFT 8
+# define GEN9_WM_DS_BF_STENCIL_REF_MASK INTEL_MASK(7, 0)
+# define GEN9_WM_DS_BF_STENCIL_REF_SHIFT 0
+
+enum brw_pixel_shader_computed_depth_mode {
+ BRW_PSCDEPTH_OFF = 0, /* PS does not compute depth */
+ BRW_PSCDEPTH_ON = 1, /* PS computes depth; no guarantee about value */
+ BRW_PSCDEPTH_ON_GE = 2, /* PS guarantees output depth >= source depth */
+ BRW_PSCDEPTH_ON_LE = 3, /* PS guarantees output depth <= source depth */
+};
#define _3DSTATE_PS_EXTRA 0x784F /* GEN8+ */
/* DW1 */
# define GEN8_PSX_PIXEL_SHADER_NO_RT_WRITE (1 << 30)
# define GEN8_PSX_OMASK_TO_RENDER_TARGET (1 << 29)
# define GEN8_PSX_KILL_ENABLE (1 << 28)
-# define GEN8_PSX_PSCDEPTH_OFF (0 << 26)
-# define GEN8_PSX_PSCDEPTH_ON (1 << 26)
-# define GEN8_PSX_PSCDEPTH_ON_GE (2 << 26)
-# define GEN8_PSX_PSCDEPTH_ON_LE (3 << 26)
+# define GEN8_PSX_COMPUTED_DEPTH_MODE_SHIFT 26
# define GEN8_PSX_FORCE_COMPUTED_DEPTH (1 << 25)
# define GEN8_PSX_USES_SOURCE_DEPTH (1 << 24)
# define GEN8_PSX_USES_SOURCE_W (1 << 23)
# define GEN7_WM_DEPTH_RESOLVE (1 << 28)
# define GEN7_WM_HIERARCHICAL_DEPTH_RESOLVE (1 << 27)
# define GEN7_WM_KILL_ENABLE (1 << 25)
-# define GEN7_WM_PSCDEPTH_OFF (0 << 23)
-# define GEN7_WM_PSCDEPTH_ON (1 << 23)
-# define GEN7_WM_PSCDEPTH_ON_GE (2 << 23)
-# define GEN7_WM_PSCDEPTH_ON_LE (3 << 23)
+# define GEN7_WM_COMPUTED_DEPTH_MODE_SHIFT 23
# define GEN7_WM_USES_SOURCE_DEPTH (1 << 20)
# define GEN7_WM_USES_SOURCE_W (1 << 19)
# define GEN7_WM_POSITION_ZW_PIXEL (0 << 17)
#define HSW_MOCS_WB_LLC_WB_ELLC (2 << 1)
#define HSW_MOCS_UC_LLC_WB_ELLC (3 << 1)
-/* Broadwell: write-back or write-through; always use all the caches. */
-#define BDW_MOCS_WB 0x78
-#define BDW_MOCS_WT 0x58
+/* Broadwell: these defines always use all available caches (L3, LLC, eLLC),
+ * and let you force write-back (WB) or write-through (WT) caching, or leave
+ * it up to the page table entry (PTE) specified by the kernel.
+ */
+#define BDW_MOCS_WB 0x78
+#define BDW_MOCS_WT 0x58
+#define BDW_MOCS_PTE 0x18
-#include "intel_chipset.h"
+/* Skylake: MOCS is now an index into an array of 64 different configurable
+ * cache settings. We still use only either write-back or write-through; and
+ * rely on the documented default values.
+ */
+#define SKL_MOCS_WB 9
+#define SKL_MOCS_WT 5
#endif
projects / mesa.git / blobdiff