i965/urb: fixes division by zero

[mesa.git] / src / mesa / drivers / dri / i965 / brw_defines.h

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 9edb6f542046c873a6cd4f3f9c48b816938a2898..3395c9b87cceefd6eaa31cb9a4e81d4e81f45c85 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -63,7 +63,6 @@
 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8)
 # define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM     (1 << 8)
 
-#ifndef _3DPRIM_POINTLIST /* FIXME: Avoid clashing with defines from bdw_pack.h */
 #define _3DPRIM_POINTLIST         0x01
 #define _3DPRIM_LINELIST          0x02
 #define _3DPRIM_LINESTRIP         0x03
@@ -87,7 +86,6 @@
 #define _3DPRIM_TRIFAN_NOSTIPPLE  0x16
 #define _3DPRIM_PATCHLIST(n) ({ assert(n > 0 && n <= 32); 0x20 + (n - 1); })
 
-#endif /* bdw_pack.h */
 
 /* We use this offset to be able to pass native primitive types in struct
  * _mesa_prim::mode.  Native primitive types are BRW_PRIM_OFFSET +
@@ -658,6 +656,7 @@
 #define GEN8_SURFACE_AUX_MODE_MCS               1
 #define GEN8_SURFACE_AUX_MODE_APPEND            2
 #define GEN8_SURFACE_AUX_MODE_HIZ               3
+#define GEN9_SURFACE_AUX_MODE_CCS_E             5
 
 /* Surface state DW7 */
 #define GEN9_SURFACE_RT_COMPRESSION_SHIFT       30
@@ -951,7 +950,6 @@ enum opcode {
     */
    FS_OPCODE_FB_WRITE_LOGICAL,
 
-   FS_OPCODE_BLORP_FB_WRITE,
    FS_OPCODE_REP_FB_WRITE,
    FS_OPCODE_PACK_STENCIL_REF,
    SHADER_OPCODE_RCP,
@@ -970,19 +968,8 @@ enum opcode {
     *
     * LOGICAL opcodes are eventually translated to the matching non-LOGICAL
     * opcode but instead of taking a single payload blob they expect their
-    * arguments separately as individual sources:
-    *
-    * Source 0: [optional] Texture coordinates.
-    * Source 1: [optional] Shadow comparitor.
-    * Source 2: [optional] dPdx if the operation takes explicit derivatives,
-    *                      otherwise LOD value.
-    * Source 3: [optional] dPdy if the operation takes explicit derivatives.
-    * Source 4: [optional] Sample index.
-    * Source 5: [optional] MCS data.
-    * Source 6: [required] Texture sampler.
-    * Source 7: [optional] Texel offset.
-    * Source 8: [required] Number of coordinate components (as UD immediate).
-    * Source 9: [required] Number derivative components (as UD immediate).
+    * arguments separately as individual sources. The position/ordering of the
+    * arguments are defined by the enum tex_logical_srcs.
     */
    SHADER_OPCODE_TEX,
    SHADER_OPCODE_TEX_LOGICAL,
@@ -1026,6 +1013,15 @@ enum opcode {
     */
    SHADER_OPCODE_LOAD_PAYLOAD,
 
+   /**
+    * Packs a number of sources into a single value. Unlike LOAD_PAYLOAD, this
+    * acts intra-channel, obtaining the final value for each channel by
+    * combining the sources values for the same channel, the first source
+    * occupying the lowest bits and the last source occupying the highest
+    * bits.
+    */
+   FS_OPCODE_PACK,
+
    SHADER_OPCODE_SHADER_TIME_ADD,
 
    /**
@@ -1406,6 +1402,33 @@ enum fb_write_logical_srcs {
    FB_WRITE_LOGICAL_SRC_COMPONENTS,  /* REQUIRED */
 };
 
+enum tex_logical_srcs {
+   /** Texture coordinates */
+   TEX_LOGICAL_SRC_COORDINATE,
+   /** Shadow comparitor */
+   TEX_LOGICAL_SRC_SHADOW_C,
+   /** dPdx if the operation takes explicit derivatives, otherwise LOD value */
+   TEX_LOGICAL_SRC_LOD,
+   /** dPdy if the operation takes explicit derivatives */
+   TEX_LOGICAL_SRC_LOD2,
+   /** Sample index */
+   TEX_LOGICAL_SRC_SAMPLE_INDEX,
+   /** MCS data */
+   TEX_LOGICAL_SRC_MCS,
+   /** REQUIRED: Texture surface index */
+   TEX_LOGICAL_SRC_SURFACE,
+   /** Texture sampler index */
+   TEX_LOGICAL_SRC_SAMPLER,
+   /** Texel offset for gathers */
+   TEX_LOGICAL_SRC_OFFSET_VALUE,
+   /** REQUIRED: Number of coordinate components (as UD immediate) */
+   TEX_LOGICAL_SRC_COORD_COMPONENTS,
+   /** REQUIRED: Number of derivative components (as UD immediate) */
+   TEX_LOGICAL_SRC_GRAD_COMPONENTS,
+
+   TEX_LOGICAL_NUM_SRCS,
+};
+
 #ifdef __cplusplus
 /**
  * Allow brw_urb_write_flags enums to be ORed together.
@@ -2713,6 +2736,7 @@ enum brw_wm_barycentric_interp_mode {
 # define GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE       (1 << 8)
 # define GEN7_PS_DUAL_SOURCE_BLEND_ENABLE              (1 << 7)
 # define GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE          (1 << 6)
+# define GEN9_PS_RENDER_TARGET_RESOLVE_FULL             (3 << 6)
 # define HSW_PS_UAV_ACCESS_ENABLE                      (1 << 5)
 # define GEN7_PS_POSOFFSET_NONE                                (0 << 3)
 # define GEN7_PS_POSOFFSET_CENTROID                    (2 << 3)
@@ -2923,6 +2947,7 @@ enum brw_wm_barycentric_interp_mode {
 #define GPGPU_WALKER                            0x7105
 /* GEN7 DW0 */
 # define GEN7_GPGPU_INDIRECT_PARAMETER_ENABLE   (1 << 10)
+# define GEN7_GPGPU_PREDICATE_ENABLE            (1 << 8)
 /* GEN8+ DW2 */
 # define GPGPU_WALKER_INDIRECT_LENGTH_SHIFT     0
 # define GPGPU_WALKER_INDIRECT_LENGTH_MASK      INTEL_MASK(15, 0)