/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
develop this 3D driver.
Permission is hereby granted, free of charge, to any person obtaining
**********************************************************************/
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
#define INTEL_MASK(high, low) (((1<<((high)-(low)+1))-1)<<(low))
#define GEN7_SURFACE_MSFMT_MSS (0 << 6)
#define GEN7_SURFACE_MSFMT_DEPTH_STENCIL (1 << 6)
#define GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT 18
+#define GEN7_SURFACE_MIN_ARRAY_ELEMENT_MASK INTEL_MASK(28, 18)
#define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT 7
+#define GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_MASK INTEL_MASK(17, 7)
/* Surface state DW5 */
#define BRW_SURFACE_X_OFFSET_SHIFT 25
* instructions.
*/
FS_OPCODE_FB_WRITE = 128,
+ FS_OPCODE_BLORP_FB_WRITE,
SHADER_OPCODE_RCP,
SHADER_OPCODE_RSQ,
SHADER_OPCODE_SQRT,
SHADER_OPCODE_TXL,
SHADER_OPCODE_TXS,
FS_OPCODE_TXB,
- SHADER_OPCODE_TXF_MS,
+ SHADER_OPCODE_TXF_CMS,
+ SHADER_OPCODE_TXF_UMS,
SHADER_OPCODE_TXF_MCS,
SHADER_OPCODE_LOD,
SHADER_OPCODE_TG4,
BRW_SFID_DATAPORT_WRITE = 5,
BRW_SFID_URB = 6,
BRW_SFID_THREAD_SPAWNER = 7,
+ BRW_SFID_VME = 8,
GEN6_SFID_DATAPORT_SAMPLER_CACHE = 4,
GEN6_SFID_DATAPORT_RENDER_CACHE = 5,
GEN6_SFID_DATAPORT_CONSTANT_CACHE = 9,
GEN7_SFID_DATAPORT_DATA_CACHE = 10,
+ GEN7_SFID_PIXEL_INTERPOLATOR = 11,
HSW_SFID_DATAPORT_DATA_CACHE_1 = 12,
+ HSW_SFID_CRE = 13,
};
#define GEN7_MESSAGE_TARGET_DP_DATA_CACHE 10
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
+#define GEN8_MATH_FUNCTION_INVM 14
+#define GEN8_MATH_FUNCTION_RSQRTM 15
#define BRW_MATH_INTEGER_UNSIGNED 0
#define BRW_MATH_INTEGER_SIGNED 1
# define GEN6_CC_VIEWPORT_MODIFY (1 << 12)
# define GEN6_SF_VIEWPORT_MODIFY (1 << 11)
# define GEN6_CLIP_VIEWPORT_MODIFY (1 << 10)
+# define GEN7_NUM_VIEWPORTS 16
#define _3DSTATE_VIEWPORT_STATE_POINTERS_CC 0x7823 /* GEN7+ */
#define _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL 0x7821 /* GEN7+ */
# define GEN6_CLIP_MIN_POINT_WIDTH_SHIFT 17
# define GEN6_CLIP_MAX_POINT_WIDTH_SHIFT 6
# define GEN6_CLIP_FORCE_ZERO_RTAINDEX (1 << 5)
+# define GEN6_CLIP_MAX_VP_INDEX_MASK INTEL_MASK(3, 0)
#define _3DSTATE_SF 0x7813 /* GEN6+ */
/* DW1 (for gen6) */
/* GEN7/DW2: */
# define HSW_SF_LINE_STIPPLE_ENABLE 14
+# define GEN8_SF_SMOOTH_POINT_ENABLE (1 << 13)
+
#define _3DSTATE_SBE 0x781F /* GEN7+ */
/* DW1 */
+# define GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH (1 << 29)
+# define GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET (1 << 28)
# define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28)
# define GEN7_SBE_NUM_OUTPUTS_SHIFT 22
# define GEN7_SBE_SWIZZLE_ENABLE (1 << 21)
# define GEN7_SBE_POINT_SPRITE_LOWERLEFT (1 << 20)
# define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11
# define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4
+# define GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT 5
/* DW2-9: Attribute setup (same as DW8-15 of gen6 _3DSTATE_SF) */
/* DW10: Point sprite texture coordinate enables */
/* DW11: Constant interpolation enables */
/* DW12: attr 0-7 wrap shortest enables */
/* DW13: attr 8-16 wrap shortest enables */
+#define _3DSTATE_SBE_SWIZ 0x7851 /* GEN8+ */
+
+#define _3DSTATE_RASTER 0x7850 /* GEN8+ */
+/* DW1 */
+# define GEN8_RASTER_FRONT_WINDING_CCW (1 << 21)
+# define GEN8_RASTER_CULL_BOTH (0 << 16)
+# define GEN8_RASTER_CULL_NONE (1 << 16)
+# define GEN8_RASTER_CULL_FRONT (2 << 16)
+# define GEN8_RASTER_CULL_BACK (3 << 16)
+# define GEN8_RASTER_SMOOTH_POINT_ENABLE (1 << 13)
+# define GEN8_RASTER_LINE_AA_ENABLE (1 << 2)
+# define GEN8_RASTER_SCISSOR_ENABLE (1 << 1)
+# define GEN8_RASTER_VIEWPORT_Z_CLIP_TEST_ENABLE (1 << 0)
+
+#define _3DSTATE_PS_BLEND 0x784D /* GEN8+ */
+/* DW1 */
+# define GEN8_PS_BLEND_ALPHA_TO_COVERAGE_ENABLE (1 << 31)
+# define GEN8_PS_BLEND_HAS_WRITEABLE_RT (1 << 30)
+# define GEN8_PS_BLEND_COLOR_BUFFER_BLEND_ENABLE (1 << 29)
+# define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(28, 24)
+# define GEN8_PS_BLEND_SRC_ALPHA_BLEND_FACTOR_SHIFT 24
+# define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_MASK INTEL_MASK(23, 19)
+# define GEN8_PS_BLEND_DST_ALPHA_BLEND_FACTOR_SHIFT 19
+# define GEN8_PS_BLEND_SRC_BLEND_FACTOR_MASK INTEL_MASK(18, 14)
+# define GEN8_PS_BLEND_SRC_BLEND_FACTOR_SHIFT 14
+# define GEN8_PS_BLEND_DST_BLEND_FACTOR_MASK INTEL_MASK(13, 9)
+# define GEN8_PS_BLEND_DST_BLEND_FACTOR_SHIFT 9
+# define GEN8_PS_BLEND_ALPHA_TEST_ENABLE (1 << 8)
+# define GEN8_PS_BLEND_INDEPENDENT_ALPHA_BLEND_ENABLE (1 << 7)
+
+#define _3DSTATE_WM_DEPTH_STENCIL 0x784E /* GEN8+ */
+/* DW1 */
+# define GEN8_WM_DS_STENCIL_FAIL_OP_SHIFT 29
+# define GEN8_WM_DS_Z_FAIL_OP_SHIFT 26
+# define GEN8_WM_DS_Z_PASS_OP_SHIFT 23
+# define GEN8_WM_DS_BF_STENCIL_FUNC_SHIFT 20
+# define GEN8_WM_DS_BF_STENCIL_FAIL_OP_SHIFT 17
+# define GEN8_WM_DS_BF_Z_FAIL_OP_SHIFT 14
+# define GEN8_WM_DS_BF_Z_PASS_OP_SHIFT 11
+# define GEN8_WM_DS_STENCIL_FUNC_SHIFT 8
+# define GEN8_WM_DS_DEPTH_FUNC_SHIFT 5
+# define GEN8_WM_DS_DOUBLE_SIDED_STENCIL_ENABLE (1 << 4)
+# define GEN8_WM_DS_STENCIL_TEST_ENABLE (1 << 3)
+# define GEN8_WM_DS_STENCIL_BUFFER_WRITE_ENABLE (1 << 2)
+# define GEN8_WM_DS_DEPTH_TEST_ENABLE (1 << 1)
+# define GEN8_WM_DS_DEPTH_BUFFER_WRITE_ENABLE (1 << 0)
+/* DW2 */
+# define GEN8_WM_DS_STENCIL_TEST_MASK_MASK INTEL_MASK(31, 24)
+# define GEN8_WM_DS_STENCIL_TEST_MASK_SHIFT 24
+# define GEN8_WM_DS_STENCIL_WRITE_MASK_MASK INTEL_MASK(23, 16)
+# define GEN8_WM_DS_STENCIL_WRITE_MASK_SHIFT 16
+# define GEN8_WM_DS_BF_STENCIL_TEST_MASK_MASK INTEL_MASK(15, 8)
+# define GEN8_WM_DS_BF_STENCIL_TEST_MASK_SHIFT 8
+# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_MASK INTEL_MASK(7, 0)
+# define GEN8_WM_DS_BF_STENCIL_WRITE_MASK_SHIFT 0
+
enum brw_wm_barycentric_interp_mode {
BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC = 0,
BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC = 1,
projects / mesa.git / blobdiff