i965: Disable hardware blending if advanced blending is in use.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_device_info.c

diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c b/src/mesa/drivers/dri/i965/brw_device_info.c
index 55c4d3613d03c38f3c05b8bc8ba8775ca3511ce9..fb224fae234afd0522e88d2e2f0d26f9b8fb1f66 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_device_info.c
+++ b/src/mesa/drivers/dri/i965/brw_device_info.c
@@ -116,7 +116,6 @@ static const struct brw_device_info brw_device_info_snb_gt2 = {
 
 static const struct brw_device_info brw_device_info_ivb_gt1 = {
    GEN7_FEATURES, .is_ivybridge = true, .gt = 1,
-   .needs_unlit_centroid_workaround = true,
    .num_slices = 1,
    .max_vs_threads = 36,
    .max_hs_threads = 36,
@@ -137,7 +136,6 @@ static const struct brw_device_info brw_device_info_ivb_gt1 = {
 
 static const struct brw_device_info brw_device_info_ivb_gt2 = {
    GEN7_FEATURES, .is_ivybridge = true, .gt = 2,
-   .needs_unlit_centroid_workaround = true,
    .num_slices = 1,
    .max_vs_threads = 128,
    .max_hs_threads = 128,
@@ -158,7 +156,6 @@ static const struct brw_device_info brw_device_info_ivb_gt2 = {
 
 static const struct brw_device_info brw_device_info_byt = {
    GEN7_FEATURES, .is_baytrail = true, .gt = 1,
-   .needs_unlit_centroid_workaround = true,
    .num_slices = 1,
    .has_llc = false,
    .max_vs_threads = 36,
@@ -252,6 +249,7 @@ static const struct brw_device_info brw_device_info_hsw_gt3 = {
    .has_llc = true,                                 \
    .has_pln = true,                                 \
    .supports_simd16_3src = true,                    \
+   .has_surface_tile_offset = true,                 \
    .max_vs_threads = 504,                           \
    .max_hs_threads = 504,                           \
    .max_ds_threads = 504,                           \
@@ -312,7 +310,7 @@ static const struct brw_device_info brw_device_info_chv = {
    .max_ds_threads = 80,
    .max_gs_threads = 80,
    .max_wm_threads = 128,
-   .max_cs_threads = 28,
+   .max_cs_threads = 6 * 7,
    .urb = {
       .size = 192,
       .min_vs_entries = 34,
@@ -332,6 +330,7 @@ static const struct brw_device_info brw_device_info_chv = {
    .has_llc = true,                                 \
    .has_pln = true,                                 \
    .supports_simd16_3src = true,                    \
+   .has_surface_tile_offset = true,                 \
    .max_vs_threads = 336,                           \
    .max_gs_threads = 336,                           \
    .max_hs_threads = 336,                           \
@@ -401,6 +400,28 @@ static const struct brw_device_info brw_device_info_bxt = {
    }
 };
 
+static const struct brw_device_info brw_device_info_bxt_2x6 = {
+   GEN9_FEATURES,
+   .is_broxton = 1,
+   .gt = 1,
+   .has_llc = false,
+
+   .num_slices = 1,
+   .max_vs_threads = 56, /* XXX: guess */
+   .max_hs_threads = 56, /* XXX: guess */
+   .max_ds_threads = 56,
+   .max_gs_threads = 56,
+   .max_wm_threads = 64 * 2,
+   .max_cs_threads = 6 * 6,
+   .urb = {
+      .size = 128,
+      .min_vs_entries = 34,
+      .max_vs_entries = 352,
+      .max_hs_entries = 128,
+      .max_ds_entries = 208,
+      .max_gs_entries = 128,
+   }
+};
 /*
  * Note: for all KBL SKUs, the PRM says SKL for GS entries, not SKL+.
  * There's no KBL entry. Using the default SKL (GEN9) GS entries value.
@@ -482,3 +503,15 @@ brw_get_device_info(int devid)
 
    return devinfo;
 }
+
+const char *
+brw_get_device_name(int devid)
+{
+   switch (devid) {
+#undef CHIPSET
+#define CHIPSET(id, family, name) case id: return name;
+#include "pci_ids/i965_pci_ids.h"
+   default:
+      return NULL;
+   }
+}