i965: Split brw_set_prim into brw/gen6 variants

[mesa.git] / src / mesa / drivers / dri / i965 / brw_draw.c

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c b/src/mesa/drivers/dri/i965/brw_draw.c
index bdb5b672899d556141c02d8118335735b9c43b5e..39d38a57a4a9492e05eb6974ac0ff56d01c19231 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -115,6 +115,19 @@ static GLuint brw_set_prim(struct brw_context *brw,
    return prim_to_hw_prim[mode];
 }
 
+static GLuint gen6_set_prim(struct brw_context *brw,
+                            const struct _mesa_prim *prim)
+{
+   DBG("PRIM: %s\n", _mesa_lookup_enum_by_nr(prim->mode));
+
+   if (prim->mode != brw->primitive) {
+      brw->primitive = prim->mode;
+      brw->state.dirty.brw |= BRW_NEW_PRIMITIVE;
+   }
+
+   return prim_to_hw_prim[mode];
+}
+
 
 static GLuint trim(GLenum prim, GLuint length)
 {
@@ -335,7 +348,11 @@ static GLboolean brw_try_draw_prims( struct gl_context *ctx,
        */
       intel_batchbuffer_require_space(intel, estimated_max_prim_size, false);
 
-      hw_prim = brw_set_prim(brw, &prim[i]);
+      if (intel->gen < 6)
+        hw_prim = brw_set_prim(brw, &prim[i]);
+      else
+        hw_prim = gen6_set_prim(brw, &prim[i]);
+
       if (brw->state.dirty.brw) {
         brw_validate_state(brw);