front_irb->need_downsample = true;
if (back_irb)
back_irb->need_downsample = true;
- if (depth_irb && ctx->Depth.Mask) {
+ if (depth_irb && brw_depth_writes_enabled(brw)) {
intel_renderbuffer_att_set_needs_depth_resolve(depth_att);
brw_render_cache_set_add_bo(brw, depth_irb->mt->bo);
}
struct intel_renderbuffer *irb =
intel_renderbuffer(fb->_ColorDrawBuffers[i]);
- if (irb) {
- brw_render_cache_set_add_bo(brw, irb->mt->bo);
-
- if (intel_miptree_is_lossless_compressed(brw, irb->mt)) {
- irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
- }
- }
+ if (!irb)
+ continue;
+
+ brw_render_cache_set_add_bo(brw, irb->mt->bo);
+ intel_miptree_used_for_rendering(
+ brw, irb->mt, irb->mt_level, irb->mt_layer, irb->layer_count);
}
}
if (!irb) {
continue;
}
+
+ /* For layered rendering non-compressed fast cleared buffers need to be
+ * resolved. Surface state can carry only one fast color clear value
+ * while each layer may have its own fast clear color value. For
+ * compressed buffers color value is available in the color buffer.
+ */
+ if (irb->layer_count > 1 &&
+ !(irb->mt->aux_disable & INTEL_AUX_DISABLE_CCS) &&
+ !intel_miptree_is_lossless_compressed(brw, irb->mt)) {
+ assert(brw->gen >= 8);
+
+ intel_miptree_resolve_color(brw, irb->mt, irb->mt_level,
+ irb->mt_layer, irb->layer_count, 0);
+ }
}
}
if (brw->always_flush_batch)
intel_batchbuffer_flush(brw);
- brw_state_cache_check_size(brw);
+ brw_program_cache_check_size(brw);
brw_postdraw_set_buffers_need_resolve(brw);
return;