i965/gs: Add a case to brwNewProgram() for geometry shaders.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_draw_upload.c

diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 17a5629de91e214e42eae0b3b395d571e5d7d5cb..390b4a37f35168c41df1d92d97e1cfbb21eb4264 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -222,9 +222,9 @@ static GLuint byte_types_scale[5] = {
  * the appopriate hardware surface type.
  * Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
  */
-static unsigned
-get_surface_type(struct brw_context *brw,
-                 const struct gl_client_array *glarray)
+unsigned
+brw_get_vertex_surface_type(struct brw_context *brw,
+                            const struct gl_client_array *glarray)
 {
    int size = glarray->Size;
 
@@ -342,7 +342,8 @@ get_surface_type(struct brw_context *brw,
    }
 }
 
-static GLuint get_index_type(GLenum type)
+unsigned
+brw_get_index_type(GLenum type)
 {
    switch (type) {
    case GL_UNSIGNED_BYTE:  return BRW_INDEX_BYTE;
@@ -399,7 +400,7 @@ copy_array_to_vbo_array(struct brw_context *brw,
 
 static void brw_prepare_vertices(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->ctx;
    /* CACHE_NEW_VS_PROG */
    GLbitfield64 vs_inputs = brw->vs.prog_data->inputs_read;
    const unsigned char *ptr = NULL;
@@ -658,6 +659,9 @@ static void brw_emit_vertices(struct brw_context *brw)
         if (brw->gen >= 7)
            dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
 
+         if (brw->gen == 7)
+           dw0 |= GEN7_MOCS_L3 << 16;
+
         OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
         OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
         if (brw->gen >= 5) {
@@ -684,7 +688,7 @@ static void brw_emit_vertices(struct brw_context *brw)
    OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
    for (i = 0; i < brw->vb.nr_enabled; i++) {
       struct brw_vertex_element *input = brw->vb.enabled[i];
-      uint32_t format = get_surface_type(brw, input->glarray);
+      uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
       uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
       uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
       uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
@@ -745,7 +749,8 @@ static void brw_emit_vertices(struct brw_context *brw)
    }
 
    if (brw->gen >= 6 && gen6_edgeflag_input) {
-      uint32_t format = get_surface_type(brw, gen6_edgeflag_input->glarray);
+      uint32_t format =
+         brw_get_vertex_surface_type(brw, gen6_edgeflag_input->glarray);
 
       OUT_BATCH((gen6_edgeflag_input->buffer << GEN6_VE0_INDEX_SHIFT) |
                 GEN6_VE0_VALID |
@@ -795,7 +800,7 @@ const struct brw_tracked_state brw_vertices = {
 
 static void brw_upload_indices(struct brw_context *brw)
 {
-   struct gl_context *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->ctx;
    const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
    GLuint ib_size;
    drm_intel_bo *bo = NULL;
@@ -897,7 +902,7 @@ static void brw_emit_index_buffer(struct brw_context *brw)
    BEGIN_BATCH(3);
    OUT_BATCH(CMD_INDEX_BUFFER << 16 |
              cut_index_setting |
-             get_index_type(index_buffer->type) << 8 |
+             brw_get_index_type(index_buffer->type) << 8 |
              1);
    OUT_RELOC(brw->ib.bo,
              I915_GEM_DOMAIN_VERTEX, 0,