* the appopriate hardware surface type.
* Format will be GL_RGBA or possibly GL_BGRA for GLubyte[4] color arrays.
*/
-static unsigned
-get_surface_type(struct intel_context *intel,
- const struct gl_client_array *glarray)
+unsigned
+brw_get_vertex_surface_type(struct brw_context *brw,
+ const struct gl_client_array *glarray)
{
int size = glarray->Size;
else {
return ubyte_types_norm[size];
}
+ case GL_FIXED:
+ if (brw->gen >= 8 || brw->is_haswell)
+ return fixed_point_types[size];
+
+ /* This produces GL_FIXED inputs as values between INT32_MIN and
+ * INT32_MAX, which will be scaled down by 1/65536 by the VS.
+ */
+ return int_types_scale[size];
/* See GL_ARB_vertex_type_2_10_10_10_rev.
* W/A: Pre-Haswell, the hardware doesn't really support the formats we'd
* like to use here, so upload everything as UINT and fix
*/
case GL_INT_2_10_10_10_REV:
assert(size == 4);
- if (intel->gen >= 8 || intel->is_haswell) {
+ if (brw->gen >= 8 || brw->is_haswell) {
return glarray->Format == GL_BGRA
? BRW_SURFACEFORMAT_B10G10R10A2_SNORM
: BRW_SURFACEFORMAT_R10G10B10A2_SNORM;
return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
case GL_UNSIGNED_INT_2_10_10_10_REV:
assert(size == 4);
- if (intel->gen >= 8 || intel->is_haswell) {
+ if (brw->gen >= 8 || brw->is_haswell) {
return glarray->Format == GL_BGRA
? BRW_SURFACEFORMAT_B10G10R10A2_UNORM
: BRW_SURFACEFORMAT_R10G10B10A2_UNORM;
*/
if (glarray->Type == GL_INT_2_10_10_10_REV) {
assert(size == 4);
- if (intel->gen >= 8 || intel->is_haswell) {
+ if (brw->gen >= 8 || brw->is_haswell) {
return glarray->Format == GL_BGRA
? BRW_SURFACEFORMAT_B10G10R10A2_SSCALED
: BRW_SURFACEFORMAT_R10G10B10A2_SSCALED;
return BRW_SURFACEFORMAT_R10G10B10A2_UINT;
} else if (glarray->Type == GL_UNSIGNED_INT_2_10_10_10_REV) {
assert(size == 4);
- if (intel->gen >= 8 || intel->is_haswell) {
+ if (brw->gen >= 8 || brw->is_haswell) {
return glarray->Format == GL_BGRA
? BRW_SURFACEFORMAT_B10G10R10A2_USCALED
: BRW_SURFACEFORMAT_R10G10B10A2_USCALED;
case GL_UNSIGNED_SHORT: return ushort_types_scale[size];
case GL_UNSIGNED_BYTE: return ubyte_types_scale[size];
case GL_FIXED:
- if (intel->gen >= 8 || intel->is_haswell)
+ if (brw->gen >= 8 || brw->is_haswell)
return fixed_point_types[size];
/* This produces GL_FIXED inputs as values between INT32_MIN and
}
}
-static GLuint get_index_type(GLenum type)
+unsigned
+brw_get_index_type(GLenum type)
{
switch (type) {
case GL_UNSIGNED_BYTE: return BRW_INDEX_BYTE;
* to replicate it out.
*/
if (src_stride == 0) {
- intel_upload_data(&brw->intel, element->glarray->Ptr,
+ intel_upload_data(brw, element->glarray->Ptr,
element->glarray->_ElementSize,
element->glarray->_ElementSize,
&buffer->bo, &buffer->offset);
GLuint size = count * dst_stride;
if (dst_stride == src_stride) {
- intel_upload_data(&brw->intel, src, size, dst_stride,
+ intel_upload_data(brw, src, size, dst_stride,
&buffer->bo, &buffer->offset);
} else {
- char * const map = intel_upload_map(&brw->intel, size, dst_stride);
+ char * const map = intel_upload_map(brw, size, dst_stride);
char *dst = map;
while (count--) {
src += src_stride;
dst += dst_stride;
}
- intel_upload_unmap(&brw->intel, map, size, dst_stride,
+ intel_upload_unmap(brw, map, size, dst_stride,
&buffer->bo, &buffer->offset);
}
buffer->stride = dst_stride;
static void brw_prepare_vertices(struct brw_context *brw)
{
- struct gl_context *ctx = &brw->intel.ctx;
- struct intel_context *intel = intel_context(ctx);
+ struct gl_context *ctx = &brw->ctx;
/* CACHE_NEW_VS_PROG */
GLbitfield64 vs_inputs = brw->vs.prog_data->inputs_read;
const unsigned char *ptr = NULL;
* is passed sideband through the fixed function units. So, we need to
* prepare the vertex buffer for it, but it's not present in inputs_read.
*/
- if (intel->gen >= 6 && (ctx->Polygon.FrontMode != GL_FILL ||
+ if (brw->gen >= 6 && (ctx->Polygon.FrontMode != GL_FILL ||
ctx->Polygon.BackMode != GL_FILL)) {
vs_inputs |= VERT_BIT_EDGEFLAG;
}
struct brw_vertex_buffer *buffer = &brw->vb.buffers[j];
/* Named buffer object: Just reference its contents directly. */
- buffer->bo = intel_bufferobj_source(intel,
+ buffer->bo = intel_bufferobj_source(brw,
intel_buffer, 1,
&buffer->offset);
drm_intel_bo_reference(buffer->bo);
ptr = glarray->Ptr;
}
else if (interleaved != glarray->StrideB ||
- (uintptr_t)(glarray->Ptr - ptr) > interleaved)
+ glarray->Ptr < ptr ||
+ (uintptr_t)(glarray->Ptr - ptr) + glarray->_ElementSize > interleaved)
{
+ /* If our stride is different from the first attribute's stride,
+ * or if the first attribute's stride didn't cover our element,
+ * disable the interleaved upload optimization. The second case
+ * can most commonly occur in cases where there is a single vertex
+ * and, for example, the data is stored on the application's
+ * stack.
+ *
+ * NOTE: This will also disable the optimization in cases where
+ * the data is in a different order than the array indices.
+ * Something like:
+ *
+ * float data[...];
+ * glVertexAttribPointer(0, 4, GL_FLOAT, 32, &data[4]);
+ * glVertexAttribPointer(1, 4, GL_FLOAT, 32, &data[0]);
+ */
interleaved = 0;
}
static void brw_emit_vertices(struct brw_context *brw)
{
- struct gl_context *ctx = &brw->intel.ctx;
- struct intel_context *intel = intel_context(ctx);
GLuint i, nr_elements;
brw_prepare_vertices(brw);
if (nr_elements == 0) {
BEGIN_BATCH(3);
OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | 1);
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
OUT_BATCH((0 << GEN6_VE0_INDEX_SHIFT) |
GEN6_VE0_VALID |
(BRW_SURFACEFORMAT_R32G32B32A32_FLOAT << BRW_VE0_FORMAT_SHIFT) |
*/
if (brw->vb.nr_buffers) {
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
assert(brw->vb.nr_buffers <= 33);
} else {
assert(brw->vb.nr_buffers <= 17);
struct brw_vertex_buffer *buffer = &brw->vb.buffers[i];
uint32_t dw0;
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
dw0 = buffer->step_rate
? GEN6_VB0_ACCESS_INSTANCEDATA
: GEN6_VB0_ACCESS_VERTEXDATA;
dw0 |= i << BRW_VB0_INDEX_SHIFT;
}
- if (intel->gen >= 7)
+ if (brw->gen >= 7)
dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
+ if (brw->gen == 7)
+ dw0 |= GEN7_MOCS_L3 << 16;
+
OUT_BATCH(dw0 | (buffer->stride << BRW_VB0_PITCH_SHIFT));
OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->offset);
- if (intel->gen >= 5) {
+ if (brw->gen >= 5) {
OUT_RELOC(buffer->bo, I915_GEM_DOMAIN_VERTEX, 0, buffer->bo->size - 1);
} else
OUT_BATCH(0);
/* The hardware allows one more VERTEX_ELEMENTS than VERTEX_BUFFERS, presumably
* for VertexID/InstanceID.
*/
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
assert(nr_elements <= 34);
} else {
assert(nr_elements <= 18);
OUT_BATCH((_3DSTATE_VERTEX_ELEMENTS << 16) | (2 * nr_elements - 1));
for (i = 0; i < brw->vb.nr_enabled; i++) {
struct brw_vertex_element *input = brw->vb.enabled[i];
- uint32_t format = get_surface_type(intel, input->glarray);
+ uint32_t format = brw_get_vertex_surface_type(brw, input->glarray);
uint32_t comp0 = BRW_VE1_COMPONENT_STORE_SRC;
uint32_t comp1 = BRW_VE1_COMPONENT_STORE_SRC;
uint32_t comp2 = BRW_VE1_COMPONENT_STORE_SRC;
* of in the VUE. We have to upload it sideband as the last vertex
* element according to the B-Spec.
*/
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
gen6_edgeflag_input = input;
continue;
}
break;
}
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
OUT_BATCH((input->buffer << GEN6_VE0_INDEX_SHIFT) |
GEN6_VE0_VALID |
(format << BRW_VE0_FORMAT_SHIFT) |
(input->offset << BRW_VE0_SRC_OFFSET_SHIFT));
}
- if (intel->gen >= 5)
+ if (brw->gen >= 5)
OUT_BATCH((comp0 << BRW_VE1_COMPONENT_0_SHIFT) |
(comp1 << BRW_VE1_COMPONENT_1_SHIFT) |
(comp2 << BRW_VE1_COMPONENT_2_SHIFT) |
((i * 4) << BRW_VE1_DST_OFFSET_SHIFT));
}
- if (intel->gen >= 6 && gen6_edgeflag_input) {
- uint32_t format = get_surface_type(intel, gen6_edgeflag_input->glarray);
+ if (brw->gen >= 6 && gen6_edgeflag_input) {
+ uint32_t format =
+ brw_get_vertex_surface_type(brw, gen6_edgeflag_input->glarray);
OUT_BATCH((gen6_edgeflag_input->buffer << GEN6_VE0_INDEX_SHIFT) |
GEN6_VE0_VALID |
(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_2_SHIFT) |
(BRW_VE1_COMPONENT_STORE_0 << BRW_VE1_COMPONENT_3_SHIFT));
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
dw0 |= GEN6_VE0_VALID;
} else {
dw0 |= BRW_VE0_VALID;
static void brw_upload_indices(struct brw_context *brw)
{
- struct gl_context *ctx = &brw->intel.ctx;
- struct intel_context *intel = &brw->intel;
+ struct gl_context *ctx = &brw->ctx;
const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
GLuint ib_size;
drm_intel_bo *bo = NULL;
/* Get new bufferobj, offset:
*/
- intel_upload_data(&brw->intel, index_buffer->ptr, ib_size, ib_type_size,
+ intel_upload_data(brw, index_buffer->ptr, ib_size, ib_type_size,
&bo, &offset);
brw->ib.start_vertex_offset = offset / ib_type_size;
} else {
GL_MAP_READ_BIT,
bufferobj);
- intel_upload_data(&brw->intel, map, ib_size, ib_type_size,
- &bo, &offset);
+ intel_upload_data(brw, map, ib_size, ib_type_size, &bo, &offset);
brw->ib.start_vertex_offset = offset / ib_type_size;
ctx->Driver.UnmapBuffer(ctx, bufferobj);
*/
brw->ib.start_vertex_offset = offset / ib_type_size;
- bo = intel_bufferobj_source(intel,
+ bo = intel_bufferobj_source(brw,
intel_buffer_object(bufferobj),
ib_type_size,
&offset);
static void brw_emit_index_buffer(struct brw_context *brw)
{
- struct intel_context *intel = &brw->intel;
const struct _mesa_index_buffer *index_buffer = brw->ib.ib;
GLuint cut_index_setting;
if (index_buffer == NULL)
return;
- if (brw->prim_restart.enable_cut_index && !intel->is_haswell) {
+ if (brw->prim_restart.enable_cut_index && !brw->is_haswell) {
cut_index_setting = BRW_CUT_INDEX_ENABLE;
} else {
cut_index_setting = 0;
BEGIN_BATCH(3);
OUT_BATCH(CMD_INDEX_BUFFER << 16 |
cut_index_setting |
- get_index_type(index_buffer->type) << 8 |
+ brw_get_index_type(index_buffer->type) << 8 |
1);
OUT_RELOC(brw->ib.bo,
I915_GEM_DOMAIN_VERTEX, 0,
projects / mesa.git / blobdiff