/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
develop this 3D driver.
-
+
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
-
+
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
-
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
+
**********************************************************************/
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
-
+
#include "brw_context.h"
#include "brw_defines.h"
#include "brw_eu.h"
+#include "util/ralloc.h"
+
+/**
+ * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
+ *
+ * This is different than reg_encoding from brw_disasm.c in that it operates
+ * on the abstract enum values, rather than the generation-specific encoding.
+ */
+const char *
+brw_reg_type_letters(unsigned type)
+{
+ const char *names[] = {
+ [BRW_REGISTER_TYPE_UD] = "UD",
+ [BRW_REGISTER_TYPE_D] = "D",
+ [BRW_REGISTER_TYPE_UW] = "UW",
+ [BRW_REGISTER_TYPE_W] = "W",
+ [BRW_REGISTER_TYPE_F] = "F",
+ [BRW_REGISTER_TYPE_UB] = "UB",
+ [BRW_REGISTER_TYPE_B] = "B",
+ [BRW_REGISTER_TYPE_UV] = "UV",
+ [BRW_REGISTER_TYPE_V] = "V",
+ [BRW_REGISTER_TYPE_VF] = "VF",
+ [BRW_REGISTER_TYPE_DF] = "DF",
+ [BRW_REGISTER_TYPE_HF] = "HF",
+ [BRW_REGISTER_TYPE_UQ] = "UQ",
+ [BRW_REGISTER_TYPE_Q] = "Q",
+ };
+ assert(type <= BRW_REGISTER_TYPE_Q);
+ return names[type];
+}
+/* Returns a conditional modifier that negates the condition. */
+enum brw_conditional_mod
+brw_negate_cmod(uint32_t cmod)
+{
+ switch (cmod) {
+ case BRW_CONDITIONAL_Z:
+ return BRW_CONDITIONAL_NZ;
+ case BRW_CONDITIONAL_NZ:
+ return BRW_CONDITIONAL_Z;
+ case BRW_CONDITIONAL_G:
+ return BRW_CONDITIONAL_LE;
+ case BRW_CONDITIONAL_GE:
+ return BRW_CONDITIONAL_L;
+ case BRW_CONDITIONAL_L:
+ return BRW_CONDITIONAL_GE;
+ case BRW_CONDITIONAL_LE:
+ return BRW_CONDITIONAL_G;
+ default:
+ return ~0;
+ }
+}
-/* How does predicate control work when execution_size != 8? Do I
- * need to test/set for 0xffff when execution_size is 16?
+/* Returns the corresponding conditional mod for swapping src0 and
+ * src1 in e.g. CMP.
*/
-void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
+enum brw_conditional_mod
+brw_swap_cmod(uint32_t cmod)
{
- p->current->header.predicate_control = BRW_PREDICATE_NONE;
-
- if (value != 0xff) {
- if (value != p->flag_value) {
- brw_push_insn_state(p);
- brw_MOV(p, brw_flag_reg(), brw_imm_uw(value));
- p->flag_value = value;
- brw_pop_insn_state(p);
- }
+ switch (cmod) {
+ case BRW_CONDITIONAL_Z:
+ case BRW_CONDITIONAL_NZ:
+ return cmod;
+ case BRW_CONDITIONAL_G:
+ return BRW_CONDITIONAL_L;
+ case BRW_CONDITIONAL_GE:
+ return BRW_CONDITIONAL_LE;
+ case BRW_CONDITIONAL_L:
+ return BRW_CONDITIONAL_G;
+ case BRW_CONDITIONAL_LE:
+ return BRW_CONDITIONAL_GE;
+ default:
+ return BRW_CONDITIONAL_NONE;
+ }
+}
+
+void
+brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
+{
+ brw_inst_set_exec_size(p->devinfo, p->current, value);
+}
- p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
- }
+void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
+{
+ brw_inst_set_pred_control(p->devinfo, p->current, pc);
}
-void brw_set_predicate_control( struct brw_compile *p, GLuint pc )
+void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
{
- p->current->header.predicate_control = pc;
+ brw_inst_set_pred_inv(p->devinfo, p->current, predicate_inverse);
}
-void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional )
+void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
{
- p->current->header.destreg__conditionalmod = conditional;
+ if (p->devinfo->gen >= 7)
+ brw_inst_set_flag_reg_nr(p->devinfo, p->current, reg);
+
+ brw_inst_set_flag_subreg_nr(p->devinfo, p->current, subreg);
}
-void brw_set_access_mode( struct brw_compile *p, GLuint access_mode )
+void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
{
- p->current->header.access_mode = access_mode;
+ brw_inst_set_access_mode(p->devinfo, p->current, access_mode);
}
-void brw_set_compression_control( struct brw_compile *p, GLboolean compression_control )
+void
+brw_set_default_compression_control(struct brw_codegen *p,
+ enum brw_compression compression_control)
{
p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
- if (p->brw->intel.gen >= 6) {
- /* Since we don't use the 32-wide support in gen6, we translate
+ if (p->devinfo->gen >= 6) {
+ /* Since we don't use the SIMD32 support in gen6, we translate
* the pre-gen6 compression control here.
*/
switch (compression_control) {
/* This is the "use the first set of bits of dmask/vmask/arf
* according to execsize" option.
*/
- p->current->header.compression_control = GEN6_COMPRESSION_1Q;
+ brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1Q);
break;
case BRW_COMPRESSION_2NDHALF:
- /* For 8-wide, this is "use the second set of 8 bits." */
- p->current->header.compression_control = GEN6_COMPRESSION_2Q;
+ /* For SIMD8, this is "use the second set of 8 bits." */
+ brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_2Q);
break;
case BRW_COMPRESSION_COMPRESSED:
- /* For 16-wide instruction compression, use the first set of 16 bits
- * since we don't do 32-wide dispatch.
+ /* For SIMD16 instruction compression, use the first set of 16 bits
+ * since we don't do SIMD32 dispatch.
*/
- p->current->header.compression_control = GEN6_COMPRESSION_1H;
+ brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1H);
break;
default:
- assert(!"not reached");
- p->current->header.compression_control = GEN6_COMPRESSION_1H;
- break;
+ unreachable("not reached");
}
} else {
- p->current->header.compression_control = compression_control;
+ brw_inst_set_qtr_control(p->devinfo, p->current, compression_control);
}
}
-void brw_set_mask_control( struct brw_compile *p, GLuint value )
+void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
{
- p->current->header.mask_control = value;
+ brw_inst_set_mask_control(p->devinfo, p->current, value);
}
-void brw_set_saturate( struct brw_compile *p, GLuint value )
+void brw_set_default_saturate( struct brw_codegen *p, bool enable )
{
- p->current->header.saturate = value;
+ brw_inst_set_saturate(p->devinfo, p->current, enable);
}
-void brw_set_acc_write_control(struct brw_compile *p, GLuint value)
+void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
{
- if (p->brw->intel.gen >= 6)
- p->current->header.acc_wr_control = value;
+ if (p->devinfo->gen >= 6)
+ brw_inst_set_acc_wr_control(p->devinfo, p->current, value);
}
-void brw_push_insn_state( struct brw_compile *p )
+void brw_push_insn_state( struct brw_codegen *p )
{
assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
- memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
+ memcpy(p->current + 1, p->current, sizeof(brw_inst));
p->compressed_stack[p->current - p->stack] = p->compressed;
- p->current++;
+ p->current++;
}
-void brw_pop_insn_state( struct brw_compile *p )
+void brw_pop_insn_state( struct brw_codegen *p )
{
assert(p->current != p->stack);
p->current--;
/***********************************************************************
*/
-void brw_init_compile( struct brw_context *brw, struct brw_compile *p )
+void
+brw_init_codegen(const struct brw_device_info *devinfo,
+ struct brw_codegen *p, void *mem_ctx)
{
- p->brw = brw;
+ memset(p, 0, sizeof(*p));
+
+ p->devinfo = devinfo;
+ /*
+ * Set the initial instruction store array size to 1024, if found that
+ * isn't enough, then it will double the store size at brw_next_insn()
+ * until out of memory.
+ */
+ p->store_size = 1024;
+ p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
p->nr_insn = 0;
p->current = p->stack;
p->compressed = false;
memset(p->current, 0, sizeof(p->current[0]));
+ p->mem_ctx = mem_ctx;
+
/* Some defaults?
*/
- brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
- brw_set_saturate(p, 0);
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_set_predicate_control_flag_value(p, 0xff);
+ brw_set_default_exec_size(p, BRW_EXECUTE_8);
+ brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
+ brw_set_default_saturate(p, 0);
+ brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
+
+ /* Set up control flow stack */
+ p->if_stack_depth = 0;
+ p->if_stack_array_size = 16;
+ p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
+
+ p->loop_stack_depth = 0;
+ p->loop_stack_array_size = 16;
+ p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
+ p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
+
+ brw_init_compaction_tables(devinfo);
}
-const GLuint *brw_get_program( struct brw_compile *p,
- GLuint *sz )
-{
- GLuint i;
-
- for (i = 0; i < 8; i++)
- brw_NOP(p);
-
- *sz = p->nr_insn * sizeof(struct brw_instruction);
- return (const GLuint *)p->store;
-}
-
-
-
-/**
- * Subroutine calls require special attention.
- * Mesa instructions may be expanded into multiple hardware instructions
- * so the prog_instruction::BranchTarget field can't be used as an index
- * into the hardware instructions.
- *
- * The BranchTarget field isn't needed, however. Mesa's GLSL compiler
- * emits CAL and BGNSUB instructions with labels that can be used to map
- * subroutine calls to actual subroutine code blocks.
- *
- * The structures and function here implement patching of CAL instructions
- * so they jump to the right subroutine code...
- */
-
-
-/**
- * For each OPCODE_BGNSUB we create one of these.
- */
-struct brw_glsl_label
-{
- const char *name; /**< the label string */
- GLuint position; /**< the position of the brw instruction for this label */
- struct brw_glsl_label *next; /**< next in linked list */
-};
-
-
-/**
- * For each OPCODE_CAL we create one of these.
- */
-struct brw_glsl_call
-{
- GLuint call_inst_pos; /**< location of the CAL instruction */
- const char *sub_name; /**< name of subroutine to call */
- struct brw_glsl_call *next; /**< next in linked list */
-};
-
-
-/**
- * Called for each OPCODE_BGNSUB.
- */
-void
-brw_save_label(struct brw_compile *c, const char *name, GLuint position)
+const unsigned *brw_get_program( struct brw_codegen *p,
+ unsigned *sz )
{
- struct brw_glsl_label *label = CALLOC_STRUCT(brw_glsl_label);
- label->name = name;
- label->position = position;
- label->next = c->first_label;
- c->first_label = label;
+ *sz = p->next_insn_offset;
+ return (const unsigned *)p->store;
}
-
-/**
- * Called for each OPCODE_CAL.
- */
void
-brw_save_call(struct brw_compile *c, const char *name, GLuint call_pos)
-{
- struct brw_glsl_call *call = CALLOC_STRUCT(brw_glsl_call);
- call->call_inst_pos = call_pos;
- call->sub_name = name;
- call->next = c->first_call;
- c->first_call = call;
-}
-
-
-/**
- * Lookup a label, return label's position/offset.
- */
-static GLuint
-brw_lookup_label(struct brw_compile *c, const char *name)
+brw_disassemble(const struct brw_device_info *devinfo,
+ void *assembly, int start, int end, FILE *out)
{
- const struct brw_glsl_label *label;
- for (label = c->first_label; label; label = label->next) {
- if (strcmp(name, label->name) == 0) {
- return label->position;
+ bool dump_hex = false;
+
+ for (int offset = start; offset < end;) {
+ brw_inst *insn = assembly + offset;
+ brw_inst uncompacted;
+ bool compacted = brw_inst_cmpt_control(devinfo, insn);
+ if (0)
+ fprintf(out, "0x%08x: ", offset);
+
+ if (compacted) {
+ brw_compact_inst *compacted = (void *)insn;
+ if (dump_hex) {
+ fprintf(out, "0x%08x 0x%08x ",
+ ((uint32_t *)insn)[1],
+ ((uint32_t *)insn)[0]);
+ }
+
+ brw_uncompact_instruction(devinfo, &uncompacted, compacted);
+ insn = &uncompacted;
+ offset += 8;
+ } else {
+ if (dump_hex) {
+ fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
+ ((uint32_t *)insn)[3],
+ ((uint32_t *)insn)[2],
+ ((uint32_t *)insn)[1],
+ ((uint32_t *)insn)[0]);
+ }
+ offset += 16;
}
- }
- abort(); /* should never happen */
- return ~0;
-}
-
-/**
- * When we're done generating code, this function is called to resolve
- * subroutine calls.
- */
-void
-brw_resolve_cals(struct brw_compile *c)
-{
- const struct brw_glsl_call *call;
-
- for (call = c->first_call; call; call = call->next) {
- const GLuint sub_loc = brw_lookup_label(c, call->sub_name);
- struct brw_instruction *brw_call_inst = &c->store[call->call_inst_pos];
- struct brw_instruction *brw_sub_inst = &c->store[sub_loc];
- GLint offset = brw_sub_inst - brw_call_inst;
-
- /* patch brw_inst1 to point to brw_inst2 */
- brw_set_src1(brw_call_inst, brw_imm_d(offset * 16));
- }
-
- /* free linked list of calls */
- {
- struct brw_glsl_call *call, *next;
- for (call = c->first_call; call; call = next) {
- next = call->next;
- free(call);
- }
- c->first_call = NULL;
- }
-
- /* free linked list of labels */
- {
- struct brw_glsl_label *label, *next;
- for (label = c->first_label; label; label = next) {
- next = label->next;
- free(label);
- }
- c->first_label = NULL;
- }
+ brw_disassemble_inst(out, devinfo, insn, compacted);
+ }
}
projects / mesa.git / blobdiff