/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
develop this 3D driver.
Permission is hereby granted, free of charge, to any person obtaining
**********************************************************************/
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
#include "brw_defines.h"
#include "brw_eu.h"
-#include "glsl/ralloc.h"
+#include "util/ralloc.h"
+
+/**
+ * Converts a BRW_REGISTER_TYPE_* enum to a short string (F, UD, and so on).
+ *
+ * This is different than reg_encoding from brw_disasm.c in that it operates
+ * on the abstract enum values, rather than the generation-specific encoding.
+ */
+const char *
+brw_reg_type_letters(unsigned type)
+{
+ const char *names[] = {
+ [BRW_REGISTER_TYPE_UD] = "UD",
+ [BRW_REGISTER_TYPE_D] = "D",
+ [BRW_REGISTER_TYPE_UW] = "UW",
+ [BRW_REGISTER_TYPE_W] = "W",
+ [BRW_REGISTER_TYPE_F] = "F",
+ [BRW_REGISTER_TYPE_UB] = "UB",
+ [BRW_REGISTER_TYPE_B] = "B",
+ [BRW_REGISTER_TYPE_UV] = "UV",
+ [BRW_REGISTER_TYPE_V] = "V",
+ [BRW_REGISTER_TYPE_VF] = "VF",
+ [BRW_REGISTER_TYPE_DF] = "DF",
+ [BRW_REGISTER_TYPE_HF] = "HF",
+ [BRW_REGISTER_TYPE_UQ] = "UQ",
+ [BRW_REGISTER_TYPE_Q] = "Q",
+ };
+ assert(type <= BRW_REGISTER_TYPE_Q);
+ return names[type];
+}
+
+/* Returns a conditional modifier that negates the condition. */
+enum brw_conditional_mod
+brw_negate_cmod(uint32_t cmod)
+{
+ switch (cmod) {
+ case BRW_CONDITIONAL_Z:
+ return BRW_CONDITIONAL_NZ;
+ case BRW_CONDITIONAL_NZ:
+ return BRW_CONDITIONAL_Z;
+ case BRW_CONDITIONAL_G:
+ return BRW_CONDITIONAL_LE;
+ case BRW_CONDITIONAL_GE:
+ return BRW_CONDITIONAL_L;
+ case BRW_CONDITIONAL_L:
+ return BRW_CONDITIONAL_GE;
+ case BRW_CONDITIONAL_LE:
+ return BRW_CONDITIONAL_G;
+ default:
+ return ~0;
+ }
+}
/* Returns the corresponding conditional mod for swapping src0 and
* src1 in e.g. CMP.
*/
-uint32_t
+enum brw_conditional_mod
brw_swap_cmod(uint32_t cmod)
{
switch (cmod) {
case BRW_CONDITIONAL_LE:
return BRW_CONDITIONAL_GE;
default:
- return ~0;
+ return BRW_CONDITIONAL_NONE;
}
}
-
-/* How does predicate control work when execution_size != 8? Do I
- * need to test/set for 0xffff when execution_size is 16?
- */
-void brw_set_predicate_control_flag_value( struct brw_compile *p, unsigned value )
+void
+brw_set_default_exec_size(struct brw_codegen *p, unsigned value)
{
- p->current->header.predicate_control = BRW_PREDICATE_NONE;
-
- if (value != 0xff) {
- if (value != p->flag_value) {
- brw_push_insn_state(p);
- brw_MOV(p, brw_flag_reg(0, 0), brw_imm_uw(value));
- p->flag_value = value;
- brw_pop_insn_state(p);
- }
-
- p->current->header.predicate_control = BRW_PREDICATE_NORMAL;
- }
+ brw_inst_set_exec_size(p->devinfo, p->current, value);
}
-void brw_set_predicate_control( struct brw_compile *p, unsigned pc )
+void brw_set_default_predicate_control( struct brw_codegen *p, unsigned pc )
{
- p->current->header.predicate_control = pc;
+ brw_inst_set_pred_control(p->devinfo, p->current, pc);
}
-void brw_set_predicate_inverse(struct brw_compile *p, bool predicate_inverse)
+void brw_set_default_predicate_inverse(struct brw_codegen *p, bool predicate_inverse)
{
- p->current->header.predicate_inverse = predicate_inverse;
+ brw_inst_set_pred_inv(p->devinfo, p->current, predicate_inverse);
}
-void brw_set_conditionalmod( struct brw_compile *p, unsigned conditional )
+void brw_set_default_flag_reg(struct brw_codegen *p, int reg, int subreg)
{
- p->current->header.destreg__conditionalmod = conditional;
-}
+ if (p->devinfo->gen >= 7)
+ brw_inst_set_flag_reg_nr(p->devinfo, p->current, reg);
-void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg)
-{
- p->current->bits2.da1.flag_reg_nr = reg;
- p->current->bits2.da1.flag_subreg_nr = subreg;
+ brw_inst_set_flag_subreg_nr(p->devinfo, p->current, subreg);
}
-void brw_set_access_mode( struct brw_compile *p, unsigned access_mode )
+void brw_set_default_access_mode( struct brw_codegen *p, unsigned access_mode )
{
- p->current->header.access_mode = access_mode;
+ brw_inst_set_access_mode(p->devinfo, p->current, access_mode);
}
void
-brw_set_compression_control(struct brw_compile *p,
+brw_set_default_compression_control(struct brw_codegen *p,
enum brw_compression compression_control)
{
p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
- if (p->brw->gen >= 6) {
- /* Since we don't use the 32-wide support in gen6, we translate
+ if (p->devinfo->gen >= 6) {
+ /* Since we don't use the SIMD32 support in gen6, we translate
* the pre-gen6 compression control here.
*/
switch (compression_control) {
/* This is the "use the first set of bits of dmask/vmask/arf
* according to execsize" option.
*/
- p->current->header.compression_control = GEN6_COMPRESSION_1Q;
+ brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1Q);
break;
case BRW_COMPRESSION_2NDHALF:
- /* For 8-wide, this is "use the second set of 8 bits." */
- p->current->header.compression_control = GEN6_COMPRESSION_2Q;
+ /* For SIMD8, this is "use the second set of 8 bits." */
+ brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_2Q);
break;
case BRW_COMPRESSION_COMPRESSED:
- /* For 16-wide instruction compression, use the first set of 16 bits
- * since we don't do 32-wide dispatch.
+ /* For SIMD16 instruction compression, use the first set of 16 bits
+ * since we don't do SIMD32 dispatch.
*/
- p->current->header.compression_control = GEN6_COMPRESSION_1H;
+ brw_inst_set_qtr_control(p->devinfo, p->current, GEN6_COMPRESSION_1H);
break;
default:
- assert(!"not reached");
- p->current->header.compression_control = GEN6_COMPRESSION_1H;
- break;
+ unreachable("not reached");
}
} else {
- p->current->header.compression_control = compression_control;
+ brw_inst_set_qtr_control(p->devinfo, p->current, compression_control);
}
}
-void brw_set_mask_control( struct brw_compile *p, unsigned value )
+void brw_set_default_mask_control( struct brw_codegen *p, unsigned value )
{
- p->current->header.mask_control = value;
+ brw_inst_set_mask_control(p->devinfo, p->current, value);
}
-void brw_set_saturate( struct brw_compile *p, bool enable )
+void brw_set_default_saturate( struct brw_codegen *p, bool enable )
{
- p->current->header.saturate = enable;
+ brw_inst_set_saturate(p->devinfo, p->current, enable);
}
-void brw_set_acc_write_control(struct brw_compile *p, unsigned value)
+void brw_set_default_acc_write_control(struct brw_codegen *p, unsigned value)
{
- if (p->brw->gen >= 6)
- p->current->header.acc_wr_control = value;
+ if (p->devinfo->gen >= 6)
+ brw_inst_set_acc_wr_control(p->devinfo, p->current, value);
}
-void brw_push_insn_state( struct brw_compile *p )
+void brw_push_insn_state( struct brw_codegen *p )
{
assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
- memcpy(p->current+1, p->current, sizeof(struct brw_instruction));
+ memcpy(p->current + 1, p->current, sizeof(brw_inst));
p->compressed_stack[p->current - p->stack] = p->compressed;
p->current++;
}
-void brw_pop_insn_state( struct brw_compile *p )
+void brw_pop_insn_state( struct brw_codegen *p )
{
assert(p->current != p->stack);
p->current--;
/***********************************************************************
*/
void
-brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
+brw_init_codegen(const struct brw_device_info *devinfo,
+ struct brw_codegen *p, void *mem_ctx)
{
memset(p, 0, sizeof(*p));
- p->brw = brw;
+ p->devinfo = devinfo;
/*
* Set the initial instruction store array size to 1024, if found that
* isn't enough, then it will double the store size at brw_next_insn()
* until out of memory.
*/
p->store_size = 1024;
- p->store = rzalloc_array(mem_ctx, struct brw_instruction, p->store_size);
+ p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
p->nr_insn = 0;
p->current = p->stack;
p->compressed = false;
/* Some defaults?
*/
- brw_set_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
- brw_set_saturate(p, 0);
- brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_set_predicate_control_flag_value(p, 0xff);
+ brw_set_default_exec_size(p, BRW_EXECUTE_8);
+ brw_set_default_mask_control(p, BRW_MASK_ENABLE); /* what does this do? */
+ brw_set_default_saturate(p, 0);
+ brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
/* Set up control flow stack */
p->if_stack_depth = 0;
p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
- brw_init_compaction_tables(brw);
+ brw_init_compaction_tables(devinfo);
}
-const unsigned *brw_get_program( struct brw_compile *p,
+const unsigned *brw_get_program( struct brw_codegen *p,
unsigned *sz )
{
- brw_compact_instructions(p);
-
*sz = p->next_insn_offset;
return (const unsigned *)p->store;
}
void
-brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end)
+brw_disassemble(const struct brw_device_info *devinfo,
+ void *assembly, int start, int end, FILE *out)
{
- struct brw_context *brw = p->brw;
- void *store = p->store;
bool dump_hex = false;
for (int offset = start; offset < end;) {
- struct brw_instruction *insn = store + offset;
- struct brw_instruction uncompacted;
- printf("0x%08x: ", offset);
-
- if (insn->header.cmpt_control) {
- struct brw_compact_instruction *compacted = (void *)insn;
+ brw_inst *insn = assembly + offset;
+ brw_inst uncompacted;
+ bool compacted = brw_inst_cmpt_control(devinfo, insn);
+ if (0)
+ fprintf(out, "0x%08x: ", offset);
+
+ if (compacted) {
+ brw_compact_inst *compacted = (void *)insn;
if (dump_hex) {
- printf("0x%08x 0x%08x ",
- ((uint32_t *)insn)[1],
- ((uint32_t *)insn)[0]);
+ fprintf(out, "0x%08x 0x%08x ",
+ ((uint32_t *)insn)[1],
+ ((uint32_t *)insn)[0]);
}
- brw_uncompact_instruction(brw, &uncompacted, compacted);
+ brw_uncompact_instruction(devinfo, &uncompacted, compacted);
insn = &uncompacted;
offset += 8;
} else {
if (dump_hex) {
- printf("0x%08x 0x%08x 0x%08x 0x%08x ",
- ((uint32_t *)insn)[3],
- ((uint32_t *)insn)[2],
- ((uint32_t *)insn)[1],
- ((uint32_t *)insn)[0]);
+ fprintf(out, "0x%08x 0x%08x 0x%08x 0x%08x ",
+ ((uint32_t *)insn)[3],
+ ((uint32_t *)insn)[2],
+ ((uint32_t *)insn)[1],
+ ((uint32_t *)insn)[0]);
}
offset += 16;
}
- brw_disasm(stdout, insn, p->brw->gen);
+ brw_disassemble_inst(out, devinfo, insn, compacted);
}
}
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