i965: Fix DP write channel ordering on Sandybridge.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu.c

diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index 1df561386e6ad8b6d906ea71e6f4197adf1422d4..4e7c1226ad4dd8b26b1c1a572f85b14bfe01dd36 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -237,7 +237,7 @@ brw_resolve_cals(struct brw_compile *c)
         struct brw_glsl_call *call, *next;
         for (call = c->first_call; call; call = next) {
            next = call->next;
-           _mesa_free(call);
+           free(call);
        }
        c->first_call = NULL;
     }
@@ -247,7 +247,7 @@ brw_resolve_cals(struct brw_compile *c)
         struct brw_glsl_label *label, *next;
        for (label = c->first_label; label; label = next) {
            next = label->next;
-           _mesa_free(label);
+           free(label);
        }
        c->first_label = NULL;
     }