i965: Remove never used RSR and RSL opcodes.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu.c

diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index 130d801edc9e24149cbdd3483232b35b47c906e6..983aa4c4945fda99ec676c5e188f0a136caf1081 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -70,7 +70,7 @@ void brw_set_predicate_control_flag_value( struct brw_compile *p, GLuint value )
    if (value != 0xff) {
       if (value != p->flag_value) {
         brw_push_insn_state(p);
-        brw_MOV(p, brw_flag_reg(), brw_imm_uw(value));
+        brw_MOV(p, brw_flag_reg(0, 0), brw_imm_uw(value));
         p->flag_value = value;
         brw_pop_insn_state(p);
       }
@@ -94,6 +94,12 @@ void brw_set_conditionalmod( struct brw_compile *p, GLuint conditional )
    p->current->header.destreg__conditionalmod = conditional;
 }
 
+void brw_set_flag_reg(struct brw_compile *p, int reg, int subreg)
+{
+   p->current->bits2.da1.flag_reg_nr = reg;
+   p->current->bits2.da1.flag_subreg_nr = subreg;
+}
+
 void brw_set_access_mode( struct brw_compile *p, GLuint access_mode )
 {
    p->current->header.access_mode = access_mode;
@@ -105,7 +111,7 @@ brw_set_compression_control(struct brw_compile *p,
 {
    p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
 
-   if (p->brw->intel.gen >= 6) {
+   if (p->brw->gen >= 6) {
       /* Since we don't use the 32-wide support in gen6, we translate
        * the pre-gen6 compression control here.
        */
@@ -148,7 +154,7 @@ void brw_set_saturate( struct brw_compile *p, bool enable )
 
 void brw_set_acc_write_control(struct brw_compile *p, GLuint value)
 {
-   if (p->brw->intel.gen >= 6)
+   if (p->brw->gen >= 6)
       p->current->header.acc_wr_control = value;
 }
 
@@ -207,23 +213,15 @@ brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
    p->loop_stack = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
    p->if_depth_in_loop = rzalloc_array(mem_ctx, int, p->loop_stack_array_size);
 
-   brw_init_compaction_tables(&brw->intel);
+   brw_init_compaction_tables(brw);
 }
 
 
 const GLuint *brw_get_program( struct brw_compile *p,
                               GLuint *sz )
 {
-   GLuint i;
-
    brw_compact_instructions(p);
 
-   /* We emit a cacheline (8 instructions) of NOPs at the end of the program to
-    * make sure that instruction prefetch doesn't wander off into some other BO.
-    */
-   for (i = 0; i < 8; i++)
-      brw_NOP(p);
-
    *sz = p->next_insn_offset;
    return (const GLuint *)p->store;
 }
@@ -232,7 +230,6 @@ void
 brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end)
 {
    struct brw_context *brw = p->brw;
-   struct intel_context *intel = &brw->intel;
    void *store = p->store;
    bool dump_hex = false;
 
@@ -249,7 +246,7 @@ brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end)
                   ((uint32_t *)insn)[0]);
         }
 
-        brw_uncompact_instruction(intel, &uncompacted, compacted);
+        brw_uncompact_instruction(brw, &uncompacted, compacted);
         insn = &uncompacted;
         offset += 8;
       } else {
@@ -263,6 +260,6 @@ brw_dump_compile(struct brw_compile *p, FILE *out, int start, int end)
         offset += 16;
       }
 
-      brw_disasm(stdout, insn, p->brw->intel.gen);
+      brw_disasm(stdout, insn, p->brw->gen);
    }
 }