i965/nir/vec4: Implement single-element "mov" operations

[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu_compact.c

diff --git a/src/mesa/drivers/dri/i965/brw_eu_compact.c b/src/mesa/drivers/dri/i965/brw_eu_compact.c
index 428cdf4b2056ed05b830abb15446336a6669a615..67f0b45ac04b08f362d7eef7bb10c76d940d8770 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_compact.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_compact.c
@@ -849,6 +849,12 @@ set_3src_source_index(const struct brw_device_info *devinfo,
 static bool
 has_unmapped_bits(const struct brw_device_info *devinfo, brw_inst *src)
 {
+   /* EOT can only be mapped on a send if the src1 is an immediate */
+   if ((brw_inst_opcode(devinfo, src) == BRW_OPCODE_SENDC ||
+        brw_inst_opcode(devinfo, src) == BRW_OPCODE_SEND) &&
+       brw_inst_eot(devinfo, src))
+      return true;
+
    /* Check for instruction bits that don't map to any of the fields of the
     * compacted instruction.  The instruction cannot be compacted if any of
     * them are set.  They overlap with:
@@ -1218,18 +1224,18 @@ brw_uncompact_instruction(const struct brw_device_info *devinfo, brw_inst *dst,
    }
 }
 
-void brw_debug_compact_uncompact(struct brw_context *brw,
+void brw_debug_compact_uncompact(const struct brw_device_info *devinfo,
                                  brw_inst *orig,
                                  brw_inst *uncompacted)
 {
    fprintf(stderr, "Instruction compact/uncompact changed (gen%d):\n",
-           brw->gen);
+           devinfo->gen);
 
    fprintf(stderr, "  before: ");
-   brw_disassemble_inst(stderr, brw, orig, true);
+   brw_disassemble_inst(stderr, devinfo, orig, true);
 
    fprintf(stderr, "  after:  ");
-   brw_disassemble_inst(stderr, brw, uncompacted, false);
+   brw_disassemble_inst(stderr, devinfo, uncompacted, false);
 
    uint32_t *before_bits = (uint32_t *)orig;
    uint32_t *after_bits = (uint32_t *)uncompacted;
@@ -1306,7 +1312,7 @@ update_gen4_jump_count(const struct brw_device_info *devinfo, brw_inst *insn,
 }
 
 void
-brw_init_compaction_tables(struct brw_context *brw)
+brw_init_compaction_tables(const struct brw_device_info *devinfo)
 {
    static bool initialized;
    if (initialized || p_atomic_cmpxchg(&initialized, false, true) != false)
@@ -1329,7 +1335,7 @@ brw_init_compaction_tables(struct brw_context *brw)
    assert(gen8_subreg_table[ARRAY_SIZE(gen8_subreg_table) - 1] != 0);
    assert(gen8_src_index_table[ARRAY_SIZE(gen8_src_index_table) - 1] != 0);
 
-   switch (brw->gen) {
+   switch (devinfo->gen) {
    case 9:
    case 8:
       control_index_table = gen8_control_index_table;
@@ -1362,10 +1368,9 @@ brw_init_compaction_tables(struct brw_context *brw)
 }
 
 void
-brw_compact_instructions(struct brw_compile *p, int start_offset,
+brw_compact_instructions(struct brw_codegen *p, int start_offset,
                          int num_annotations, struct annotation *annotation)
 {
-   struct brw_context *brw = p->brw;
    const struct brw_device_info *devinfo = p->devinfo;
    void *store = p->store + start_offset / 16;
    /* For an instruction at byte offset 16*i before compaction, this is the
@@ -1400,26 +1405,17 @@ brw_compact_instructions(struct brw_compile *p, int start_offset,
             brw_inst uncompacted;
             brw_uncompact_instruction(devinfo, &uncompacted, dst);
             if (memcmp(&saved, &uncompacted, sizeof(uncompacted))) {
-               brw_debug_compact_uncompact(brw, &saved, &uncompacted);
+               brw_debug_compact_uncompact(devinfo, &saved, &uncompacted);
             }
          }
 
          offset += sizeof(brw_compact_inst);
       } else {
-         /* It appears that the end of thread SEND instruction needs to be
-          * aligned, or the GPU hangs. All uncompacted instructions need to be
-          * aligned on G45.
-          */
-         if ((offset & sizeof(brw_compact_inst)) != 0 &&
-             (((brw_inst_opcode(devinfo, src) == BRW_OPCODE_SEND ||
-                brw_inst_opcode(devinfo, src) == BRW_OPCODE_SENDC) &&
-               brw_inst_eot(devinfo, src)) ||
-              devinfo->is_g4x)) {
+         /* All uncompacted instructions need to be aligned on G45. */
+         if ((offset & sizeof(brw_compact_inst)) != 0 && devinfo->is_g4x){
             brw_compact_inst *align = store + offset;
             memset(align, 0, sizeof(*align));
-            brw_compact_inst_set_opcode(align,
-                                        devinfo->is_g4x ? BRW_OPCODE_NENOP :
-                                                          BRW_OPCODE_NOP);
+            brw_compact_inst_set_opcode(align, BRW_OPCODE_NENOP);
             brw_compact_inst_set_cmpt_control(align, true);
             offset += sizeof(brw_compact_inst);
             compacted_count--;