i965: Mostly fix glsl-max-varyings.
[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu_emit.c
index 34490b7f16fc403f74baa98c4ce88604cd146c3f..10e9ebc3b0ecddaaec24717ba107bc0b6071d4c9 100644 (file)
@@ -286,6 +286,7 @@ static void brw_set_ff_sync_message(struct brw_context *brw,
                                    GLuint response_length,
                                    GLboolean end_of_thread)
 {
+       struct intel_context *intel = &brw->intel;
        brw_set_src1(insn, brw_imm_d(0));
 
        insn->bits3.urb_gen5.opcode = 1; /* FF_SYNC */
@@ -298,8 +299,12 @@ static void brw_set_ff_sync_message(struct brw_context *brw,
        insn->bits3.urb_gen5.response_length = response_length; /* may be 1 or 0 */
        insn->bits3.urb_gen5.msg_length = 1;
        insn->bits3.urb_gen5.end_of_thread = end_of_thread;
-       insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
-       insn->bits2.send_gen5.end_of_thread = end_of_thread;
+       if (intel->gen >= 6) {
+          insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_URB;
+       } else {
+          insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
+          insn->bits2.send_gen5.end_of_thread = end_of_thread;
+       }
 }
 
 static void brw_set_urb_message( struct brw_context *brw,
@@ -901,6 +906,20 @@ void brw_CMP(struct brw_compile *p,
    }
 }
 
+/* Issue 'wait' instruction for n1, host could program MMIO
+   to wake up thread. */
+void brw_WAIT (struct brw_compile *p)
+{
+   struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WAIT);
+   struct brw_reg src = brw_notification_1_reg();
+
+   brw_set_dest(insn, src);
+   brw_set_src0(insn, src);
+   brw_set_src1(insn, brw_null_reg());
+   insn->header.execution_size = 0; /* must */
+   insn->header.predicate_control = 0;
+   insn->header.compression_control = 0;
+}
 
 
 /***********************************************************************