i965: Mostly fix glsl-max-varyings.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu_emit.c

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 785d382a009d8f7e772ba6106cf8a790e8bbe057..10e9ebc3b0ecddaaec24717ba107bc0b6071d4c9 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -280,31 +280,31 @@ static void brw_set_math_message( struct brw_context *brw,
 }
 
 
-static void brw_set_ff_sync_message( struct brw_context *brw,
-                                struct brw_instruction *insn,
-                                GLboolean allocate,
-                                GLboolean used,
-                                GLuint msg_length,
-                                GLuint response_length,
-                                GLboolean end_of_thread,
-                                GLboolean complete,
-                                GLuint offset,
-                                GLuint swizzle_control )
+static void brw_set_ff_sync_message(struct brw_context *brw,
+                                   struct brw_instruction *insn,
+                                   GLboolean allocate,
+                                   GLuint response_length,
+                                   GLboolean end_of_thread)
 {
+       struct intel_context *intel = &brw->intel;
        brw_set_src1(insn, brw_imm_d(0));
 
-       insn->bits3.urb_gen5.opcode = 1;
-       insn->bits3.urb_gen5.offset = offset;
-       insn->bits3.urb_gen5.swizzle_control = swizzle_control;
+       insn->bits3.urb_gen5.opcode = 1; /* FF_SYNC */
+       insn->bits3.urb_gen5.offset = 0; /* Not used by FF_SYNC */
+       insn->bits3.urb_gen5.swizzle_control = 0; /* Not used by FF_SYNC */
        insn->bits3.urb_gen5.allocate = allocate;
-       insn->bits3.urb_gen5.used = used;
-       insn->bits3.urb_gen5.complete = complete;
+       insn->bits3.urb_gen5.used = 0; /* Not used by FF_SYNC */
+       insn->bits3.urb_gen5.complete = 0; /* Not used by FF_SYNC */
        insn->bits3.urb_gen5.header_present = 1;
-       insn->bits3.urb_gen5.response_length = response_length;
-       insn->bits3.urb_gen5.msg_length = msg_length;
+       insn->bits3.urb_gen5.response_length = response_length; /* may be 1 or 0 */
+       insn->bits3.urb_gen5.msg_length = 1;
        insn->bits3.urb_gen5.end_of_thread = end_of_thread;
-       insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
-       insn->bits2.send_gen5.end_of_thread = end_of_thread;
+       if (intel->gen >= 6) {
+          insn->header.destreg__conditionalmod = BRW_MESSAGE_TARGET_URB;
+       } else {
+          insn->bits2.send_gen5.sfid = BRW_MESSAGE_TARGET_URB;
+          insn->bits2.send_gen5.end_of_thread = end_of_thread;
+       }
 }
 
 static void brw_set_urb_message( struct brw_context *brw,
@@ -906,6 +906,20 @@ void brw_CMP(struct brw_compile *p,
    }
 }
 
+/* Issue 'wait' instruction for n1, host could program MMIO
+   to wake up thread. */
+void brw_WAIT (struct brw_compile *p)
+{
+   struct brw_instruction *insn = next_insn(p, BRW_OPCODE_WAIT);
+   struct brw_reg src = brw_notification_1_reg();
+
+   brw_set_dest(insn, src);
+   brw_set_src0(insn, src);
+   brw_set_src1(insn, brw_null_reg());
+   insn->header.execution_size = 0; /* must */
+   insn->header.predicate_control = 0;
+   insn->header.compression_control = 0;
+}
 
 
 /***********************************************************************
@@ -971,10 +985,25 @@ void brw_math_16( struct brw_compile *p,
                  struct brw_reg src,
                  GLuint precision )
 {
+   struct intel_context *intel = &p->brw->intel;
    struct brw_instruction *insn;
    GLuint msg_length = (function == BRW_MATH_FUNCTION_POW) ? 2 : 1; 
    GLuint response_length = (function == BRW_MATH_FUNCTION_SINCOS) ? 2 : 1; 
 
+   if (intel->gen >= 6) {
+      insn = next_insn(p, BRW_OPCODE_MATH);
+
+      /* Math is the same ISA format as other opcodes, except that CondModifier
+       * becomes FC[3:0] and ThreadCtrl becomes FC[5:4].
+       */
+      insn->header.destreg__conditionalmod = function;
+
+      brw_set_dest(insn, dest);
+      brw_set_src0(insn, src);
+      brw_set_src1(insn, brw_null_reg());
+      return;
+   }
+
    /* First instruction:
     */
    brw_push_insn_state(p);
@@ -1451,18 +1480,11 @@ void brw_ff_sync(struct brw_compile *p,
                   GLuint msg_reg_nr,
                   struct brw_reg src0,
                   GLboolean allocate,
-                  GLboolean used,
-                  GLuint msg_length,
                   GLuint response_length,
-                  GLboolean eot,
-                  GLboolean writes_complete,
-                  GLuint offset,
-                  GLuint swizzle)
+                  GLboolean eot)
 {
    struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
 
-   assert(msg_length < 16);
-
    brw_set_dest(insn, dest);
    brw_set_src0(insn, src0);
    brw_set_src1(insn, brw_imm_d(0));
@@ -1470,13 +1492,8 @@ void brw_ff_sync(struct brw_compile *p,
    insn->header.destreg__conditionalmod = msg_reg_nr;
 
    brw_set_ff_sync_message(p->brw,
-                      insn,
-                      allocate,
-                      used,
-                      msg_length,
-                      response_length, 
-                      eot, 
-                      writes_complete, 
-                      offset,
-                      swizzle);
+                          insn,
+                          allocate,
+                          response_length,
+                          eot);
 }