* registers required for messages with EOT.
*/
struct brw_context *brw = p->brw;
- if (brw->gen == 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
+ if (brw->gen >= 7 && reg->file == BRW_MESSAGE_REGISTER_FILE) {
reg->file = BRW_GENERAL_REGISTER_FILE;
reg->nr += GEN7_MRF_HACK_START;
}
static void
validate_reg(const struct brw_context *brw, brw_inst *inst, struct brw_reg reg)
{
- int hstride_for_reg[] = {0, 1, 2, 4};
- int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32, 64, 128, 256};
- int width_for_reg[] = {1, 2, 4, 8, 16};
- int execsize_for_reg[] = {1, 2, 4, 8, 16};
+ const int hstride_for_reg[] = {0, 1, 2, 4};
+ const int vstride_for_reg[] = {0, 1, 2, 4, 8, 16, 32};
+ const int width_for_reg[] = {1, 2, 4, 8, 16};
+ const int execsize_for_reg[] = {1, 2, 4, 8, 16};
int width, hstride, vstride, execsize;
if (reg.file == BRW_IMMEDIATE_VALUE) {
reg.file == BRW_ARF_NULL)
return;
- assert(reg.hstride >= 0 && reg.hstride < Elements(hstride_for_reg));
+ assert(reg.hstride >= 0 && reg.hstride < ARRAY_SIZE(hstride_for_reg));
hstride = hstride_for_reg[reg.hstride];
if (reg.vstride == 0xf) {
vstride = -1;
} else {
- assert(reg.vstride >= 0 && reg.vstride < Elements(vstride_for_reg));
+ assert(reg.vstride >= 0 && reg.vstride < ARRAY_SIZE(vstride_for_reg));
vstride = vstride_for_reg[reg.vstride];
}
- assert(reg.width >= 0 && reg.width < Elements(width_for_reg));
+ assert(reg.width >= 0 && reg.width < ARRAY_SIZE(width_for_reg));
width = width_for_reg[reg.width];
assert(brw_inst_exec_size(brw, inst) >= 0 &&
- brw_inst_exec_size(brw, inst) < Elements(execsize_for_reg));
+ brw_inst_exec_size(brw, inst) < ARRAY_SIZE(execsize_for_reg));
execsize = execsize_for_reg[brw_inst_exec_size(brw, inst)];
/* Restrictions from 3.3.10: Register Region Restrictions. */
brw_set_src1(struct brw_compile *p, brw_inst *inst, struct brw_reg reg)
{
const struct brw_context *brw = p->brw;
- assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
if (reg.file != BRW_ARCHITECTURE_REGISTER_FILE)
assert(reg.nr < 128);
gen7_convert_mrf_to_grf(p, ®);
+ assert(reg.file != BRW_MESSAGE_REGISTER_FILE);
validate_reg(brw, inst, reg);
struct brw_context *brw = p->brw;
brw_set_src1(p, inst, brw_imm_d(0));
- brw_inst_set_sfid(brw, inst, sfid);
+
+ /* For indirect sends, `inst` will not be the SEND/SENDC instruction
+ * itself; instead, it will be a MOV/OR into the address register.
+ *
+ * In this case, we avoid setting the extended message descriptor bits,
+ * since they go on the later SEND/SENDC instead and if set here would
+ * instead clobber the conditionalmod bits.
+ */
+ unsigned opcode = brw_inst_opcode(brw, inst);
+ if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
+ brw_inst_set_sfid(brw, inst, sfid);
+ }
+
brw_inst_set_mlen(brw, inst, msg_length);
brw_inst_set_rlen(brw, inst, response_length);
brw_inst_set_eot(brw, inst, end_of_thread);
}
}
+void brw_set_indirect_send_descriptor(struct brw_compile *p,
+ brw_inst *insn,
+ unsigned sfid,
+ struct brw_reg descriptor)
+{
+ /* Only a0.0 may be used as SEND's descriptor operand. */
+ assert(descriptor.file == BRW_ARCHITECTURE_REGISTER_FILE);
+ assert(descriptor.type == BRW_REGISTER_TYPE_UD);
+ assert(descriptor.nr == BRW_ARF_ADDRESS);
+ assert(descriptor.subnr == 0);
+
+ brw_set_message_descriptor(p, insn, sfid, 0, 0, false, false);
+ brw_set_src1(p, insn, descriptor);
+}
+
static void
gen7_set_dp_scratch_message(struct brw_compile *p,
brw_inst *inst,
ALU2(SHR)
ALU2(SHL)
ALU2(ASR)
-ALU1(F32TO16)
-ALU1(F16TO32)
ALU1(FRC)
ALU1(RNDD)
ALU2(MAC)
ALU2(DPH)
ALU2(DP3)
ALU2(DP2)
-ALU2(LINE)
ALU2(PLN)
ALU3F(MAD)
ALU3F(LRP)
return brw_alu2(p, BRW_OPCODE_MUL, dest, src0, src1);
}
+brw_inst *
+brw_LINE(struct brw_compile *p, struct brw_reg dest,
+ struct brw_reg src0, struct brw_reg src1)
+{
+ src0.vstride = BRW_VERTICAL_STRIDE_0;
+ src0.width = BRW_WIDTH_1;
+ src0.hstride = BRW_HORIZONTAL_STRIDE_0;
+ return brw_alu2(p, BRW_OPCODE_LINE, dest, src0, src1);
+}
+
+brw_inst *
+brw_F32TO16(struct brw_compile *p, struct brw_reg dst, struct brw_reg src)
+{
+ const struct brw_context *brw = p->brw;
+ const bool align16 = brw_inst_access_mode(brw, p->current) == BRW_ALIGN_16;
+ /* The F32TO16 instruction doesn't support 32-bit destination types in
+ * Align1 mode, and neither does the Gen8 implementation in terms of a
+ * converting MOV. Gen7 does zero out the high 16 bits in Align16 mode as
+ * an undocumented feature.
+ */
+ const bool needs_zero_fill = (dst.type == BRW_REGISTER_TYPE_UD &&
+ (!align16 || brw->gen >= 8));
+ brw_inst *inst;
+
+ if (align16) {
+ assert(dst.type == BRW_REGISTER_TYPE_UD);
+ } else {
+ assert(dst.type == BRW_REGISTER_TYPE_UD ||
+ dst.type == BRW_REGISTER_TYPE_W ||
+ dst.type == BRW_REGISTER_TYPE_UW ||
+ dst.type == BRW_REGISTER_TYPE_HF);
+ }
+
+ brw_push_insn_state(p);
+
+ if (needs_zero_fill) {
+ brw_set_default_access_mode(p, BRW_ALIGN_1);
+ dst = spread(retype(dst, BRW_REGISTER_TYPE_W), 2);
+ }
+
+ if (brw->gen >= 8) {
+ inst = brw_MOV(p, retype(dst, BRW_REGISTER_TYPE_HF), src);
+ } else {
+ assert(brw->gen == 7);
+ inst = brw_alu1(p, BRW_OPCODE_F32TO16, dst, src);
+ }
+
+ if (needs_zero_fill) {
+ brw_inst_set_no_dd_clear(brw, inst, true);
+ inst = brw_MOV(p, suboffset(dst, 1), brw_imm_ud(0u));
+ brw_inst_set_no_dd_check(brw, inst, true);
+ }
+
+ brw_pop_insn_state(p);
+ return inst;
+}
+
+brw_inst *
+brw_F16TO32(struct brw_compile *p, struct brw_reg dst, struct brw_reg src)
+{
+ const struct brw_context *brw = p->brw;
+ bool align16 = brw_inst_access_mode(brw, p->current) == BRW_ALIGN_16;
+
+ if (align16) {
+ assert(src.type == BRW_REGISTER_TYPE_UD);
+ } else {
+ /* From the Ivybridge PRM, Vol4, Part3, Section 6.26 f16to32:
+ *
+ * Because this instruction does not have a 16-bit floating-point
+ * type, the source data type must be Word (W). The destination type
+ * must be F (Float).
+ */
+ if (src.type == BRW_REGISTER_TYPE_UD)
+ src = spread(retype(src, BRW_REGISTER_TYPE_W), 2);
+
+ assert(src.type == BRW_REGISTER_TYPE_W ||
+ src.type == BRW_REGISTER_TYPE_UW ||
+ src.type == BRW_REGISTER_TYPE_HF);
+ }
+
+ if (brw->gen >= 8) {
+ return brw_MOV(p, dst, retype(src, BRW_REGISTER_TYPE_HF));
+ } else {
+ assert(brw->gen == 7);
+ return brw_alu1(p, BRW_OPCODE_F16TO32, dst, src);
+ }
+}
+
void brw_NOP(struct brw_compile *p)
{
brw_inst_set_gen6_jump_count(brw, insn, 0);
brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
brw_set_src1(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
- } else {
+ } else if (brw->gen == 7) {
brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
brw_set_src0(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
- brw_set_src1(p, insn, brw_imm_ud(0));
+ brw_set_src1(p, insn, brw_imm_w(0));
+ brw_inst_set_jip(brw, insn, 0);
+ brw_inst_set_uip(brw, insn, 0);
+ } else {
+ brw_set_dest(p, insn, vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_D)));
+ brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(brw, insn, 0);
brw_inst_set_uip(brw, insn, 0);
}
assert(endif_inst != NULL);
assert(else_inst == NULL || brw_inst_opcode(brw, else_inst) == BRW_OPCODE_ELSE);
- unsigned br = 1;
- /* Jump count is for 64bit data chunk each, so one 128bit instruction
- * requires 2 chunks.
- */
- if (brw->gen >= 5)
- br = 2;
+ unsigned br = brw_jump_scale(brw);
assert(brw_inst_opcode(brw, endif_inst) == BRW_OPCODE_ENDIF);
brw_inst_set_exec_size(brw, endif_inst, brw_inst_exec_size(brw, if_inst));
/* The IF instruction's UIP and ELSE's JIP should point to ENDIF */
brw_inst_set_uip(brw, if_inst, br * (endif_inst - if_inst));
brw_inst_set_jip(brw, else_inst, br * (endif_inst - else_inst));
+ if (brw->gen >= 8) {
+ /* Since we don't set branch_ctrl, the ELSE's JIP and UIP both
+ * should point to ENDIF.
+ */
+ brw_inst_set_uip(brw, else_inst, br * (endif_inst - else_inst));
+ }
}
}
}
brw_inst_set_gen6_jump_count(brw, insn, 0);
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
- } else {
+ } else if (brw->gen == 7) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
- brw_set_src1(p, insn, brw_imm_ud(0));
+ brw_set_src1(p, insn, brw_imm_w(0));
+ brw_inst_set_jip(brw, insn, 0);
+ brw_inst_set_uip(brw, insn, 0);
+ } else {
+ brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+ brw_set_src0(p, insn, brw_imm_d(0));
brw_inst_set_jip(brw, insn, 0);
brw_inst_set_uip(brw, insn, 0);
}
brw_set_dest(p, insn, brw_imm_w(0));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
- } else {
+ } else if (brw->gen == 7) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
- brw_set_src1(p, insn, brw_imm_ud(0));
+ brw_set_src1(p, insn, brw_imm_w(0));
+ } else {
+ brw_set_src0(p, insn, brw_imm_d(0));
}
brw_inst_set_qtr_control(brw, insn, BRW_COMPRESSION_NONE);
brw_inst *insn;
insn = next_insn(p, BRW_OPCODE_BREAK);
- if (brw->gen >= 6) {
+ if (brw->gen >= 8) {
+ brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+ brw_set_src0(p, insn, brw_imm_d(0x0));
+ } else if (brw->gen >= 6) {
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src1(p, insn, brw_imm_d(0x0));
insn = next_insn(p, BRW_OPCODE_CONTINUE);
brw_set_dest(p, insn, brw_ip_reg());
- brw_set_src0(p, insn, brw_ip_reg());
- brw_set_src1(p, insn, brw_imm_d(0x0));
+ if (brw->gen >= 8) {
+ brw_set_src0(p, insn, brw_imm_d(0x0));
+ } else {
+ brw_set_src0(p, insn, brw_ip_reg());
+ brw_set_src1(p, insn, brw_imm_d(0x0));
+ }
if (brw->gen < 6) {
brw_inst_set_gen4_pop_count(brw, insn,
insn = next_insn(p, BRW_OPCODE_HALT);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
- brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
- brw_set_src1(p, insn, brw_imm_d(0x0)); /* UIP and JIP, updated later. */
+ if (brw->gen >= 8) {
+ brw_set_src0(p, insn, brw_imm_d(0x0));
+ } else {
+ brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+ brw_set_src1(p, insn, brw_imm_d(0x0)); /* UIP and JIP, updated later. */
+ }
if (p->compressed) {
brw_inst_set_exec_size(brw, insn, BRW_EXECUTE_16);
struct brw_context *brw = p->brw;
brw_inst *do_inst = get_inner_do_insn(p);
brw_inst *inst;
- int br = (brw->gen == 5) ? 2 : 1;
+ unsigned br = brw_jump_scale(brw);
+
+ assert(brw->gen < 6);
for (inst = while_inst - 1; inst != do_inst; inst--) {
/* If the jump count is != 0, that means that this instruction has already
{
struct brw_context *brw = p->brw;
brw_inst *insn, *do_insn;
- unsigned br = 1;
-
- if (brw->gen >= 5)
- br = 2;
+ unsigned br = brw_jump_scale(brw);
- if (brw->gen >= 7) {
- insn = next_insn(p, BRW_OPCODE_WHILE);
- do_insn = get_inner_do_insn(p);
-
- brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
- brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
- brw_set_src1(p, insn, brw_imm_ud(0));
- brw_inst_set_jip(brw, insn, br * (do_insn - insn));
-
- brw_inst_set_exec_size(brw, insn, p->compressed ? BRW_EXECUTE_16
- : BRW_EXECUTE_8);
- } else if (brw->gen == 6) {
+ if (brw->gen >= 6) {
insn = next_insn(p, BRW_OPCODE_WHILE);
do_insn = get_inner_do_insn(p);
- brw_set_dest(p, insn, brw_imm_w(0));
- brw_inst_set_gen6_jump_count(brw, insn, br * (do_insn - insn));
- brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
- brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+ if (brw->gen >= 8) {
+ brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+ brw_set_src0(p, insn, brw_imm_d(0));
+ brw_inst_set_jip(brw, insn, br * (do_insn - insn));
+ } else if (brw->gen == 7) {
+ brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+ brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+ brw_set_src1(p, insn, brw_imm_w(0));
+ brw_inst_set_jip(brw, insn, br * (do_insn - insn));
+ } else {
+ brw_set_dest(p, insn, brw_imm_w(0));
+ brw_inst_set_gen6_jump_count(brw, insn, br * (do_insn - insn));
+ brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+ brw_set_src1(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
+ }
brw_inst_set_exec_size(brw, insn, p->compressed ? BRW_EXECUTE_16
: BRW_EXECUTE_8);
unsigned function,
unsigned msg_reg_nr,
struct brw_reg src,
- unsigned data_type,
unsigned precision )
{
struct brw_context *brw = p->brw;
brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
+ unsigned data_type;
+ if (has_scalar_region(src)) {
+ data_type = BRW_MATH_DATA_SCALAR;
+ } else {
+ data_type = BRW_MATH_DATA_VECTOR;
+ }
assert(brw->gen < 6);
assert(dest.file == BRW_GENERAL_REGISTER_FILE ||
(brw->gen >= 7 && dest.file == BRW_MESSAGE_REGISTER_FILE));
- assert(src0.file == BRW_GENERAL_REGISTER_FILE);
+ assert(src0.file == BRW_GENERAL_REGISTER_FILE ||
+ (brw->gen >= 8 && src0.file == BRW_IMMEDIATE_VALUE));
assert(dest.hstride == BRW_HORIZONTAL_STRIDE_1);
if (brw->gen == 6) {
function == BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER) {
assert(src0.type != BRW_REGISTER_TYPE_F);
assert(src1.type != BRW_REGISTER_TYPE_F);
- assert(src1.file == BRW_GENERAL_REGISTER_FILE);
+ assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
+ (brw->gen >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
} else {
assert(src0.type == BRW_REGISTER_TYPE_F);
assert(src1.type == BRW_REGISTER_TYPE_F);
if (function == BRW_MATH_FUNCTION_POW) {
- assert(src1.file == BRW_GENERAL_REGISTER_FILE);
+ assert(src1.file == BRW_GENERAL_REGISTER_FILE ||
+ (brw->gen >= 8 && src1.file == BRW_IMMEDIATE_VALUE));
} else {
assert(src1.file == BRW_ARCHITECTURE_REGISTER_FILE &&
src1.nr == BRW_ARF_NULL);
if (brw->gen >= 6)
offset /= 16;
- mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
+ if (p->brw->gen >= 7) {
+ /* On gen 7 and above, we no longer have message registers and we can
+ * send from any register we want. By using the destination register
+ * for the message, we guarantee that the implied message write won't
+ * accidentally overwrite anything. This has been a problem because
+ * the MRF registers and source for the final FB write are both fixed
+ * and may overlap.
+ */
+ mrf = retype(dest, BRW_REGISTER_TYPE_UD);
+ } else {
+ mrf = retype(mrf, BRW_REGISTER_TYPE_UD);
+ }
dest = retype(dest, BRW_REGISTER_TYPE_UW);
if (num_regs == 1) {
brw_MOV(p, mrf, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
/* set message header global offset field (reg 0, element 2) */
- brw_MOV(p,
- retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE,
- mrf.nr,
- 2), BRW_REGISTER_TYPE_UD),
- brw_imm_ud(offset));
+ brw_MOV(p, get_element_ud(mrf, 2), brw_imm_ud(offset));
brw_pop_insn_state(p);
}
void brw_fb_WRITE(struct brw_compile *p,
int dispatch_width,
- unsigned msg_reg_nr,
- struct brw_reg src0,
+ struct brw_reg payload,
+ struct brw_reg implied_header,
unsigned msg_control,
unsigned binding_table_index,
unsigned msg_length,
unsigned response_length,
bool eot,
+ bool last_render_target,
bool header_present)
{
struct brw_context *brw = p->brw;
brw_inst *insn;
unsigned msg_type;
- struct brw_reg dest;
+ struct brw_reg dest, src0;
if (dispatch_width == 16)
dest = retype(vec16(brw_null_reg()), BRW_REGISTER_TYPE_UW);
if (brw->gen >= 6) {
/* headerless version, just submit color payload */
- src0 = brw_message_reg(msg_reg_nr);
+ src0 = payload;
msg_type = GEN6_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE;
} else {
- brw_inst_set_base_mrf(brw, insn, msg_reg_nr);
+ assert(payload.file == BRW_MESSAGE_REGISTER_FILE);
+ brw_inst_set_base_mrf(brw, insn, payload.nr);
+ src0 = implied_header;
msg_type = BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE;
}
msg_type,
msg_length,
header_present,
- eot, /* last render target write */
+ last_render_target,
response_length,
eot,
0 /* send_commit_msg */);
return_format);
}
+/* Adjust the message header's sampler state pointer to
+ * select the correct group of 16 samplers.
+ */
+void brw_adjust_sampler_state_pointer(struct brw_compile *p,
+ struct brw_reg header,
+ struct brw_reg sampler_index)
+{
+ /* The "Sampler Index" field can only store values between 0 and 15.
+ * However, we can add an offset to the "Sampler State Pointer"
+ * field, effectively selecting a different set of 16 samplers.
+ *
+ * The "Sampler State Pointer" needs to be aligned to a 32-byte
+ * offset, and each sampler state is only 16-bytes, so we can't
+ * exclusively use the offset - we have to use both.
+ */
+
+ struct brw_context *brw = p->brw;
+
+ if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
+ const int sampler_state_size = 16; /* 16 bytes */
+ uint32_t sampler = sampler_index.dw1.ud;
+
+ if (sampler >= 16) {
+ assert(brw->is_haswell || brw->gen >= 8);
+ brw_ADD(p,
+ get_element_ud(header, 3),
+ get_element_ud(brw_vec8_grf(0, 0), 3),
+ brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
+ }
+ } else {
+ /* Non-const sampler array indexing case */
+ if (brw->gen < 8 && !brw->is_haswell) {
+ return;
+ }
+
+ struct brw_reg temp = get_element_ud(header, 3);
+
+ brw_AND(p, temp, get_element_ud(sampler_index, 0), brw_imm_ud(0x0f0));
+ brw_SHL(p, temp, temp, brw_imm_ud(4));
+ brw_ADD(p,
+ get_element_ud(header, 3),
+ get_element_ud(brw_vec8_grf(0, 0), 3),
+ temp);
+ }
+}
+
/* All these variables are pretty confusing - we might be better off
* using bitmasks and macros for this, in the old style. Or perhaps
* just having the caller instantiate the fields in dword3 itself.
gen6_resolve_implied_move(p, &src0, msg_reg_nr);
- if (brw->gen == 7 && !(flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
+ if (brw->gen >= 7 && !(flags & BRW_URB_WRITE_USE_CHANNEL_MASKS)) {
/* Enable Channel Masks in the URB_WRITE_HWORD message header */
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_1);
{
struct brw_context *brw = p->brw;
int offset;
- int scale = 8;
+ int scale = 16 / brw_jump_scale(brw);
void *store = p->store;
+ assert(brw->gen >= 6);
+
/* Always start after the instruction (such as a WHILE) we're trying to fix
* up.
*/
{
struct brw_context *brw = p->brw;
int offset;
- int scale = 8;
+ int br = brw_jump_scale(brw);
+ int scale = 16 / br;
void *store = p->store;
if (brw->gen < 6)
assert(brw_inst_jip(brw, insn) != 0);
break;
- case BRW_OPCODE_ENDIF:
- if (block_end_offset == 0)
- brw_inst_set_jip(brw, insn, 2);
+ case BRW_OPCODE_ENDIF: {
+ int32_t jump = (block_end_offset == 0) ?
+ 1 * br : (block_end_offset - offset) / scale;
+ if (brw->gen >= 7)
+ brw_inst_set_jip(brw, insn, jump);
else
- brw_inst_set_jip(brw, insn, (block_end_offset - offset) / scale);
+ brw_inst_set_gen6_jump_count(brw, insn, jump);
break;
+ }
case BRW_OPCODE_HALT:
/* From the Sandy Bridge PRM (volume 4, part 2, section 8.3.19):
atomic_op | /* Atomic Operation Type: BRW_AOP_* */
(response_length ? 1 << 5 : 0); /* Return data expected */
- if (brw->is_haswell) {
+ if (brw->gen >= 8 || brw->is_haswell) {
brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1,
msg_length, response_length,
header_present, false);
void
brw_untyped_atomic(struct brw_compile *p,
struct brw_reg dest,
- struct brw_reg mrf,
+ struct brw_reg payload,
unsigned atomic_op,
unsigned bind_table_index,
unsigned msg_length,
brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UD));
- brw_set_src0(p, insn, retype(mrf, BRW_REGISTER_TYPE_UD));
+ brw_set_src0(p, insn, retype(payload, BRW_REGISTER_TYPE_UD));
brw_set_src1(p, insn, brw_imm_d(0));
brw_set_dp_untyped_atomic_message(
p, insn, atomic_op, bind_table_index, msg_length, response_length,
(brw_inst_exec_size(brw, insn) == BRW_EXECUTE_16 ? 16 : 8);
const unsigned num_channels = response_length / (dispatch_width / 8);
- if (brw->is_haswell) {
+ if (brw->gen >= 8 || brw->is_haswell) {
brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1,
msg_length, response_length,
header_present, false);
projects / mesa.git / blobdiff