i965/fs: add support for BRW_OPCODE_AVG in fs_generator

[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu_emit.c

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 90fde1d1e106117220541eee960167e27a1d0991..8ab043fd63c8a63024a7d51d3445a369c634d765 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1,6 +1,6 @@
 /*
  Copyright (C) Intel Corp.  2006.  All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
  develop this 3D driver.
 
  Permission is hereby granted, free of charge, to any person obtaining
@@ -26,7 +26,7 @@
  **********************************************************************/
  /*
   * Authors:
-  *   Keith Whitwell <keith@tungstengraphics.com>
+  *   Keith Whitwell <keithw@vmware.com>
   */
 
 
@@ -108,8 +108,6 @@ unsigned
 brw_reg_type_to_hw_type(const struct brw_context *brw,
                         enum brw_reg_type type, unsigned file)
 {
-   bool imm = file == BRW_IMMEDIATE_VALUE;
-
    if (file == BRW_IMMEDIATE_VALUE) {
       const static int imm_hw_types[] = {
          [BRW_REGISTER_TYPE_UD] = BRW_HW_REG_TYPE_UD,
@@ -122,10 +120,14 @@ brw_reg_type_to_hw_type(const struct brw_context *brw,
          [BRW_REGISTER_TYPE_UV] = BRW_HW_REG_IMM_TYPE_UV,
          [BRW_REGISTER_TYPE_VF] = BRW_HW_REG_IMM_TYPE_VF,
          [BRW_REGISTER_TYPE_V]  = BRW_HW_REG_IMM_TYPE_V,
-         [BRW_REGISTER_TYPE_DF] = -1,
+         [BRW_REGISTER_TYPE_DF] = GEN8_HW_REG_IMM_TYPE_DF,
+         [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_IMM_TYPE_HF,
+         [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
+         [BRW_REGISTER_TYPE_Q]  = GEN8_HW_REG_TYPE_Q,
       };
       assert(type < ARRAY_SIZE(imm_hw_types));
       assert(imm_hw_types[type] != -1);
+      assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_DF);
       return imm_hw_types[type];
    } else {
       /* Non-immediate registers */
@@ -141,10 +143,14 @@ brw_reg_type_to_hw_type(const struct brw_context *brw,
          [BRW_REGISTER_TYPE_VF] = -1,
          [BRW_REGISTER_TYPE_V]  = -1,
          [BRW_REGISTER_TYPE_DF] = GEN7_HW_REG_NON_IMM_TYPE_DF,
+         [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_NON_IMM_TYPE_HF,
+         [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
+         [BRW_REGISTER_TYPE_Q]  = GEN8_HW_REG_TYPE_Q,
       };
       assert(type < ARRAY_SIZE(hw_types));
       assert(hw_types[type] != -1);
       assert(brw->gen >= 7 || type < BRW_REGISTER_TYPE_DF);
+      assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_HF);
       return hw_types[type];
    }
 }