/*
Copyright (C) Intel Corp. 2006. All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
+ Intel funded Tungsten Graphics to
develop this 3D driver.
-
+
Permission is hereby granted, free of charge, to any person obtaining
a copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
distribute, sublicense, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
-
+
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial
portions of the Software.
-
+
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
+
**********************************************************************/
/*
* Authors:
- * Keith Whitwell <keith@tungstengraphics.com>
+ * Keith Whitwell <keithw@vmware.com>
*/
-
+
#include "brw_context.h"
#include "brw_defines.h"
void
gen6_resolve_implied_move(struct brw_compile *p,
struct brw_reg *src,
- GLuint msg_reg_nr)
+ unsigned msg_reg_nr)
{
struct brw_context *brw = p->brw;
if (brw->gen < 6)
}
}
+/**
+ * Convert a brw_reg_type enumeration value into the hardware representation.
+ *
+ * The hardware encoding may depend on whether the value is an immediate.
+ */
+unsigned
+brw_reg_type_to_hw_type(const struct brw_context *brw,
+ enum brw_reg_type type, unsigned file)
+{
+ if (file == BRW_IMMEDIATE_VALUE) {
+ const static int imm_hw_types[] = {
+ [BRW_REGISTER_TYPE_UD] = BRW_HW_REG_TYPE_UD,
+ [BRW_REGISTER_TYPE_D] = BRW_HW_REG_TYPE_D,
+ [BRW_REGISTER_TYPE_UW] = BRW_HW_REG_TYPE_UW,
+ [BRW_REGISTER_TYPE_W] = BRW_HW_REG_TYPE_W,
+ [BRW_REGISTER_TYPE_F] = BRW_HW_REG_TYPE_F,
+ [BRW_REGISTER_TYPE_UB] = -1,
+ [BRW_REGISTER_TYPE_B] = -1,
+ [BRW_REGISTER_TYPE_UV] = BRW_HW_REG_IMM_TYPE_UV,
+ [BRW_REGISTER_TYPE_VF] = BRW_HW_REG_IMM_TYPE_VF,
+ [BRW_REGISTER_TYPE_V] = BRW_HW_REG_IMM_TYPE_V,
+ [BRW_REGISTER_TYPE_DF] = GEN8_HW_REG_IMM_TYPE_DF,
+ [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_IMM_TYPE_HF,
+ [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
+ [BRW_REGISTER_TYPE_Q] = GEN8_HW_REG_TYPE_Q,
+ };
+ assert(type < ARRAY_SIZE(imm_hw_types));
+ assert(imm_hw_types[type] != -1);
+ assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_DF);
+ return imm_hw_types[type];
+ } else {
+ /* Non-immediate registers */
+ const static int hw_types[] = {
+ [BRW_REGISTER_TYPE_UD] = BRW_HW_REG_TYPE_UD,
+ [BRW_REGISTER_TYPE_D] = BRW_HW_REG_TYPE_D,
+ [BRW_REGISTER_TYPE_UW] = BRW_HW_REG_TYPE_UW,
+ [BRW_REGISTER_TYPE_W] = BRW_HW_REG_TYPE_W,
+ [BRW_REGISTER_TYPE_UB] = BRW_HW_REG_NON_IMM_TYPE_UB,
+ [BRW_REGISTER_TYPE_B] = BRW_HW_REG_NON_IMM_TYPE_B,
+ [BRW_REGISTER_TYPE_F] = BRW_HW_REG_TYPE_F,
+ [BRW_REGISTER_TYPE_UV] = -1,
+ [BRW_REGISTER_TYPE_VF] = -1,
+ [BRW_REGISTER_TYPE_V] = -1,
+ [BRW_REGISTER_TYPE_DF] = GEN7_HW_REG_NON_IMM_TYPE_DF,
+ [BRW_REGISTER_TYPE_HF] = GEN8_HW_REG_NON_IMM_TYPE_HF,
+ [BRW_REGISTER_TYPE_UQ] = GEN8_HW_REG_TYPE_UQ,
+ [BRW_REGISTER_TYPE_Q] = GEN8_HW_REG_TYPE_Q,
+ };
+ assert(type < ARRAY_SIZE(hw_types));
+ assert(hw_types[type] != -1);
+ assert(brw->gen >= 7 || type < BRW_REGISTER_TYPE_DF);
+ assert(brw->gen >= 8 || type < BRW_REGISTER_TYPE_HF);
+ return hw_types[type];
+ }
+}
void
brw_set_dest(struct brw_compile *p, struct brw_instruction *insn,
gen7_convert_mrf_to_grf(p, &dest);
insn->bits1.da1.dest_reg_file = dest.file;
- insn->bits1.da1.dest_reg_type = dest.type;
+ insn->bits1.da1.dest_reg_type =
+ brw_reg_type_to_hw_type(p->brw, dest.type, dest.file);
insn->bits1.da1.dest_address_mode = dest.address_mode;
- if (dest.address_mode == BRW_ADDRESS_DIRECT) {
+ if (dest.address_mode == BRW_ADDRESS_DIRECT) {
insn->bits1.da1.dest_reg_nr = dest.nr;
if (insn->header.access_mode == BRW_ALIGN_1) {
else {
insn->bits1.da16.dest_subreg_nr = dest.subnr / 16;
insn->bits1.da16.dest_writemask = dest.dw1.bits.writemask;
- assert(dest.dw1.bits.writemask != 0 ||
- dest.file == BRW_ARCHITECTURE_REGISTER_FILE);
+ if (dest.file == BRW_GENERAL_REGISTER_FILE ||
+ dest.file == BRW_MESSAGE_REGISTER_FILE) {
+ assert(dest.dw1.bits.writemask != 0);
+ }
/* From the Ivybridge PRM, Vol 4, Part 3, Section 5.2.4.1:
* Although Dst.HorzStride is a don't care for Align16, HW needs
* this to be programmed as "01".
validate_reg(insn, reg);
insn->bits1.da1.src0_reg_file = reg.file;
- insn->bits1.da1.src0_reg_type = reg.type;
+ insn->bits1.da1.src0_reg_type =
+ brw_reg_type_to_hw_type(brw, reg.type, reg.file);
insn->bits2.da1.src0_abs = reg.abs;
insn->bits2.da1.src0_negate = reg.negate;
insn->bits2.da1.src0_address_mode = reg.address_mode;
if (reg.file == BRW_IMMEDIATE_VALUE) {
insn->bits3.ud = reg.dw1.ud;
-
+
/* Required to set some fields in src1 as well:
*/
insn->bits1.da1.src1_reg_file = 0; /* arf */
- insn->bits1.da1.src1_reg_type = reg.type;
+ insn->bits1.da1.src1_reg_type = insn->bits1.da1.src0_reg_type;
}
- else
+ else
{
if (reg.address_mode == BRW_ADDRESS_DIRECT) {
if (insn->header.access_mode == BRW_ALIGN_1) {
insn->bits2.ia1.src0_subreg_nr = reg.subnr;
if (insn->header.access_mode == BRW_ALIGN_1) {
- insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset;
+ insn->bits2.ia1.src0_indirect_offset = reg.dw1.bits.indirect_offset;
}
else {
insn->bits2.ia16.src0_subreg_nr = reg.dw1.bits.indirect_offset;
}
if (insn->header.access_mode == BRW_ALIGN_1) {
- if (reg.width == BRW_WIDTH_1 &&
+ if (reg.width == BRW_WIDTH_1 &&
insn->header.execution_size == BRW_EXECUTE_1) {
insn->bits2.da1.src0_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
insn->bits2.da1.src0_width = BRW_WIDTH_1;
validate_reg(insn, reg);
insn->bits1.da1.src1_reg_file = reg.file;
- insn->bits1.da1.src1_reg_type = reg.type;
+ insn->bits1.da1.src1_reg_type =
+ brw_reg_type_to_hw_type(p->brw, reg.type, reg.file);
insn->bits3.da1.src1_abs = reg.abs;
insn->bits3.da1.src1_negate = reg.negate;
}
if (insn->header.access_mode == BRW_ALIGN_1) {
- if (reg.width == BRW_WIDTH_1 &&
+ if (reg.width == BRW_WIDTH_1 &&
insn->header.execution_size == BRW_EXECUTE_1) {
insn->bits3.da1.src1_horiz_stride = BRW_HORIZONTAL_STRIDE_0;
insn->bits3.da1.src1_width = BRW_WIDTH_1;
static void brw_set_math_message( struct brw_compile *p,
struct brw_instruction *insn,
- GLuint function,
- GLuint integer_type,
+ unsigned function,
+ unsigned integer_type,
bool low_precision,
- GLuint dataType )
+ unsigned dataType )
{
struct brw_context *brw = p->brw;
unsigned msg_length;
static void brw_set_ff_sync_message(struct brw_compile *p,
struct brw_instruction *insn,
bool allocate,
- GLuint response_length,
+ unsigned response_length,
bool end_of_thread)
{
brw_set_message_descriptor(p, insn, BRW_SFID_URB,
static void brw_set_urb_message( struct brw_compile *p,
struct brw_instruction *insn,
enum brw_urb_write_flags flags,
- GLuint msg_length,
- GLuint response_length,
- GLuint offset,
- GLuint swizzle_control )
+ unsigned msg_length,
+ unsigned response_length,
+ unsigned offset,
+ unsigned swizzle_control )
{
struct brw_context *brw = p->brw;
void
brw_set_dp_write_message(struct brw_compile *p,
struct brw_instruction *insn,
- GLuint binding_table_index,
- GLuint msg_control,
- GLuint msg_type,
- GLuint msg_length,
+ unsigned binding_table_index,
+ unsigned msg_control,
+ unsigned msg_type,
+ unsigned msg_length,
bool header_present,
- GLuint last_render_target,
- GLuint response_length,
- GLuint end_of_thread,
- GLuint send_commit_msg)
+ unsigned last_render_target,
+ unsigned response_length,
+ unsigned end_of_thread,
+ unsigned send_commit_msg)
{
struct brw_context *brw = p->brw;
unsigned sfid;
void
brw_set_dp_read_message(struct brw_compile *p,
struct brw_instruction *insn,
- GLuint binding_table_index,
- GLuint msg_control,
- GLuint msg_type,
- GLuint target_cache,
- GLuint msg_length,
+ unsigned binding_table_index,
+ unsigned msg_control,
+ unsigned msg_type,
+ unsigned target_cache,
+ unsigned msg_length,
bool header_present,
- GLuint response_length)
+ unsigned response_length)
{
struct brw_context *brw = p->brw;
unsigned sfid;
void
brw_set_sampler_message(struct brw_compile *p,
struct brw_instruction *insn,
- GLuint binding_table_index,
- GLuint sampler,
- GLuint msg_type,
- GLuint response_length,
- GLuint msg_length,
- GLuint header_present,
- GLuint simd_mode,
- GLuint return_format)
+ unsigned binding_table_index,
+ unsigned sampler,
+ unsigned msg_type,
+ unsigned response_length,
+ unsigned msg_length,
+ unsigned header_present,
+ unsigned simd_mode,
+ unsigned return_format)
{
struct brw_context *brw = p->brw;
#define next_insn brw_next_insn
struct brw_instruction *
-brw_next_insn(struct brw_compile *p, GLuint opcode)
+brw_next_insn(struct brw_compile *p, unsigned opcode)
{
struct brw_instruction *insn;
insn = &p->store[p->nr_insn++];
memcpy(insn, p->current, sizeof(*insn));
- /* Reset this one-shot flag:
+ /* Reset this one-shot flag:
*/
if (p->current->header.destreg__conditionalmod) {
}
static struct brw_instruction *brw_alu1( struct brw_compile *p,
- GLuint opcode,
+ unsigned opcode,
struct brw_reg dest,
struct brw_reg src )
{
}
static struct brw_instruction *brw_alu2(struct brw_compile *p,
- GLuint opcode,
+ unsigned opcode,
struct brw_reg dest,
struct brw_reg src0,
struct brw_reg src1 )
{
- struct brw_instruction *insn = next_insn(p, opcode);
+ struct brw_instruction *insn = next_insn(p, opcode);
brw_set_dest(p, insn, dest);
brw_set_src0(p, insn, src0);
brw_set_src1(p, insn, src1);
}
static struct brw_instruction *brw_alu3(struct brw_compile *p,
- GLuint opcode,
+ unsigned opcode,
struct brw_reg dest,
struct brw_reg src0,
struct brw_reg src1,
ALU1(FBH)
ALU1(FBL)
ALU1(CBIT)
+ALU2(ADDC)
+ALU2(SUBB)
ROUND(RNDZ)
ROUND(RNDE)
void brw_NOP(struct brw_compile *p)
{
- struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_NOP);
brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src1(p, insn, brw_imm_ud(0x0));
* Comparisons, if/else/endif
*/
-struct brw_instruction *brw_JMPI(struct brw_compile *p,
+struct brw_instruction *brw_JMPI(struct brw_compile *p,
struct brw_reg dest,
struct brw_reg src0,
struct brw_reg src1)
* popped off. If the stack is now empty, normal execution resumes.
*/
struct brw_instruction *
-brw_IF(struct brw_compile *p, GLuint execute_size)
+brw_IF(struct brw_compile *p, unsigned execute_size)
{
struct brw_context *brw = p->brw;
struct brw_instruction *insn;
* For gen6, there's no more mask stack, so no need for DO. WHILE
* just points back to the first instruction of the loop.
*/
-struct brw_instruction *brw_DO(struct brw_compile *p, GLuint execute_size)
+struct brw_instruction *brw_DO(struct brw_compile *p, unsigned execute_size)
{
struct brw_context *brw = p->brw;
{
struct brw_context *brw = p->brw;
struct brw_instruction *insn, *do_insn;
- GLuint br = 1;
+ unsigned br = 1;
if (brw->gen >= 5)
br = 2;
{
struct brw_context *brw = p->brw;
struct brw_instruction *jmp_insn = &p->store[jmp_insn_idx];
- GLuint jmpi = 1;
+ unsigned jmpi = 1;
if (brw->gen >= 5)
jmpi = 2;
*/
void brw_CMP(struct brw_compile *p,
struct brw_reg dest,
- GLuint conditional,
+ unsigned conditional,
struct brw_reg src0,
struct brw_reg src1)
{
/* Make it so that future instructions will use the computed flag
* value until brw_set_predicate_control_flag_value() is called
- * again.
+ * again.
*/
if (dest.file == BRW_ARCHITECTURE_REGISTER_FILE &&
dest.nr == 0) {
*/
void brw_math( struct brw_compile *p,
struct brw_reg dest,
- GLuint function,
- GLuint msg_reg_nr,
+ unsigned function,
+ unsigned msg_reg_nr,
struct brw_reg src,
- GLuint data_type,
- GLuint precision )
+ unsigned data_type,
+ unsigned precision )
{
struct brw_context *brw = p->brw;
*/
void brw_math2(struct brw_compile *p,
struct brw_reg dest,
- GLuint function,
+ unsigned function,
struct brw_reg src0,
struct brw_reg src1)
{
void brw_oword_block_write_scratch(struct brw_compile *p,
struct brw_reg mrf,
int num_regs,
- GLuint offset)
+ unsigned offset)
{
struct brw_context *brw = p->brw;
uint32_t msg_control, msg_type;
struct brw_reg dest,
struct brw_reg mrf,
int num_regs,
- GLuint offset)
+ unsigned offset)
{
struct brw_context *brw = p->brw;
uint32_t msg_control;
}
}
+void
+gen7_block_read_scratch(struct brw_compile *p,
+ struct brw_reg dest,
+ int num_regs,
+ unsigned offset)
+{
+ dest = retype(dest, BRW_REGISTER_TYPE_UW);
+
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+
+ assert(insn->header.predicate_control == BRW_PREDICATE_NONE);
+ insn->header.compression_control = BRW_COMPRESSION_NONE;
+
+ brw_set_dest(p, insn, dest);
+
+ /* The HW requires that the header is present; this is to get the g0.5
+ * scratch offset.
+ */
+ bool header_present = true;
+ brw_set_src0(p, insn, brw_vec8_grf(0, 0));
+
+ brw_set_message_descriptor(p, insn,
+ GEN7_SFID_DATAPORT_DATA_CACHE,
+ 1, /* mlen: just g0 */
+ num_regs,
+ header_present,
+ false);
+
+ insn->bits3.ud |= GEN7_DATAPORT_SCRATCH_READ;
+
+ assert(num_regs == 1 || num_regs == 2 || num_regs == 4);
+ insn->bits3.ud |= (num_regs - 1) << GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT;
+
+ /* According to the docs, offset is "A 12-bit HWord offset into the memory
+ * Immediate Memory buffer as specified by binding table 0xFF." An HWORD
+ * is 32 bytes, which happens to be the size of a register.
+ */
+ offset /= REG_SIZE;
+ assert(offset < (1 << 12));
+ insn->bits3.ud |= offset;
+}
+
/**
* Read a float[4] vector from the data port Data Cache (const buffer).
* Location (in buffer) should be a multiple of 16.
void brw_fb_WRITE(struct brw_compile *p,
int dispatch_width,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
- GLuint msg_control,
- GLuint binding_table_index,
- GLuint msg_length,
- GLuint response_length,
+ unsigned msg_control,
+ unsigned binding_table_index,
+ unsigned msg_length,
+ unsigned response_length,
bool eot,
bool header_present)
{
struct brw_context *brw = p->brw;
struct brw_instruction *insn;
- GLuint msg_type;
+ unsigned msg_type;
struct brw_reg dest;
if (dispatch_width == 16)
*/
void brw_SAMPLE(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
- GLuint binding_table_index,
- GLuint sampler,
- GLuint msg_type,
- GLuint response_length,
- GLuint msg_length,
- GLuint header_present,
- GLuint simd_mode,
- GLuint return_format)
+ unsigned binding_table_index,
+ unsigned sampler,
+ unsigned msg_type,
+ unsigned response_length,
+ unsigned msg_length,
+ unsigned header_present,
+ unsigned simd_mode,
+ unsigned return_format)
{
struct brw_context *brw = p->brw;
struct brw_instruction *insn;
- gen6_resolve_implied_move(p, &src0, msg_reg_nr);
+ if (msg_reg_nr != -1)
+ gen6_resolve_implied_move(p, &src0, msg_reg_nr);
insn = next_insn(p, BRW_OPCODE_SEND);
insn->header.predicate_control = 0; /* XXX */
- insn->header.compression_control = BRW_COMPRESSION_NONE;
+
+ /* From the 965 PRM (volume 4, part 1, section 14.2.41):
+ *
+ * "Instruction compression is not allowed for this instruction (that
+ * is, send). The hardware behavior is undefined if this instruction is
+ * set as compressed. However, compress control can be set to "SecHalf"
+ * to affect the EMask generation."
+ *
+ * No similar wording is found in later PRMs, but there are examples
+ * utilizing send with SecHalf. More importantly, SIMD8 sampler messages
+ * are allowed in SIMD16 mode and they could not work without SecHalf. For
+ * these reasons, we allow BRW_COMPRESSION_2NDHALF here.
+ */
+ if (insn->header.compression_control != BRW_COMPRESSION_2NDHALF)
+ insn->header.compression_control = BRW_COMPRESSION_NONE;
+
if (brw->gen < 6)
insn->header.destreg__conditionalmod = msg_reg_nr;
*/
void brw_urb_WRITE(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
enum brw_urb_write_flags flags,
- GLuint msg_length,
- GLuint response_length,
- GLuint offset,
- GLuint swizzle)
+ unsigned msg_length,
+ unsigned response_length,
+ unsigned offset,
+ unsigned swizzle)
{
struct brw_context *brw = p->brw;
struct brw_instruction *insn;
insn,
flags,
msg_length,
- response_length,
+ response_length,
offset,
swizzle);
}
void brw_ff_sync(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
bool allocate,
- GLuint response_length,
+ unsigned response_length,
bool eot)
{
struct brw_context *brw = p->brw;
void
brw_svb_write(struct brw_compile *p,
struct brw_reg dest,
- GLuint msg_reg_nr,
+ unsigned msg_reg_nr,
struct brw_reg src0,
- GLuint binding_table_index,
+ unsigned binding_table_index,
bool send_commit_msg)
{
struct brw_instruction *insn;
send_commit_msg); /* send_commit_msg */
}
+static void
+brw_set_dp_untyped_atomic_message(struct brw_compile *p,
+ struct brw_instruction *insn,
+ unsigned atomic_op,
+ unsigned bind_table_index,
+ unsigned msg_length,
+ unsigned response_length,
+ bool header_present)
+{
+ if (p->brw->is_haswell) {
+ brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1,
+ msg_length, response_length,
+ header_present, false);
+
+
+ if (insn->header.access_mode == BRW_ALIGN_1) {
+ if (insn->header.execution_size != BRW_EXECUTE_16)
+ insn->bits3.ud |= 1 << 12; /* SIMD8 mode */
+
+ insn->bits3.gen7_dp.msg_type =
+ HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
+ } else {
+ insn->bits3.gen7_dp.msg_type =
+ HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP_SIMD4X2;
+ }
+
+ } else {
+ brw_set_message_descriptor(p, insn, GEN7_SFID_DATAPORT_DATA_CACHE,
+ msg_length, response_length,
+ header_present, false);
+
+ insn->bits3.gen7_dp.msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
+
+ if (insn->header.execution_size != BRW_EXECUTE_16)
+ insn->bits3.ud |= 1 << 12; /* SIMD8 mode */
+ }
+
+ if (response_length)
+ insn->bits3.ud |= 1 << 13; /* Return data expected */
+
+ insn->bits3.gen7_dp.binding_table_index = bind_table_index;
+ insn->bits3.ud |= atomic_op << 8;
+}
+
+void
+brw_untyped_atomic(struct brw_compile *p,
+ struct brw_reg dest,
+ struct brw_reg mrf,
+ unsigned atomic_op,
+ unsigned bind_table_index,
+ unsigned msg_length,
+ unsigned response_length) {
+ struct brw_instruction *insn = brw_next_insn(p, BRW_OPCODE_SEND);
+
+ brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UD));
+ brw_set_src0(p, insn, retype(mrf, BRW_REGISTER_TYPE_UD));
+ brw_set_src1(p, insn, brw_imm_d(0));
+ brw_set_dp_untyped_atomic_message(
+ p, insn, atomic_op, bind_table_index, msg_length, response_length,
+ insn->header.access_mode == BRW_ALIGN_1);
+}
+
+static void
+brw_set_dp_untyped_surface_read_message(struct brw_compile *p,
+ struct brw_instruction *insn,
+ unsigned bind_table_index,
+ unsigned msg_length,
+ unsigned response_length,
+ bool header_present)
+{
+ const unsigned dispatch_width =
+ (insn->header.execution_size == BRW_EXECUTE_16 ? 16 : 8);
+ const unsigned num_channels = response_length / (dispatch_width / 8);
+
+ if (p->brw->is_haswell) {
+ brw_set_message_descriptor(p, insn, HSW_SFID_DATAPORT_DATA_CACHE_1,
+ msg_length, response_length,
+ header_present, false);
+
+ insn->bits3.gen7_dp.msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_SURFACE_READ;
+ } else {
+ brw_set_message_descriptor(p, insn, GEN7_SFID_DATAPORT_DATA_CACHE,
+ msg_length, response_length,
+ header_present, false);
+
+ insn->bits3.gen7_dp.msg_type = GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ;
+ }
+
+ if (insn->header.access_mode == BRW_ALIGN_1) {
+ if (dispatch_width == 16)
+ insn->bits3.ud |= 1 << 12; /* SIMD16 mode */
+ else
+ insn->bits3.ud |= 2 << 12; /* SIMD8 mode */
+ }
+
+ insn->bits3.gen7_dp.binding_table_index = bind_table_index;
+
+ /* Set mask of 32-bit channels to drop. */
+ insn->bits3.ud |= (0xf & (0xf << num_channels)) << 8;
+}
+
+void
+brw_untyped_surface_read(struct brw_compile *p,
+ struct brw_reg dest,
+ struct brw_reg mrf,
+ unsigned bind_table_index,
+ unsigned msg_length,
+ unsigned response_length)
+{
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+
+ brw_set_dest(p, insn, retype(dest, BRW_REGISTER_TYPE_UD));
+ brw_set_src0(p, insn, retype(mrf, BRW_REGISTER_TYPE_UD));
+ brw_set_dp_untyped_surface_read_message(
+ p, insn, bind_table_index, msg_length, response_length,
+ insn->header.access_mode == BRW_ALIGN_1);
+}
+
/**
* This instruction is generated as a single-channel align1 instruction by
* both the VS and FS stages when using INTEL_DEBUG=shader_time.
BRW_ARF_NULL, 0));
brw_set_src0(p, send, brw_vec1_reg(payload.file,
payload.nr, 0));
-
- uint32_t sfid, msg_type;
- if (brw->is_haswell) {
- sfid = HSW_SFID_DATAPORT_DATA_CACHE_1;
- msg_type = HSW_DATAPORT_DC_PORT1_UNTYPED_ATOMIC_OP;
- } else {
- sfid = GEN7_SFID_DATAPORT_DATA_CACHE;
- msg_type = GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP;
- }
-
- bool header_present = false;
- bool eot = false;
- uint32_t mlen = 2; /* offset, value */
- uint32_t rlen = 0;
- brw_set_message_descriptor(p, send, sfid, mlen, rlen, header_present, eot);
-
- send->bits3.ud |= msg_type << 14;
- send->bits3.ud |= 0 << 13; /* no return data */
- send->bits3.ud |= 1 << 12; /* SIMD8 mode */
- send->bits3.ud |= BRW_AOP_ADD << 8;
- send->bits3.ud |= surf_index << 0;
+ brw_set_dp_untyped_atomic_message(p, send, BRW_AOP_ADD, surf_index,
+ 2 /* message length */,
+ 0 /* response length */,
+ false /* header present */);
}
projects / mesa.git / blobdiff