intel: Add a batch flush between front-buffer downsample and X protocol.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_eu_emit.c

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 622b22f79818ddbd615db237db7c0660453eeb0d..ecf8597823f9234c7450915d190c9b97c8c2bb27 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -515,7 +515,7 @@ static void brw_set_ff_sync_message(struct brw_compile *p,
 
 static void brw_set_urb_message( struct brw_compile *p,
                                 struct brw_instruction *insn,
-                                 unsigned flags,
+                                 enum brw_urb_write_flags flags,
                                 GLuint msg_length,
                                 GLuint response_length,
                                 GLuint offset,
@@ -531,8 +531,8 @@ static void brw_set_urb_message( struct brw_compile *p,
       insn->bits3.urb_gen7.offset = offset;
       assert(swizzle_control != BRW_URB_SWIZZLE_TRANSPOSE);
       insn->bits3.urb_gen7.swizzle_control = swizzle_control;
-      /* per_slot_offset = 0 makes it ignore offsets in message header */
-      insn->bits3.urb_gen7.per_slot_offset = 0;
+      insn->bits3.urb_gen7.per_slot_offset =
+         flags & BRW_URB_WRITE_PER_SLOT_OFFSET ? 1 : 0;
       insn->bits3.urb_gen7.complete = flags & BRW_URB_WRITE_COMPLETE ? 1 : 0;
    } else if (brw->gen >= 5) {
       insn->bits3.urb_gen5.opcode = 0; /* URB_WRITE */
@@ -2213,7 +2213,7 @@ void brw_urb_WRITE(struct brw_compile *p,
                   struct brw_reg dest,
                   GLuint msg_reg_nr,
                   struct brw_reg src0,
-                   unsigned flags,
+                   enum brw_urb_write_flags flags,
                   GLuint msg_length,
                   GLuint response_length,
                   GLuint offset,