i965: clip: Remove no-longer-needed variables.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_fallback.c

diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c
index 79691c3a0f9793804dc3cb6ad51ccef7f4ed3b92..d0b0c22abf6d5f66ee70d089b9d8cb361d553c39 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fallback.c
+++ b/src/mesa/drivers/dri/i965/brw_fallback.c
@@ -36,15 +36,12 @@
 #include "swrast/swrast.h"
 #include "tnl/tnl.h"
 #include "brw_context.h"
-#include "intel_chipset.h"
-#include "intel_fbo.h"
-#include "intel_regions.h"
 
 #define FILE_DEBUG_FLAG DEBUG_FALLBACKS
 
 static GLboolean do_check_fallback(struct brw_context *brw)
 {
-   GLcontext *ctx = &brw->intel.ctx;
+   struct gl_context *ctx = &brw->intel.ctx;
    GLuint i;
 
    if (brw->intel.no_rast) {
@@ -64,49 +61,14 @@ static GLboolean do_check_fallback(struct brw_context *brw)
    for (i = 0; i < BRW_MAX_TEX_UNIT; i++) {
       struct gl_texture_unit *texUnit = &ctx->Texture.Unit[i];
       if (texUnit->_ReallyEnabled) {
-        struct intel_texture_object *intelObj = intel_texture_object(texUnit->_Current);
-        struct gl_texture_image *texImage = intelObj->base.Image[0][intelObj->firstLevel];
+        struct gl_texture_object *tex_obj = texUnit->_Current;
+        struct gl_texture_image *texImage = tex_obj->Image[0][tex_obj->BaseLevel];
         if (texImage->Border) {
            DBG("FALLBACK: texture border\n");
            return GL_TRUE;
         }
       }
    }
-   
-   /* _NEW_STENCIL 
-    */
-   if (ctx->Stencil._Enabled &&
-       (ctx->DrawBuffer->Name == 0 && !brw->intel.hw_stencil)) {
-      DBG("FALLBACK: stencil\n");
-      return GL_TRUE;
-   }
-
-   /* _NEW_BUFFERS */
-   if (!brw->has_surface_tile_offset) {
-      for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
-        struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
-        struct intel_renderbuffer *irb = intel_renderbuffer(rb);
-
-        /* The original gen4 hardware couldn't set up WM surfaces pointing
-         * at an offset within a tile, which can happen when rendering to
-         * anything but the base level of a texture or the +X face/0 depth.
-         * This was fixed with the 4 Series hardware.
-         *
-         * For these original chips, you would have to make the depth and
-         * color destination surfaces include information on the texture
-         * type, LOD, face, and various limits to use them as a destination.
-         * I would have done this, but there's also a nasty requirement that
-         * the depth and the color surfaces all be of the same LOD, which
-         * may be a worse requirement than this alignment.  (Also, we may
-         * want to just demote the texture to untiled, instead).
-         */
-        if (irb->region && irb->region->tiling != I915_TILING_NONE &&
-            (irb->region->draw_offset & 4095)) {
-           DBG("FALLBACK: non-tile-aligned destination for tiled FBO\n");
-           return GL_TRUE;
-        }
-      }
-   }
 
    return GL_FALSE;
 }
@@ -118,7 +80,7 @@ static void check_fallback(struct brw_context *brw)
 
 const struct brw_tracked_state brw_check_fallback = {
    .dirty = {
-      .mesa = _NEW_BUFFERS | _NEW_RENDERMODE | _NEW_TEXTURE | _NEW_STENCIL,
+      .mesa = _NEW_RENDERMODE | _NEW_TEXTURE | _NEW_STENCIL,
       .brw  = 0,
       .cache = 0
    },