Merge branch 'mesa_7_6_branch'

[mesa.git] / src / mesa / drivers / dri / i965 / brw_fallback.c

diff --git a/src/mesa/drivers/dri/i965/brw_fallback.c b/src/mesa/drivers/dri/i965/brw_fallback.c
index 5f4f2d515dff9ea227b9c986ef184fdb59168727..d27c6c24ca50258d647484846fc1f4a6d62891fa 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fallback.c
+++ b/src/mesa/drivers/dri/i965/brw_fallback.c
@@ -37,6 +37,9 @@
 #include "tnl/tnl.h"
 #include "brw_context.h"
 #include "brw_fallback.h"
+#include "intel_chipset.h"
+#include "intel_fbo.h"
+#include "intel_regions.h"
 
 #include "glapi/glapi.h"
 
@@ -44,6 +47,7 @@
 
 static GLboolean do_check_fallback(struct brw_context *brw)
 {
+   struct intel_context *intel = &brw->intel;
    GLcontext *ctx = &brw->intel.ctx;
    GLuint i;
 
@@ -75,12 +79,39 @@ static GLboolean do_check_fallback(struct brw_context *brw)
    
    /* _NEW_STENCIL 
     */
-   if (ctx->Stencil.Enabled &&
+   if (ctx->Stencil._Enabled &&
        (ctx->DrawBuffer->Name == 0 && !brw->intel.hw_stencil)) {
       DBG("FALLBACK: stencil\n");
       return GL_TRUE;
    }
 
+   /* _NEW_BUFFERS */
+   if (IS_965(intel->intelScreen->deviceID) &&
+       !IS_G4X(intel->intelScreen->deviceID)) {
+      for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
+        struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i];
+        struct intel_renderbuffer *irb = intel_renderbuffer(rb);
+
+        /* The original gen4 hardware couldn't set up WM surfaces pointing
+         * at an offset within a tile, which can happen when rendering to
+         * anything but the base level of a texture or the +X face/0 depth.
+         * This was fixed with the 4 Series hardware.
+         *
+         * For these original chips, you would have to make the depth and
+         * color destination surfaces include information on the texture
+         * type, LOD, face, and various limits to use them as a destination.
+         * I would have done this, but there's also a nasty requirement that
+         * the depth and the color surfaces all be of the same LOD, which
+         * may be a worse requirement than this alignment.  (Also, we may
+         * want to just demote the texture to untiled, instead).
+         */
+        if (irb->region && irb->region->tiling != I915_TILING_NONE &&
+            (irb->region->draw_offset & 4095)) {
+           DBG("FALLBACK: non-tile-aligned destination for tiled FBO\n");
+           return GL_TRUE;
+        }
+      }
+   }
 
    return GL_FALSE;
 }