#include "../glsl/ir_optimization.h"
#include "../glsl/ir_print_visitor.h"
-static int using_new_fs = -1;
static struct brw_reg brw_reg_from_fs_reg(class fs_reg *reg);
struct gl_shader *
-brw_new_shader(GLcontext *ctx, GLuint name, GLuint type)
+brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
{
struct brw_shader *shader;
}
struct gl_shader_program *
-brw_new_shader_program(GLcontext *ctx, GLuint name)
+brw_new_shader_program(struct gl_context *ctx, GLuint name)
{
struct brw_shader_program *prog;
prog = talloc_zero(NULL, struct brw_shader_program);
}
GLboolean
-brw_compile_shader(GLcontext *ctx, struct gl_shader *shader)
+brw_compile_shader(struct gl_context *ctx, struct gl_shader *shader)
{
if (!_mesa_ir_compile_shader(ctx, shader))
return GL_FALSE;
}
GLboolean
-brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog)
+brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
{
struct intel_context *intel = intel_context(ctx);
- if (using_new_fs == -1)
- using_new_fs = getenv("INTEL_NEW_FS") != NULL;
-
- for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) {
- struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i];
-
- if (using_new_fs && shader->base.Type == GL_FRAGMENT_SHADER) {
- void *mem_ctx = talloc_new(NULL);
- bool progress;
-
- if (shader->ir)
- talloc_free(shader->ir);
- shader->ir = new(shader) exec_list;
- clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
-
- do_mat_op_to_vec(shader->ir);
- do_mod_to_fract(shader->ir);
- do_div_to_mul_rcp(shader->ir);
- do_sub_to_add_neg(shader->ir);
- do_explog_to_explog2(shader->ir);
- do_lower_texture_projection(shader->ir);
- brw_do_cubemap_normalize(shader->ir);
-
- do {
- progress = false;
-
- brw_do_channel_expressions(shader->ir);
- brw_do_vector_splitting(shader->ir);
-
- progress = do_lower_jumps(shader->ir, true, true,
- true, /* main return */
- false, /* continue */
- false /* loops */
- ) || progress;
-
- progress = do_common_optimization(shader->ir, true, 32) || progress;
-
- progress = lower_noise(shader->ir) || progress;
- progress =
- lower_variable_index_to_cond_assign(shader->ir,
- GL_TRUE, /* input */
- GL_TRUE, /* output */
- GL_TRUE, /* temp */
- GL_TRUE /* uniform */
- ) || progress;
- if (intel->gen == 6) {
- progress = do_if_to_cond_assign(shader->ir) || progress;
- }
- } while (progress);
- validate_ir_tree(shader->ir);
+ struct brw_shader *shader =
+ (struct brw_shader *)prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
+ if (shader != NULL) {
+ void *mem_ctx = talloc_new(NULL);
+ bool progress;
+
+ if (shader->ir)
+ talloc_free(shader->ir);
+ shader->ir = new(shader) exec_list;
+ clone_ir_list(mem_ctx, shader->ir, shader->base.ir);
- reparent_ir(shader->ir, shader->ir);
- talloc_free(mem_ctx);
- }
+ do_mat_op_to_vec(shader->ir);
+ do_mod_to_fract(shader->ir);
+ do_div_to_mul_rcp(shader->ir);
+ do_sub_to_add_neg(shader->ir);
+ do_explog_to_explog2(shader->ir);
+ do_lower_texture_projection(shader->ir);
+ brw_do_cubemap_normalize(shader->ir);
+
+ do {
+ progress = false;
+
+ brw_do_channel_expressions(shader->ir);
+ brw_do_vector_splitting(shader->ir);
+
+ progress = do_lower_jumps(shader->ir, true, true,
+ true, /* main return */
+ false, /* continue */
+ false /* loops */
+ ) || progress;
+
+ progress = do_common_optimization(shader->ir, true, 32) || progress;
+
+ progress = lower_noise(shader->ir) || progress;
+ progress =
+ lower_variable_index_to_cond_assign(shader->ir,
+ GL_TRUE, /* input */
+ GL_TRUE, /* output */
+ GL_TRUE, /* temp */
+ GL_TRUE /* uniform */
+ ) || progress;
+ if (intel->gen == 6) {
+ progress = do_if_to_cond_assign(shader->ir) || progress;
+ }
+ } while (progress);
+
+ validate_ir_tree(shader->ir);
+
+ reparent_ir(shader->ir, shader->ir);
+ talloc_free(mem_ctx);
}
if (!_mesa_ir_link_shader(ctx, prog))
}
static const fs_reg reg_undef;
-static const fs_reg reg_null(ARF, BRW_ARF_NULL);
+static const fs_reg reg_null_f(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_F);
+static const fs_reg reg_null_d(ARF, BRW_ARF_NULL, BRW_REGISTER_TYPE_D);
int
fs_visitor::virtual_grf_alloc(int size)
this->type = BRW_REGISTER_TYPE_F;
}
+/** Fixed HW reg constructor. */
+fs_reg::fs_reg(enum register_file file, int hw_reg, uint32_t type)
+{
+ init();
+ this->file = file;
+ this->hw_reg = hw_reg;
+ this->type = type;
+}
+
int
brw_type_for_base_type(const struct glsl_type *type)
{
assert(!"not reached: bad math opcode");
return NULL;
}
+
+ /* Can't do hstride == 0 args to gen6 math, so expand it out. We
+ * might be able to do better by doing execsize = 1 math and then
+ * expanding that result out, but we would need to be careful with
+ * masking.
+ */
+ if (intel->gen >= 6 && src.file == UNIFORM) {
+ fs_reg expanded = fs_reg(this, glsl_type::float_type);
+ emit(fs_inst(BRW_OPCODE_MOV, expanded, src));
+ src = expanded;
+ }
+
fs_inst *inst = emit(fs_inst(opcode, dst, src));
- inst->base_mrf = 2;
- inst->mlen = 1;
+ if (intel->gen < 6) {
+ inst->base_mrf = 2;
+ inst->mlen = 1;
+ }
return inst;
}
fs_inst *
fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src0, fs_reg src1)
{
+ int base_mrf = 2;
+ fs_inst *inst;
+
assert(opcode == FS_OPCODE_POW);
- fs_inst *inst = emit(fs_inst(opcode, dst, src0, src1));
+ if (intel->gen >= 6) {
+ /* Can't do hstride == 0 args to gen6 math, so expand it out. */
+ if (src0.file == UNIFORM) {
+ fs_reg expanded = fs_reg(this, glsl_type::float_type);
+ emit(fs_inst(BRW_OPCODE_MOV, expanded, src0));
+ src0 = expanded;
+ }
+
+ if (src1.file == UNIFORM) {
+ fs_reg expanded = fs_reg(this, glsl_type::float_type);
+ emit(fs_inst(BRW_OPCODE_MOV, expanded, src1));
+ src1 = expanded;
+ }
- inst->base_mrf = 2;
- inst->mlen = 2;
+ inst = emit(fs_inst(opcode, dst, src0, src1));
+ } else {
+ emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1));
+ inst = emit(fs_inst(opcode, dst, src0, reg_null_f));
+ inst->base_mrf = base_mrf;
+ inst->mlen = 2;
+ }
return inst;
}
switch (ir->operation) {
case ir_unop_logic_not:
+ /* Note that BRW_OPCODE_NOT is not appropriate here, since it is
+ * ones complement of the whole register, not just bit 0.
+ */
emit(fs_inst(BRW_OPCODE_ADD, this->result, op[0], fs_reg(-1)));
break;
case ir_unop_neg:
emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(0.0f)));
- inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)));
inst->conditional_mod = BRW_CONDITIONAL_G;
inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(1.0f)));
inst->predicated = true;
- inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, op[0], fs_reg(0.0f)));
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f)));
inst->conditional_mod = BRW_CONDITIONAL_L;
inst = emit(fs_inst(BRW_OPCODE_MOV, this->result, fs_reg(-1.0f)));
inst->predicated = true;
case ir_unop_i2f:
case ir_unop_b2f:
case ir_unop_b2i:
- emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
- break;
case ir_unop_f2i:
emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
break;
case ir_unop_i2b:
inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ inst = emit(fs_inst(BRW_OPCODE_AND, this->result,
+ this->result, fs_reg(1)));
+ break;
case ir_unop_trunc:
- emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
+ emit(fs_inst(BRW_OPCODE_RNDZ, this->result, op[0]));
break;
case ir_unop_ceil:
- op[0].negate = ~op[0].negate;
+ op[0].negate = !op[0].negate;
inst = emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
this->result.negate = true;
break;
case ir_unop_fract:
inst = emit(fs_inst(BRW_OPCODE_FRC, this->result, op[0]));
break;
+ case ir_unop_round_even:
+ emit(fs_inst(BRW_OPCODE_RNDE, this->result, op[0]));
+ break;
case ir_binop_min:
inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], op[1]));
assert(r.file != BAD_FILE);
if (ir->condition) {
- /* Get the condition bool into the predicate. */
- ir->condition->accept(this);
- inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null, this->result, fs_reg(0)));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ emit_bool_to_cond_code(ir->condition);
}
if (ir->lhs->type->is_scalar() ||
*/
assert(ir->op == ir_txb || ir->op == ir_txl);
- for (int i = 0; i < ir->coordinate->type->vector_elements * 2;) {
+ for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2),
coordinate));
coordinate.reg_offset++;
void
fs_visitor::visit(ir_texture *ir)
{
+ int sampler;
fs_inst *inst = NULL;
ir->coordinate->accept(this);
/* Should be lowered by do_lower_texture_projection */
assert(!ir->projector);
+ sampler = _mesa_get_sampler_uniform_value(ir->sampler,
+ ctx->Shader.CurrentProgram,
+ &brw->fragment_program->Base);
+ sampler = c->fp->program.Base.SamplerUnits[sampler];
+
+ /* The 965 requires the EU to do the normalization of GL rectangle
+ * texture coordinates. We use the program parameter state
+ * tracking to get the scaling factor.
+ */
+ if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) {
+ struct gl_program_parameter_list *params = c->fp->program.Base.Parameters;
+ int tokens[STATE_LENGTH] = {
+ STATE_INTERNAL,
+ STATE_TEXRECT_SCALE,
+ sampler,
+ 0,
+ 0
+ };
+
+ fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
+ fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
+ GLuint index = _mesa_add_state_reference(params,
+ (gl_state_index *)tokens);
+ float *vec_values = this->fp->Base.Parameters->ParameterValues[index];
+
+ c->prog_data.param[c->prog_data.nr_params++] = &vec_values[0];
+ c->prog_data.param[c->prog_data.nr_params++] = &vec_values[1];
+
+ fs_reg dst = fs_reg(this, ir->coordinate->type);
+ fs_reg src = coordinate;
+ coordinate = dst;
+
+ emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_x));
+ dst.reg_offset++;
+ src.reg_offset++;
+ emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_y));
+ }
+
/* Writemasking doesn't eliminate channels on SIMD8 texture
* samples, so don't worry about them.
*/
inst = emit_texture_gen5(ir, dst, coordinate);
}
- inst->sampler =
- _mesa_get_sampler_uniform_value(ir->sampler,
- ctx->Shader.CurrentProgram,
- &brw->fragment_program->Base);
- inst->sampler = c->fp->program.Base.SamplerUnits[inst->sampler];
+ inst->sampler = sampler;
this->result = dst;
assert(ir->condition == NULL); /* FINISHME */
- emit(fs_inst(FS_OPCODE_DISCARD_NOT, temp, reg_null));
- emit(fs_inst(FS_OPCODE_DISCARD_AND, reg_null, temp));
+ emit(fs_inst(FS_OPCODE_DISCARD_NOT, temp, reg_null_d));
+ emit(fs_inst(FS_OPCODE_DISCARD_AND, reg_null_d, temp));
kill_emitted = true;
}
}
}
+void
+fs_visitor::emit_bool_to_cond_code(ir_rvalue *ir)
+{
+ ir_expression *expr = ir->as_expression();
+
+ if (expr) {
+ fs_reg op[2];
+ fs_inst *inst;
+
+ for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
+ assert(expr->operands[i]->type->is_scalar());
+
+ expr->operands[i]->accept(this);
+ op[i] = this->result;
+ }
+
+ switch (expr->operation) {
+ case ir_unop_logic_not:
+ inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d, op[0], fs_reg(1)));
+ inst->conditional_mod = BRW_CONDITIONAL_Z;
+ break;
+
+ case ir_binop_logic_xor:
+ inst = emit(fs_inst(BRW_OPCODE_XOR, reg_null_d, op[0], op[1]));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ break;
+
+ case ir_binop_logic_or:
+ inst = emit(fs_inst(BRW_OPCODE_OR, reg_null_d, op[0], op[1]));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ break;
+
+ case ir_binop_logic_and:
+ inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d, op[0], op[1]));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ break;
+
+ case ir_unop_f2b:
+ if (intel->gen >= 6) {
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d,
+ op[0], fs_reg(0.0f)));
+ } else {
+ inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, op[0]));
+ }
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ break;
+
+ case ir_unop_i2b:
+ if (intel->gen >= 6) {
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], fs_reg(0)));
+ } else {
+ inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, op[0]));
+ }
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ break;
+
+ case ir_binop_greater:
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
+ inst->conditional_mod = BRW_CONDITIONAL_G;
+ break;
+ case ir_binop_gequal:
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
+ inst->conditional_mod = BRW_CONDITIONAL_GE;
+ break;
+ case ir_binop_less:
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
+ inst->conditional_mod = BRW_CONDITIONAL_L;
+ break;
+ case ir_binop_lequal:
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
+ inst->conditional_mod = BRW_CONDITIONAL_LE;
+ break;
+ case ir_binop_equal:
+ case ir_binop_all_equal:
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
+ inst->conditional_mod = BRW_CONDITIONAL_Z;
+ break;
+ case ir_binop_nequal:
+ case ir_binop_any_nequal:
+ inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d, op[0], op[1]));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ break;
+ default:
+ assert(!"not reached");
+ this->fail = true;
+ break;
+ }
+ return;
+ }
+
+ ir->accept(this);
+
+ if (intel->gen >= 6) {
+ fs_inst *inst = emit(fs_inst(BRW_OPCODE_AND, reg_null_d,
+ this->result, fs_reg(1)));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ } else {
+ fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, reg_null_d, this->result));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ }
+}
+
void
fs_visitor::visit(ir_if *ir)
{
*/
this->base_ir = ir->condition;
- /* Generate the condition into the condition code. */
- ir->condition->accept(this);
- inst = emit(fs_inst(BRW_OPCODE_MOV, fs_reg(brw_null_reg()), this->result));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ emit_bool_to_cond_code(ir->condition);
inst = emit(fs_inst(BRW_OPCODE_IF));
inst->predicated = true;
this->base_ir = ir->to;
ir->to->accept(this);
- fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null,
+ fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP, reg_null_d,
counter, this->result));
switch (ir->cmp) {
case ir_binop_equal:
/* If the pixel centers end up used, the setup is the same as for gen4. */
this->current_annotation = "compute pixel centers";
- this->pixel_x = fs_reg(this, glsl_type::uint_type);
- this->pixel_y = fs_reg(this, glsl_type::uint_type);
- this->pixel_x.type = BRW_REGISTER_TYPE_UW;
- this->pixel_y.type = BRW_REGISTER_TYPE_UW;
+ fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
+ fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
+ int_pixel_x.type = BRW_REGISTER_TYPE_UW;
+ int_pixel_y.type = BRW_REGISTER_TYPE_UW;
emit(fs_inst(BRW_OPCODE_ADD,
- this->pixel_x,
+ int_pixel_x,
fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
fs_reg(brw_imm_v(0x10101010))));
emit(fs_inst(BRW_OPCODE_ADD,
- this->pixel_y,
+ int_pixel_y,
fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
fs_reg(brw_imm_v(0x11001100))));
+ /* As of gen6, we can no longer mix float and int sources. We have
+ * to turn the integer pixel centers into floats for their actual
+ * use.
+ */
+ this->pixel_x = fs_reg(this, glsl_type::float_type);
+ this->pixel_y = fs_reg(this, glsl_type::float_type);
+ emit(fs_inst(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x));
+ emit(fs_inst(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y));
+
this->current_annotation = "compute 1/pos.w";
this->wpos_w = fs_reg(brw_vec8_grf(c->key.source_w_reg, 0));
this->pixel_w = fs_reg(this, glsl_type::float_type);
break;
}
- assert(inst->mlen >= 1);
+ if (intel->gen >= 6) {
+ assert(inst->mlen == 0);
- if (inst->opcode == FS_OPCODE_POW) {
- brw_MOV(p, brw_message_reg(inst->base_mrf + 1), src[1]);
- }
+ if (inst->opcode == FS_OPCODE_POW) {
+ brw_math2(p, dst, op, src[0], src[1]);
+ } else {
+ brw_math(p, dst,
+ op,
+ inst->saturate ? BRW_MATH_SATURATE_SATURATE :
+ BRW_MATH_SATURATE_NONE,
+ 0, src[0],
+ BRW_MATH_DATA_VECTOR,
+ BRW_MATH_PRECISION_FULL);
+ }
+ } else {
+ assert(inst->mlen >= 1);
- brw_math(p, dst,
- op,
- inst->saturate ? BRW_MATH_SATURATE_SATURATE :
- BRW_MATH_SATURATE_NONE,
- inst->base_mrf, src[0],
- BRW_MATH_DATA_VECTOR,
- BRW_MATH_PRECISION_FULL);
+ brw_math(p, dst,
+ op,
+ inst->saturate ? BRW_MATH_SATURATE_SATURATE :
+ BRW_MATH_SATURATE_NONE,
+ inst->base_mrf, src[0],
+ BRW_MATH_DATA_VECTOR,
+ BRW_MATH_PRECISION_FULL);
+ }
}
void
*/
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
if (inst->shadow_compare) {
- assert(inst->mlen == 5);
+ assert(inst->mlen == 6);
} else {
- assert(inst->mlen <= 6);
+ assert(inst->mlen <= 4);
}
break;
case FS_OPCODE_TXB:
if (inst->shadow_compare) {
- assert(inst->mlen == 5);
+ assert(inst->mlen == 6);
msg_type = BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE;
} else {
- assert(inst->mlen == 8);
+ assert(inst->mlen == 9);
msg_type = BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS;
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD16;
}
assign_reg(int *reg_hw_locations, fs_reg *reg)
{
if (reg->file == GRF && reg->reg != 0) {
+ assert(reg->reg_offset >= 0);
reg->hw_reg = reg_hw_locations[reg->reg] + reg->reg_offset;
reg->reg = 0;
}
aligned_pair_class = class_count;
classes[aligned_pair_class] = ra_alloc_reg_class(regs);
+ class_sizes[aligned_pair_class] = 2;
class_base_reg[aligned_pair_class] = 0;
class_reg_count[aligned_pair_class] = 0;
int start = (this->first_non_payload_grf & 1) ? 1 : 0;
}
}
- assert(hw_reg != -1);
+ assert(hw_reg >= 0);
hw_reg_mapping[i] = this->first_non_payload_grf + hw_reg;
last_grf = MAX2(last_grf,
hw_reg_mapping[i] + this->virtual_grf_sizes[i] - 1);
talloc_free(regs);
}
+/**
+ * Split large virtual GRFs into separate components if we can.
+ *
+ * This is mostly duplicated with what brw_fs_vector_splitting does,
+ * but that's really conservative because it's afraid of doing
+ * splitting that doesn't result in real progress after the rest of
+ * the optimization phases, which would cause infinite looping in
+ * optimization. We can do it once here, safely. This also has the
+ * opportunity to split interpolated values, or maybe even uniforms,
+ * which we don't have at the IR level.
+ *
+ * We want to split, because virtual GRFs are what we register
+ * allocate and spill (due to contiguousness requirements for some
+ * instructions), and they're what we naturally generate in the
+ * codegen process, but most virtual GRFs don't actually need to be
+ * contiguous sets of GRFs. If we split, we'll end up with reduced
+ * live intervals and better dead code elimination and coalescing.
+ */
+void
+fs_visitor::split_virtual_grfs()
+{
+ int num_vars = this->virtual_grf_next;
+ bool split_grf[num_vars];
+ int new_virtual_grf[num_vars];
+
+ /* Try to split anything > 0 sized. */
+ for (int i = 0; i < num_vars; i++) {
+ if (this->virtual_grf_sizes[i] != 1)
+ split_grf[i] = true;
+ else
+ split_grf[i] = false;
+ }
+
+ if (brw->has_pln) {
+ /* PLN opcodes rely on the delta_xy being contiguous. */
+ split_grf[this->delta_x.reg] = false;
+ }
+
+ foreach_iter(exec_list_iterator, iter, this->instructions) {
+ fs_inst *inst = (fs_inst *)iter.get();
+
+ /* Texturing produces 4 contiguous registers, so no splitting. */
+ if ((inst->opcode == FS_OPCODE_TEX ||
+ inst->opcode == FS_OPCODE_TXB ||
+ inst->opcode == FS_OPCODE_TXL) &&
+ inst->dst.file == GRF) {
+ split_grf[inst->dst.reg] = false;
+ }
+ }
+
+ /* Allocate new space for split regs. Note that the virtual
+ * numbers will be contiguous.
+ */
+ for (int i = 0; i < num_vars; i++) {
+ if (split_grf[i]) {
+ new_virtual_grf[i] = virtual_grf_alloc(1);
+ for (int j = 2; j < this->virtual_grf_sizes[i]; j++) {
+ int reg = virtual_grf_alloc(1);
+ assert(reg == new_virtual_grf[i] + j - 1);
+ }
+ this->virtual_grf_sizes[i] = 1;
+ }
+ }
+
+ foreach_iter(exec_list_iterator, iter, this->instructions) {
+ fs_inst *inst = (fs_inst *)iter.get();
+
+ if (inst->dst.file == GRF &&
+ split_grf[inst->dst.reg] &&
+ inst->dst.reg_offset != 0) {
+ inst->dst.reg = (new_virtual_grf[inst->dst.reg] +
+ inst->dst.reg_offset - 1);
+ inst->dst.reg_offset = 0;
+ }
+ for (int i = 0; i < 3; i++) {
+ if (inst->src[i].file == GRF &&
+ split_grf[inst->src[i].reg] &&
+ inst->src[i].reg_offset != 0) {
+ inst->src[i].reg = (new_virtual_grf[inst->src[i].reg] +
+ inst->src[i].reg_offset - 1);
+ inst->src[i].reg_offset = 0;
+ }
+ }
+ }
+}
+
void
fs_visitor::calculate_live_intervals()
{
continue;
}
+ /* Update live interval so we don't have to recalculate. */
+ this->virtual_grf_use[inst->src[0].reg] = MAX2(virtual_grf_use[inst->src[0].reg],
+ virtual_grf_use[inst->dst.reg]);
+
/* Rewrite the later usage to point at the source of the move to
* be removed.
*/
return progress;
}
+
+bool
+fs_visitor::compute_to_mrf()
+{
+ bool progress = false;
+ int next_ip = 0;
+
+ foreach_iter(exec_list_iterator, iter, this->instructions) {
+ fs_inst *inst = (fs_inst *)iter.get();
+
+ int ip = next_ip;
+ next_ip++;
+
+ if (inst->opcode != BRW_OPCODE_MOV ||
+ inst->predicated ||
+ inst->dst.file != MRF || inst->src[0].file != GRF ||
+ inst->dst.type != inst->src[0].type ||
+ inst->src[0].abs || inst->src[0].negate)
+ continue;
+
+ /* Can't compute-to-MRF this GRF if someone else was going to
+ * read it later.
+ */
+ if (this->virtual_grf_use[inst->src[0].reg] > ip)
+ continue;
+
+ /* Found a move of a GRF to a MRF. Let's see if we can go
+ * rewrite the thing that made this GRF to write into the MRF.
+ */
+ bool found = false;
+ fs_inst *scan_inst;
+ for (scan_inst = (fs_inst *)inst->prev;
+ scan_inst->prev != NULL;
+ scan_inst = (fs_inst *)scan_inst->prev) {
+ /* We don't handle flow control here. Most computation of
+ * values that end up in MRFs are shortly before the MRF
+ * write anyway.
+ */
+ if (scan_inst->opcode == BRW_OPCODE_DO ||
+ scan_inst->opcode == BRW_OPCODE_WHILE ||
+ scan_inst->opcode == BRW_OPCODE_ENDIF) {
+ break;
+ }
+
+ /* You can't read from an MRF, so if someone else reads our
+ * MRF's source GRF that we wanted to rewrite, that stops us.
+ */
+ bool interfered = false;
+ for (int i = 0; i < 3; i++) {
+ if (scan_inst->src[i].file == GRF &&
+ scan_inst->src[i].reg == inst->src[0].reg &&
+ scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
+ interfered = true;
+ }
+ }
+ if (interfered)
+ break;
+
+ if (scan_inst->dst.file == MRF &&
+ scan_inst->dst.hw_reg == inst->dst.hw_reg) {
+ /* Somebody else wrote our MRF here, so we can't can't
+ * compute-to-MRF before that.
+ */
+ break;
+ }
+
+ if (scan_inst->mlen > 0) {
+ /* Found a SEND instruction, which will do some amount of
+ * implied write that may overwrite our MRF that we were
+ * hoping to compute-to-MRF somewhere above it. Nothing
+ * we have implied-writes more than 2 MRFs from base_mrf,
+ * though.
+ */
+ int implied_write_len = MIN2(scan_inst->mlen, 2);
+ if (inst->dst.hw_reg >= scan_inst->base_mrf &&
+ inst->dst.hw_reg < scan_inst->base_mrf + implied_write_len) {
+ break;
+ }
+ }
+
+ if (scan_inst->dst.file == GRF &&
+ scan_inst->dst.reg == inst->src[0].reg) {
+ /* Found the last thing to write our reg we want to turn
+ * into a compute-to-MRF.
+ */
+
+ if (scan_inst->opcode == FS_OPCODE_TEX) {
+ /* texturing writes several continuous regs, so we can't
+ * compute-to-mrf that.
+ */
+ break;
+ }
+
+ /* If it's predicated, it (probably) didn't populate all
+ * the channels.
+ */
+ if (scan_inst->predicated)
+ break;
+
+ /* SEND instructions can't have MRF as a destination. */
+ if (scan_inst->mlen)
+ break;
+
+ if (intel->gen >= 6) {
+ /* gen6 math instructions must have the destination be
+ * GRF, so no compute-to-MRF for them.
+ */
+ if (scan_inst->opcode == FS_OPCODE_RCP ||
+ scan_inst->opcode == FS_OPCODE_RSQ ||
+ scan_inst->opcode == FS_OPCODE_SQRT ||
+ scan_inst->opcode == FS_OPCODE_EXP2 ||
+ scan_inst->opcode == FS_OPCODE_LOG2 ||
+ scan_inst->opcode == FS_OPCODE_SIN ||
+ scan_inst->opcode == FS_OPCODE_COS ||
+ scan_inst->opcode == FS_OPCODE_POW) {
+ break;
+ }
+ }
+
+ if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
+ /* Found the creator of our MRF's source value. */
+ found = true;
+ break;
+ }
+ }
+ }
+ if (found) {
+ scan_inst->dst.file = MRF;
+ scan_inst->dst.hw_reg = inst->dst.hw_reg;
+ scan_inst->saturate |= inst->saturate;
+ inst->remove();
+ progress = true;
+ }
+ }
+
+ return progress;
+}
+
bool
fs_visitor::virtual_grf_interferes(int a, int b)
{
case BRW_OPCODE_RNDD:
brw_RNDD(p, dst, src[0]);
break;
+ case BRW_OPCODE_RNDE:
+ brw_RNDE(p, dst, src[0]);
+ break;
case BRW_OPCODE_RNDZ:
brw_RNDZ(p, dst, src[0]);
break;
{
struct brw_compile *p = &c->func;
struct intel_context *intel = &brw->intel;
- GLcontext *ctx = &intel->ctx;
- struct brw_shader *shader = NULL;
+ struct gl_context *ctx = &intel->ctx;
struct gl_shader_program *prog = ctx->Shader.CurrentProgram;
if (!prog)
return GL_FALSE;
- if (!using_new_fs)
- return GL_FALSE;
-
- for (unsigned int i = 0; i < prog->_NumLinkedShaders; i++) {
- if (prog->_LinkedShaders[i]->Type == GL_FRAGMENT_SHADER) {
- shader = (struct brw_shader *)prog->_LinkedShaders[i];
- break;
- }
- }
+ struct brw_shader *shader =
+ (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
if (!shader)
return GL_FALSE;
}
v.emit_fb_writes();
+
+ v.split_virtual_grfs();
+
v.assign_curb_setup();
v.assign_urb_setup();
bool progress;
do {
progress = false;
-
v.calculate_live_intervals();
progress = v.propagate_constants() || progress;
progress = v.register_coalesce() || progress;
+ progress = v.compute_to_mrf() || progress;
progress = v.dead_code_eliminate() || progress;
} while (progress);
printf(" %s\n", last_annotation_string);
}
brw_disasm(stdout, &p->store[i], intel->gen);
+ printf("0x%08x 0x%08x 0x%08x 0x%08x\n",
+ ((uint32_t *)&p->store[i])[3],
+ ((uint32_t *)&p->store[i])[2],
+ ((uint32_t *)&p->store[i])[1],
+ ((uint32_t *)&p->store[i])[0]);
}
printf("\n");
}