#include "brw_wm.h"
#include "talloc.h"
}
+#include "brw_fs.h"
#include "../glsl/glsl_types.h"
#include "../glsl/ir_optimization.h"
#include "../glsl/ir_print_visitor.h"
-enum register_file {
- ARF = BRW_ARCHITECTURE_REGISTER_FILE,
- GRF = BRW_GENERAL_REGISTER_FILE,
- MRF = BRW_MESSAGE_REGISTER_FILE,
- IMM = BRW_IMMEDIATE_VALUE,
- FIXED_HW_REG, /* a struct brw_reg */
- UNIFORM, /* prog_data->params[hw_reg] */
- BAD_FILE
-};
-
-enum fs_opcodes {
- FS_OPCODE_FB_WRITE = 256,
- FS_OPCODE_RCP,
- FS_OPCODE_RSQ,
- FS_OPCODE_SQRT,
- FS_OPCODE_EXP2,
- FS_OPCODE_LOG2,
- FS_OPCODE_POW,
- FS_OPCODE_SIN,
- FS_OPCODE_COS,
- FS_OPCODE_DDX,
- FS_OPCODE_DDY,
- FS_OPCODE_LINTERP,
- FS_OPCODE_TEX,
- FS_OPCODE_TXB,
- FS_OPCODE_TXL,
- FS_OPCODE_DISCARD,
-};
-
static int using_new_fs = -1;
static struct brw_reg brw_reg_from_fs_reg(class fs_reg *reg);
struct gl_shader *
-brw_new_shader(GLcontext *ctx, GLuint name, GLuint type)
+brw_new_shader(struct gl_context *ctx, GLuint name, GLuint type)
{
struct brw_shader *shader;
}
struct gl_shader_program *
-brw_new_shader_program(GLcontext *ctx, GLuint name)
+brw_new_shader_program(struct gl_context *ctx, GLuint name)
{
struct brw_shader_program *prog;
prog = talloc_zero(NULL, struct brw_shader_program);
}
GLboolean
-brw_compile_shader(GLcontext *ctx, struct gl_shader *shader)
+brw_compile_shader(struct gl_context *ctx, struct gl_shader *shader)
{
if (!_mesa_ir_compile_shader(ctx, shader))
return GL_FALSE;
}
GLboolean
-brw_link_shader(GLcontext *ctx, struct gl_shader_program *prog)
+brw_link_shader(struct gl_context *ctx, struct gl_shader_program *prog)
{
- if (using_new_fs == -1)
- using_new_fs = getenv("INTEL_NEW_FS") != NULL;
+ struct intel_context *intel = intel_context(ctx);
+
+ if (using_new_fs == -1) {
+ if (intel->gen >= 6)
+ using_new_fs = 1;
+ else
+ using_new_fs = getenv("INTEL_NEW_FS") != NULL;
+ }
for (unsigned i = 0; i < prog->_NumLinkedShaders; i++) {
struct brw_shader *shader = (struct brw_shader *)prog->_LinkedShaders[i];
do_sub_to_add_neg(shader->ir);
do_explog_to_explog2(shader->ir);
do_lower_texture_projection(shader->ir);
+ brw_do_cubemap_normalize(shader->ir);
do {
progress = false;
GL_TRUE, /* temp */
GL_TRUE /* uniform */
) || progress;
+ if (intel->gen == 6) {
+ progress = do_if_to_cond_assign(shader->ir) || progress;
+ }
} while (progress);
validate_ir_tree(shader->ir);
}
}
-class fs_reg {
-public:
- /* Callers of this talloc-based new need not call delete. It's
- * easier to just talloc_free 'ctx' (or any of its ancestors). */
- static void* operator new(size_t size, void *ctx)
- {
- void *node;
-
- node = talloc_size(ctx, size);
- assert(node != NULL);
-
- return node;
- }
-
- void init()
- {
- this->reg = 0;
- this->reg_offset = 0;
- this->negate = 0;
- this->abs = 0;
- this->hw_reg = -1;
- }
-
- /** Generic unset register constructor. */
- fs_reg()
- {
- init();
- this->file = BAD_FILE;
- }
-
- /** Immediate value constructor. */
- fs_reg(float f)
- {
- init();
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_F;
- this->imm.f = f;
- }
-
- /** Immediate value constructor. */
- fs_reg(int32_t i)
- {
- init();
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_D;
- this->imm.i = i;
- }
-
- /** Immediate value constructor. */
- fs_reg(uint32_t u)
- {
- init();
- this->file = IMM;
- this->type = BRW_REGISTER_TYPE_UD;
- this->imm.u = u;
- }
-
- /** Fixed brw_reg Immediate value constructor. */
- fs_reg(struct brw_reg fixed_hw_reg)
- {
- init();
- this->file = FIXED_HW_REG;
- this->fixed_hw_reg = fixed_hw_reg;
- this->type = fixed_hw_reg.type;
- }
-
- fs_reg(enum register_file file, int hw_reg);
- fs_reg(class fs_visitor *v, const struct glsl_type *type);
-
- /** Register file: ARF, GRF, MRF, IMM. */
- enum register_file file;
- /** virtual register number. 0 = fixed hw reg */
- int reg;
- /** Offset within the virtual register. */
- int reg_offset;
- /** HW register number. Generally unset until register allocation. */
- int hw_reg;
- /** Register type. BRW_REGISTER_TYPE_* */
- int type;
- bool negate;
- bool abs;
- struct brw_reg fixed_hw_reg;
-
- /** Value for file == BRW_IMMMEDIATE_FILE */
- union {
- int32_t i;
- uint32_t u;
- float f;
- } imm;
-};
-
static const fs_reg reg_undef;
static const fs_reg reg_null(ARF, BRW_ARF_NULL);
-class fs_inst : public exec_node {
-public:
- /* Callers of this talloc-based new need not call delete. It's
- * easier to just talloc_free 'ctx' (or any of its ancestors). */
- static void* operator new(size_t size, void *ctx)
- {
- void *node;
-
- node = talloc_zero_size(ctx, size);
- assert(node != NULL);
-
- return node;
- }
-
- void init()
- {
- this->opcode = BRW_OPCODE_NOP;
- this->saturate = false;
- this->conditional_mod = BRW_CONDITIONAL_NONE;
- this->predicated = false;
- this->sampler = 0;
- this->target = 0;
- this->eot = false;
- this->shadow_compare = false;
- }
-
- fs_inst()
- {
- init();
- }
-
- fs_inst(int opcode)
- {
- init();
- this->opcode = opcode;
- }
-
- fs_inst(int opcode, fs_reg dst, fs_reg src0)
- {
- init();
- this->opcode = opcode;
- this->dst = dst;
- this->src[0] = src0;
- }
-
- fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1)
- {
- init();
- this->opcode = opcode;
- this->dst = dst;
- this->src[0] = src0;
- this->src[1] = src1;
- }
-
- fs_inst(int opcode, fs_reg dst, fs_reg src0, fs_reg src1, fs_reg src2)
- {
- init();
- this->opcode = opcode;
- this->dst = dst;
- this->src[0] = src0;
- this->src[1] = src1;
- this->src[2] = src2;
- }
-
- int opcode; /* BRW_OPCODE_* or FS_OPCODE_* */
- fs_reg dst;
- fs_reg src[3];
- bool saturate;
- bool predicated;
- int conditional_mod; /**< BRW_CONDITIONAL_* */
-
- int mlen; /**< SEND message length */
- int sampler;
- int target; /**< MRT target. */
- bool eot;
- bool shadow_compare;
-
- /** @{
- * Annotation for the generated IR. One of the two can be set.
- */
- ir_instruction *ir;
- const char *annotation;
- /** @} */
-};
-
-class fs_visitor : public ir_visitor
-{
-public:
-
- fs_visitor(struct brw_wm_compile *c, struct brw_shader *shader)
- {
- this->c = c;
- this->p = &c->func;
- this->brw = p->brw;
- this->fp = brw->fragment_program;
- this->intel = &brw->intel;
- this->ctx = &intel->ctx;
- this->mem_ctx = talloc_new(NULL);
- this->shader = shader;
- this->fail = false;
- this->variable_ht = hash_table_ctor(0,
- hash_table_pointer_hash,
- hash_table_pointer_compare);
-
- this->frag_color = NULL;
- this->frag_data = NULL;
- this->frag_depth = NULL;
- this->first_non_payload_grf = 0;
-
- this->current_annotation = NULL;
- this->annotation_string = NULL;
- this->annotation_ir = NULL;
- this->base_ir = NULL;
-
- this->virtual_grf_sizes = NULL;
- this->virtual_grf_next = 1;
- this->virtual_grf_array_size = 0;
- this->virtual_grf_def = NULL;
- this->virtual_grf_use = NULL;
- }
- ~fs_visitor()
- {
- talloc_free(this->mem_ctx);
- hash_table_dtor(this->variable_ht);
- }
-
- fs_reg *variable_storage(ir_variable *var);
- int virtual_grf_alloc(int size);
-
- void visit(ir_variable *ir);
- void visit(ir_assignment *ir);
- void visit(ir_dereference_variable *ir);
- void visit(ir_dereference_record *ir);
- void visit(ir_dereference_array *ir);
- void visit(ir_expression *ir);
- void visit(ir_texture *ir);
- void visit(ir_if *ir);
- void visit(ir_constant *ir);
- void visit(ir_swizzle *ir);
- void visit(ir_return *ir);
- void visit(ir_loop *ir);
- void visit(ir_loop_jump *ir);
- void visit(ir_discard *ir);
- void visit(ir_call *ir);
- void visit(ir_function *ir);
- void visit(ir_function_signature *ir);
-
- fs_inst *emit(fs_inst inst);
- void assign_curb_setup();
- void calculate_urb_setup();
- void assign_urb_setup();
- void assign_regs();
- void assign_regs_trivial();
- void calculate_live_intervals();
- bool virtual_grf_interferes(int a, int b);
- void generate_code();
- void generate_fb_write(fs_inst *inst);
- void generate_linterp(fs_inst *inst, struct brw_reg dst,
- struct brw_reg *src);
- void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
- void generate_math(fs_inst *inst, struct brw_reg dst, struct brw_reg *src);
- void generate_discard(fs_inst *inst, struct brw_reg temp);
- void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
- void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
-
- void emit_dummy_fs();
- void emit_fragcoord_interpolation(ir_variable *ir);
- void emit_general_interpolation(ir_variable *ir);
- void emit_interpolation_setup_gen4();
- void emit_interpolation_setup_gen6();
- fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate);
- fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate);
- void emit_fb_writes();
- void emit_assignment_writes(fs_reg &l, fs_reg &r,
- const glsl_type *type, bool predicated);
-
- struct brw_reg interp_reg(int location, int channel);
- int setup_uniform_values(int loc, const glsl_type *type);
- void setup_builtin_uniform_values(ir_variable *ir);
-
- struct brw_context *brw;
- const struct gl_fragment_program *fp;
- struct intel_context *intel;
- GLcontext *ctx;
- struct brw_wm_compile *c;
- struct brw_compile *p;
- struct brw_shader *shader;
- void *mem_ctx;
- exec_list instructions;
-
- int *virtual_grf_sizes;
- int virtual_grf_next;
- int virtual_grf_array_size;
- int *virtual_grf_def;
- int *virtual_grf_use;
-
- struct hash_table *variable_ht;
- ir_variable *frag_color, *frag_data, *frag_depth;
- int first_non_payload_grf;
- int urb_setup[FRAG_ATTRIB_MAX];
-
- /** @{ debug annotation info */
- const char *current_annotation;
- ir_instruction *base_ir;
- const char **annotation_string;
- ir_instruction **annotation_ir;
- /** @} */
-
- bool fail;
-
- /* Result of last visit() method. */
- fs_reg result;
-
- fs_reg pixel_x;
- fs_reg pixel_y;
- fs_reg wpos_w;
- fs_reg pixel_w;
- fs_reg delta_x;
- fs_reg delta_y;
-
- int grf_used;
-
-};
-
int
fs_visitor::virtual_grf_alloc(int size)
{
}
}
-void
+fs_reg *
fs_visitor::emit_fragcoord_interpolation(ir_variable *ir)
{
fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
/* gl_FragCoord.w: Already set up in emit_interpolation */
emit(fs_inst(BRW_OPCODE_MOV, wpos, this->wpos_w));
- hash_table_insert(this->variable_ht, reg, ir);
+ return reg;
}
-
-void
+fs_reg *
fs_visitor::emit_general_interpolation(ir_variable *ir)
{
fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
fs_reg(interp)));
attr.reg_offset++;
}
- attr.reg_offset -= type->vector_elements;
- for (unsigned int c = 0; c < type->vector_elements; c++) {
- emit(fs_inst(BRW_OPCODE_MUL,
- attr,
- attr,
- this->pixel_w));
- attr.reg_offset++;
+ if (intel->gen < 6) {
+ attr.reg_offset -= type->vector_elements;
+ for (unsigned int c = 0; c < type->vector_elements; c++) {
+ emit(fs_inst(BRW_OPCODE_MUL,
+ attr,
+ attr,
+ this->pixel_w));
+ attr.reg_offset++;
+ }
}
location++;
}
}
- hash_table_insert(this->variable_ht, reg, ir);
+ return reg;
+}
+
+fs_reg *
+fs_visitor::emit_frontfacing_interpolation(ir_variable *ir)
+{
+ fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
+
+ /* The frontfacing comes in as a bit in the thread payload. */
+ if (intel->gen >= 6) {
+ emit(fs_inst(BRW_OPCODE_ASR,
+ *reg,
+ fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
+ fs_reg(15)));
+ emit(fs_inst(BRW_OPCODE_NOT,
+ *reg,
+ *reg));
+ emit(fs_inst(BRW_OPCODE_AND,
+ *reg,
+ *reg,
+ fs_reg(1)));
+ } else {
+ fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
+ struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
+ /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
+ * us front face
+ */
+ fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP,
+ *reg,
+ fs_reg(r1_6ud),
+ fs_reg(1u << 31)));
+ inst->conditional_mod = BRW_CONDITIONAL_L;
+ emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u)));
+ }
+
+ return reg;
+}
+
+fs_inst *
+fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src)
+{
+ switch (opcode) {
+ case FS_OPCODE_RCP:
+ case FS_OPCODE_RSQ:
+ case FS_OPCODE_SQRT:
+ case FS_OPCODE_EXP2:
+ case FS_OPCODE_LOG2:
+ case FS_OPCODE_SIN:
+ case FS_OPCODE_COS:
+ break;
+ default:
+ assert(!"not reached: bad math opcode");
+ return NULL;
+ }
+
+ /* Can't do hstride == 0 args to gen6 math, so expand it out. We
+ * might be able to do better by doing execsize = 1 math and then
+ * expanding that result out, but we would need to be careful with
+ * masking.
+ */
+ if (intel->gen >= 6 && src.file == UNIFORM) {
+ fs_reg expanded = fs_reg(this, glsl_type::float_type);
+ emit(fs_inst(BRW_OPCODE_MOV, expanded, src));
+ src = expanded;
+ }
+
+ fs_inst *inst = emit(fs_inst(opcode, dst, src));
+
+ if (intel->gen < 6) {
+ inst->base_mrf = 2;
+ inst->mlen = 1;
+ }
+
+ return inst;
+}
+
+fs_inst *
+fs_visitor::emit_math(fs_opcodes opcode, fs_reg dst, fs_reg src0, fs_reg src1)
+{
+ int base_mrf = 2;
+ fs_inst *inst;
+
+ assert(opcode == FS_OPCODE_POW);
+
+ if (intel->gen >= 6) {
+ /* Can't do hstride == 0 args to gen6 math, so expand it out. */
+ if (src0.file == UNIFORM) {
+ fs_reg expanded = fs_reg(this, glsl_type::float_type);
+ emit(fs_inst(BRW_OPCODE_MOV, expanded, src0));
+ src0 = expanded;
+ }
+
+ if (src1.file == UNIFORM) {
+ fs_reg expanded = fs_reg(this, glsl_type::float_type);
+ emit(fs_inst(BRW_OPCODE_MOV, expanded, src1));
+ src1 = expanded;
+ }
+
+ inst = emit(fs_inst(opcode, dst, src0, src1));
+ } else {
+ emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + 1), src1));
+ inst = emit(fs_inst(opcode, dst, src0, reg_null));
+
+ inst->base_mrf = base_mrf;
+ inst->mlen = 2;
+ }
+ return inst;
}
void
if (ir->mode == ir_var_in) {
if (!strcmp(ir->name, "gl_FragCoord")) {
- emit_fragcoord_interpolation(ir);
- return;
+ reg = emit_fragcoord_interpolation(ir);
} else if (!strcmp(ir->name, "gl_FrontFacing")) {
- reg = new(this->mem_ctx) fs_reg(this, ir->type);
- struct brw_reg r1_6ud = retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_UD);
- /* bit 31 is "primitive is back face", so checking < (1 << 31) gives
- * us front face
- */
- fs_inst *inst = emit(fs_inst(BRW_OPCODE_CMP,
- *reg,
- fs_reg(r1_6ud),
- fs_reg(1u << 31)));
- inst->conditional_mod = BRW_CONDITIONAL_L;
- emit(fs_inst(BRW_OPCODE_AND, *reg, *reg, fs_reg(1u)));
+ reg = emit_frontfacing_interpolation(ir);
} else {
- emit_general_interpolation(ir);
- return;
+ reg = emit_general_interpolation(ir);
}
+ assert(reg);
+ hash_table_insert(this->variable_ht, reg, ir);
+ return;
}
if (ir->mode == ir_var_uniform) {
break;
case ir_unop_rcp:
- emit(fs_inst(FS_OPCODE_RCP, this->result, op[0]));
+ emit_math(FS_OPCODE_RCP, this->result, op[0]);
break;
case ir_unop_exp2:
- emit(fs_inst(FS_OPCODE_EXP2, this->result, op[0]));
+ emit_math(FS_OPCODE_EXP2, this->result, op[0]);
break;
case ir_unop_log2:
- emit(fs_inst(FS_OPCODE_LOG2, this->result, op[0]));
+ emit_math(FS_OPCODE_LOG2, this->result, op[0]);
break;
case ir_unop_exp:
case ir_unop_log:
assert(!"not reached: should be handled by ir_explog_to_explog2");
break;
case ir_unop_sin:
- emit(fs_inst(FS_OPCODE_SIN, this->result, op[0]));
+ emit_math(FS_OPCODE_SIN, this->result, op[0]);
break;
case ir_unop_cos:
- emit(fs_inst(FS_OPCODE_COS, this->result, op[0]));
+ emit_math(FS_OPCODE_COS, this->result, op[0]);
break;
case ir_unop_dFdx:
break;
case ir_unop_sqrt:
- emit(fs_inst(FS_OPCODE_SQRT, this->result, op[0]));
+ emit_math(FS_OPCODE_SQRT, this->result, op[0]);
break;
case ir_unop_rsq:
- emit(fs_inst(FS_OPCODE_RSQ, this->result, op[0]));
+ emit_math(FS_OPCODE_RSQ, this->result, op[0]);
break;
case ir_unop_i2f:
case ir_unop_b2f:
case ir_unop_b2i:
- emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
- break;
case ir_unop_f2i:
emit(fs_inst(BRW_OPCODE_MOV, this->result, op[0]));
break;
case ir_unop_i2b:
inst = emit(fs_inst(BRW_OPCODE_CMP, this->result, op[0], fs_reg(0.0f)));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ inst = emit(fs_inst(BRW_OPCODE_AND, this->result,
+ this->result, fs_reg(1)));
+ break;
case ir_unop_trunc:
emit(fs_inst(BRW_OPCODE_RNDD, this->result, op[0]));
break;
case ir_binop_pow:
- inst = emit(fs_inst(FS_OPCODE_POW, this->result, op[0], op[1]));
+ emit_math(FS_OPCODE_POW, this->result, op[0], op[1]);
break;
case ir_unop_bit_not:
fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate)
{
int mlen;
- int base_mrf = 2;
+ int base_mrf = 1;
bool simd16 = false;
fs_reg orig_dst;
+ /* g0 header. */
+ mlen = 1;
+
if (ir->shadow_comparitor) {
- for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
+ for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
coordinate));
coordinate.reg_offset++;
- mlen++;
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
- mlen = 3;
+ mlen += 3;
if (ir->op == ir_tex) {
/* There's no plain shadow compare message, so we use shadow
emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
mlen++;
} else if (ir->op == ir_tex) {
- for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
+ for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
coordinate));
coordinate.reg_offset++;
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
- mlen = 3;
+ mlen += 3;
} else {
/* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare bias/lod
* instructions. We'll need to do SIMD16 here.
*/
assert(ir->op == ir_txb || ir->op == ir_txl);
- for (mlen = 0; mlen < ir->coordinate->type->vector_elements * 2;) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
+ for (int i = 0; i < ir->coordinate->type->vector_elements * 2;) {
+ emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i * 2),
coordinate));
coordinate.reg_offset++;
- mlen++;
-
- /* The unused upper half. */
- mlen++;
}
/* lod/bias appears after u/v/r. */
- mlen = 6;
+ mlen += 6;
if (ir->op == ir_txb) {
ir->lod_info.bias->accept(this);
fs_inst *inst = NULL;
switch (ir->op) {
case ir_tex:
- inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
+ inst = emit(fs_inst(FS_OPCODE_TEX, dst));
break;
case ir_txb:
- inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf)));
+ inst = emit(fs_inst(FS_OPCODE_TXB, dst));
break;
case ir_txl:
- inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf)));
+ inst = emit(fs_inst(FS_OPCODE_TXL, dst));
break;
case ir_txd:
case ir_txf:
assert(!"GLSL 1.30 features unsupported");
break;
}
+ inst->base_mrf = base_mrf;
inst->mlen = mlen;
if (simd16) {
* We don't fill in the unnecessary slots regardless, which may
* look surprising in the disassembly.
*/
- int mlen;
- int base_mrf = 2;
+ int mlen = 1; /* g0 header always present. */
+ int base_mrf = 1;
- for (mlen = 0; mlen < ir->coordinate->type->vector_elements; mlen++) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate));
+ for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen + i),
+ coordinate));
coordinate.reg_offset++;
- mlen++;
}
+ mlen += ir->coordinate->type->vector_elements;
if (ir->shadow_comparitor) {
- mlen = MAX2(mlen, 4);
+ mlen = MAX2(mlen, 5);
ir->shadow_comparitor->accept(this);
emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
fs_inst *inst = NULL;
switch (ir->op) {
case ir_tex:
- inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
+ inst = emit(fs_inst(FS_OPCODE_TEX, dst));
break;
case ir_txb:
ir->lod_info.bias->accept(this);
- mlen = MAX2(mlen, 4);
+ mlen = MAX2(mlen, 5);
emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
mlen++;
- inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf)));
+ inst = emit(fs_inst(FS_OPCODE_TXB, dst));
break;
case ir_txl:
ir->lod_info.lod->accept(this);
- mlen = MAX2(mlen, 4);
+ mlen = MAX2(mlen, 5);
emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result));
mlen++;
- inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf)));
+ inst = emit(fs_inst(FS_OPCODE_TXL, dst));
break;
case ir_txd:
case ir_txf:
assert(!"GLSL 1.30 features unsupported");
break;
}
+ inst->base_mrf = base_mrf;
inst->mlen = mlen;
return inst;
void
fs_visitor::visit(ir_texture *ir)
{
+ int sampler;
fs_inst *inst = NULL;
ir->coordinate->accept(this);
/* Should be lowered by do_lower_texture_projection */
assert(!ir->projector);
+ sampler = _mesa_get_sampler_uniform_value(ir->sampler,
+ ctx->Shader.CurrentProgram,
+ &brw->fragment_program->Base);
+ sampler = c->fp->program.Base.SamplerUnits[sampler];
+
+ /* The 965 requires the EU to do the normalization of GL rectangle
+ * texture coordinates. We use the program parameter state
+ * tracking to get the scaling factor.
+ */
+ if (ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT) {
+ struct gl_program_parameter_list *params = c->fp->program.Base.Parameters;
+ int tokens[STATE_LENGTH] = {
+ STATE_INTERNAL,
+ STATE_TEXRECT_SCALE,
+ sampler,
+ 0,
+ 0
+ };
+
+ fs_reg scale_x = fs_reg(UNIFORM, c->prog_data.nr_params);
+ fs_reg scale_y = fs_reg(UNIFORM, c->prog_data.nr_params + 1);
+ GLuint index = _mesa_add_state_reference(params,
+ (gl_state_index *)tokens);
+ float *vec_values = this->fp->Base.Parameters->ParameterValues[index];
+
+ c->prog_data.param[c->prog_data.nr_params++] = &vec_values[0];
+ c->prog_data.param[c->prog_data.nr_params++] = &vec_values[1];
+
+ fs_reg dst = fs_reg(this, ir->coordinate->type);
+ fs_reg src = coordinate;
+ coordinate = dst;
+
+ emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_x));
+ dst.reg_offset++;
+ src.reg_offset++;
+ emit(fs_inst(BRW_OPCODE_MUL, dst, src, scale_y));
+ }
+
/* Writemasking doesn't eliminate channels on SIMD8 texture
* samples, so don't worry about them.
*/
inst = emit_texture_gen5(ir, dst, coordinate);
}
- inst->sampler =
- _mesa_get_sampler_uniform_value(ir->sampler,
- ctx->Shader.CurrentProgram,
- &brw->fragment_program->Base);
- inst->sampler = c->fp->program.Base.SamplerUnits[inst->sampler];
+ inst->sampler = sampler;
this->result = dst;
if (ir->shadow_comparitor)
inst->shadow_compare = true;
+
+ if (c->key.tex_swizzles[inst->sampler] != SWIZZLE_NOOP) {
+ fs_reg swizzle_dst = fs_reg(this, glsl_type::vec4_type);
+
+ for (int i = 0; i < 4; i++) {
+ int swiz = GET_SWZ(c->key.tex_swizzles[inst->sampler], i);
+ fs_reg l = swizzle_dst;
+ l.reg_offset += i;
+
+ if (swiz == SWIZZLE_ZERO) {
+ emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(0.0f)));
+ } else if (swiz == SWIZZLE_ONE) {
+ emit(fs_inst(BRW_OPCODE_MOV, l, fs_reg(1.0f)));
+ } else {
+ fs_reg r = dst;
+ r.reg_offset += GET_SWZ(c->key.tex_swizzles[inst->sampler], i);
+ emit(fs_inst(BRW_OPCODE_MOV, l, r));
+ }
+ }
+ this->result = swizzle_dst;
+ }
}
void
ir->val->accept(this);
fs_reg val = this->result;
+ if (ir->type->vector_elements == 1) {
+ this->result.reg_offset += ir->mask.x;
+ return;
+ }
+
fs_reg result = fs_reg(this, ir->type);
this->result = result;
assert(ir->condition == NULL); /* FINISHME */
- emit(fs_inst(FS_OPCODE_DISCARD, temp, temp));
+ emit(fs_inst(FS_OPCODE_DISCARD_NOT, temp, reg_null));
+ emit(fs_inst(FS_OPCODE_DISCARD_AND, reg_null, temp));
+ kill_emitted = true;
}
void
write = emit(fs_inst(FS_OPCODE_FB_WRITE,
fs_reg(0),
fs_reg(0)));
+ write->base_mrf = 0;
}
/* The register location here is relative to the start of the URB
fs_reg(brw_imm_v(0x11001100))));
this->current_annotation = "compute pixel deltas from v0";
- this->delta_x = fs_reg(this, glsl_type::float_type);
- this->delta_y = fs_reg(this, glsl_type::float_type);
+ if (brw->has_pln) {
+ this->delta_x = fs_reg(this, glsl_type::vec2_type);
+ this->delta_y = this->delta_x;
+ this->delta_y.reg_offset++;
+ } else {
+ this->delta_x = fs_reg(this, glsl_type::float_type);
+ this->delta_y = fs_reg(this, glsl_type::float_type);
+ }
emit(fs_inst(BRW_OPCODE_ADD,
this->delta_x,
this->pixel_x,
interp_reg(FRAG_ATTRIB_WPOS, 3)));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = fs_reg(this, glsl_type::float_type);
- emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos_w));
+ emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
this->current_annotation = NULL;
}
/* If the pixel centers end up used, the setup is the same as for gen4. */
this->current_annotation = "compute pixel centers";
- this->pixel_x = fs_reg(this, glsl_type::uint_type);
- this->pixel_y = fs_reg(this, glsl_type::uint_type);
- this->pixel_x.type = BRW_REGISTER_TYPE_UW;
- this->pixel_y.type = BRW_REGISTER_TYPE_UW;
+ fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
+ fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
+ int_pixel_x.type = BRW_REGISTER_TYPE_UW;
+ int_pixel_y.type = BRW_REGISTER_TYPE_UW;
emit(fs_inst(BRW_OPCODE_ADD,
- this->pixel_x,
+ int_pixel_x,
fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
fs_reg(brw_imm_v(0x10101010))));
emit(fs_inst(BRW_OPCODE_ADD,
- this->pixel_y,
+ int_pixel_y,
fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
fs_reg(brw_imm_v(0x11001100))));
+ /* As of gen6, we can no longer mix float and int sources. We have
+ * to turn the integer pixel centers into floats for their actual
+ * use.
+ */
+ this->pixel_x = fs_reg(this, glsl_type::float_type);
+ this->pixel_y = fs_reg(this, glsl_type::float_type);
+ emit(fs_inst(BRW_OPCODE_MOV, this->pixel_x, int_pixel_x));
+ emit(fs_inst(BRW_OPCODE_MOV, this->pixel_y, int_pixel_y));
+
this->current_annotation = "compute 1/pos.w";
this->wpos_w = fs_reg(brw_vec8_grf(c->key.source_w_reg, 0));
this->pixel_w = fs_reg(this, glsl_type::float_type);
- emit(fs_inst(FS_OPCODE_RCP, this->pixel_w, wpos_w));
+ emit_math(FS_OPCODE_RCP, this->pixel_w, wpos_w);
this->delta_x = fs_reg(brw_vec8_grf(2, 0));
this->delta_y = fs_reg(brw_vec8_grf(3, 0));
fs_visitor::emit_fb_writes()
{
this->current_annotation = "FB write header";
+ GLboolean header_present = GL_TRUE;
int nr = 0;
- /* m0, m1 header */
- nr += 2;
+ if (intel->gen >= 6 &&
+ !this->kill_emitted &&
+ c->key.nr_color_regions == 1) {
+ header_present = false;
+ }
+
+ if (header_present) {
+ /* m0, m1 header */
+ nr += 2;
+ }
if (c->key.aa_dest_stencil_reg) {
emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, nr++),
fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
reg_undef, reg_undef));
inst->target = target;
+ inst->base_mrf = 0;
inst->mlen = nr;
if (target == c->key.nr_color_regions - 1)
inst->eot = true;
+ inst->header_present = header_present;
}
if (c->key.nr_color_regions == 0) {
fs_inst *inst = emit(fs_inst(FS_OPCODE_FB_WRITE,
reg_undef, reg_undef));
+ inst->base_mrf = 0;
inst->mlen = nr;
inst->eot = true;
+ inst->header_present = header_present;
}
this->current_annotation = NULL;
fs_visitor::generate_fb_write(fs_inst *inst)
{
GLboolean eot = inst->eot;
+ struct brw_reg implied_header;
/* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
* move, here's g1.
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
brw_set_compression_control(p, BRW_COMPRESSION_NONE);
- brw_MOV(p,
- brw_message_reg(1),
- brw_vec8_grf(1, 0));
+
+ if (inst->header_present) {
+ if (intel->gen >= 6) {
+ brw_MOV(p,
+ brw_message_reg(inst->base_mrf),
+ brw_vec8_grf(0, 0));
+ implied_header = brw_null_reg();
+ } else {
+ implied_header = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
+ }
+
+ brw_MOV(p,
+ brw_message_reg(inst->base_mrf + 1),
+ brw_vec8_grf(1, 0));
+ } else {
+ implied_header = brw_null_reg();
+ }
+
brw_pop_insn_state(p);
brw_fb_WRITE(p,
8, /* dispatch_width */
retype(vec8(brw_null_reg()), BRW_REGISTER_TYPE_UW),
- 0, /* base MRF */
- retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
+ inst->base_mrf,
+ implied_header,
inst->target,
inst->mlen,
0,
break;
}
- if (inst->opcode == FS_OPCODE_POW) {
- brw_MOV(p, brw_message_reg(3), src[1]);
- }
+ if (intel->gen >= 6) {
+ assert(inst->mlen == 0);
- brw_math(p, dst,
- op,
- inst->saturate ? BRW_MATH_SATURATE_SATURATE :
- BRW_MATH_SATURATE_NONE,
- 2, src[0],
- BRW_MATH_DATA_VECTOR,
- BRW_MATH_PRECISION_FULL);
+ if (inst->opcode == FS_OPCODE_POW) {
+ brw_math2(p, dst, op, src[0], src[1]);
+ } else {
+ brw_math(p, dst,
+ op,
+ inst->saturate ? BRW_MATH_SATURATE_SATURATE :
+ BRW_MATH_SATURATE_NONE,
+ 0, src[0],
+ BRW_MATH_DATA_VECTOR,
+ BRW_MATH_PRECISION_FULL);
+ }
+ } else {
+ assert(inst->mlen >= 1);
+
+ brw_math(p, dst,
+ op,
+ inst->saturate ? BRW_MATH_SATURATE_SATURATE :
+ BRW_MATH_SATURATE_NONE,
+ inst->base_mrf, src[0],
+ BRW_MATH_DATA_VECTOR,
+ BRW_MATH_PRECISION_FULL);
+ }
}
void
-fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src)
+fs_visitor::generate_tex(fs_inst *inst, struct brw_reg dst)
{
int msg_type = -1;
int rlen = 4;
uint32_t simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
- if (intel->gen == 5) {
+ if (intel->gen >= 5) {
switch (inst->opcode) {
case FS_OPCODE_TEX:
if (inst->shadow_compare) {
dst = vec16(dst);
}
- /* g0 header. */
- src.nr--;
-
brw_SAMPLE(p,
retype(dst, BRW_REGISTER_TYPE_UW),
- src.nr,
+ inst->base_mrf,
retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW),
SURF_INDEX_TEXTURE(inst->sampler),
inst->sampler,
WRITEMASK_XYZW,
msg_type,
rlen,
- inst->mlen + 1,
+ inst->mlen,
0,
1,
simd_mode);
}
void
-fs_visitor::generate_discard(fs_inst *inst, struct brw_reg temp)
+fs_visitor::generate_discard_not(fs_inst *inst, struct brw_reg mask)
+{
+ brw_push_insn_state(p);
+ brw_set_mask_control(p, BRW_MASK_DISABLE);
+ brw_NOT(p, mask, brw_mask_reg(1)); /* IMASK */
+ brw_pop_insn_state(p);
+}
+
+void
+fs_visitor::generate_discard_and(fs_inst *inst, struct brw_reg mask)
{
struct brw_reg g0 = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
- temp = brw_uw1_reg(temp.file, temp.nr, 0);
+ mask = brw_uw1_reg(mask.file, mask.nr, 0);
brw_push_insn_state(p);
brw_set_mask_control(p, BRW_MASK_DISABLE);
- brw_NOT(p, temp, brw_mask_reg(1)); /* IMASK */
- brw_AND(p, g0, temp, g0);
+ brw_AND(p, g0, mask, g0);
brw_pop_insn_state(p);
}
c->prog_data.first_curbe_grf = c->key.nr_payload_regs;
c->prog_data.curb_read_length = ALIGN(c->prog_data.nr_params, 8) / 8;
- if (intel->gen == 5 && (c->prog_data.first_curbe_grf +
- c->prog_data.curb_read_length) & 1) {
- /* Align the start of the interpolation coefficients so that we can use
- * the PLN instruction.
- */
- c->prog_data.first_curbe_grf++;
- }
-
/* Map the offsets in the UNIFORM file to fixed HW regs. */
foreach_iter(exec_list_iterator, iter, this->instructions) {
fs_inst *inst = (fs_inst *)iter.get();
/* Figure out where each of the incoming setup attributes lands. */
if (intel->gen >= 6) {
for (unsigned int i = 0; i < FRAG_ATTRIB_MAX; i++) {
- if (i == FRAG_ATTRIB_WPOS ||
- (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i))) {
+ if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(i)) {
urb_setup[i] = urb_next++;
}
}
int base_reg_count = BRW_MAX_GRF - this->first_non_payload_grf;
int class_sizes[base_reg_count];
int class_count = 0;
-
- calculate_live_intervals();
+ int aligned_pair_class = -1;
/* Set up the register classes.
*
* time.
*/
class_sizes[class_count++] = 1;
+ if (brw->has_pln && intel->gen < 6) {
+ /* Always set up the (unaligned) pairs for gen5, so we can find
+ * them for making the aligned pair class.
+ */
+ class_sizes[class_count++] = 2;
+ }
for (int r = 1; r < this->virtual_grf_next; r++) {
int i;
break;
}
if (i == class_count) {
+ if (this->virtual_grf_sizes[r] >= base_reg_count) {
+ fprintf(stderr, "Object too large to register allocate.\n");
+ this->fail = true;
+ }
+
class_sizes[class_count++] = this->virtual_grf_sizes[r];
}
}
int ra_reg_count = 0;
int class_base_reg[class_count];
int class_reg_count[class_count];
- int classes[class_count];
+ int classes[class_count + 1];
for (int i = 0; i < class_count; i++) {
class_base_reg[i] = ra_reg_count;
* that alias base regs, or the base regs themselves for classes[0].
*/
for (int c = 0; c <= i; c++) {
- for (int i_r = 0; i_r < class_reg_count[i] - 1; i_r++) {
+ for (int i_r = 0; i_r < class_reg_count[i]; i_r++) {
for (int c_r = MAX2(0, i_r - (class_sizes[c] - 1));
- c_r <= MIN2(class_reg_count[c] - 1, i_r + class_sizes[i] - 1);
+ c_r < MIN2(class_reg_count[c], i_r + class_sizes[i]);
c_r++) {
if (0) {
printf("%d/%d conflicts %d/%d\n",
- class_sizes[i], i_r,
- class_sizes[c], c_r);
+ class_sizes[i], this->first_non_payload_grf + i_r,
+ class_sizes[c], this->first_non_payload_grf + c_r);
}
ra_add_reg_conflict(regs,
}
}
+ /* Add a special class for aligned pairs, which we'll put delta_x/y
+ * in on gen5 so that we can do PLN.
+ */
+ if (brw->has_pln && intel->gen < 6) {
+ int reg_count = (base_reg_count - 1) / 2;
+ int unaligned_pair_class = 1;
+ assert(class_sizes[unaligned_pair_class] == 2);
+
+ aligned_pair_class = class_count;
+ classes[aligned_pair_class] = ra_alloc_reg_class(regs);
+ class_base_reg[aligned_pair_class] = 0;
+ class_reg_count[aligned_pair_class] = 0;
+ int start = (this->first_non_payload_grf & 1) ? 1 : 0;
+
+ for (int i = 0; i < reg_count; i++) {
+ ra_class_add_reg(regs, classes[aligned_pair_class],
+ class_base_reg[unaligned_pair_class] + i * 2 + start);
+ }
+ class_count++;
+ }
+
ra_set_finalize(regs);
struct ra_graph *g = ra_alloc_interference_graph(regs,
for (int i = 1; i < this->virtual_grf_next; i++) {
for (int c = 0; c < class_count; c++) {
if (class_sizes[c] == this->virtual_grf_sizes[i]) {
- ra_set_node_class(g, i, classes[c]);
+ if (aligned_pair_class >= 0 &&
+ this->delta_x.reg == i) {
+ ra_set_node_class(g, i, classes[aligned_pair_class]);
+ } else {
+ ra_set_node_class(g, i, classes[c]);
+ }
break;
}
}
for (int c = 0; c < class_count; c++) {
if (reg >= class_base_reg[c] &&
- reg < class_base_reg[c] + class_reg_count[c] - 1) {
+ reg < class_base_reg[c] + class_reg_count[c]) {
hw_reg = reg - class_base_reg[c];
break;
}
for (int i = 0; i < num_vars; i++) {
def[i] = 1 << 30;
- use[i] = 0;
+ use[i] = -1;
}
int ip = 0;
for (unsigned int i = 0; i < 3; i++) {
if (inst->src[i].file == GRF && inst->src[i].reg != 0) {
- def[inst->src[i].reg] = MIN2(def[inst->src[i].reg], eip);
use[inst->src[i].reg] = MAX2(use[inst->src[i].reg], eip);
}
}
if (inst->dst.file == GRF && inst->dst.reg != 0) {
def[inst->dst.reg] = MIN2(def[inst->dst.reg], eip);
- use[inst->dst.reg] = MAX2(use[inst->dst.reg], eip);
}
}
ip++;
}
+ talloc_free(this->virtual_grf_def);
+ talloc_free(this->virtual_grf_use);
this->virtual_grf_def = def;
this->virtual_grf_use = use;
}
+/**
+ * Attempts to move immediate constants into the immediate
+ * constant slot of following instructions.
+ *
+ * Immediate constants are a bit tricky -- they have to be in the last
+ * operand slot, you can't do abs/negate on them,
+ */
+
+bool
+fs_visitor::propagate_constants()
+{
+ bool progress = false;
+
+ foreach_iter(exec_list_iterator, iter, this->instructions) {
+ fs_inst *inst = (fs_inst *)iter.get();
+
+ if (inst->opcode != BRW_OPCODE_MOV ||
+ inst->predicated ||
+ inst->dst.file != GRF || inst->src[0].file != IMM ||
+ inst->dst.type != inst->src[0].type)
+ continue;
+
+ /* Don't bother with cases where we should have had the
+ * operation on the constant folded in GLSL already.
+ */
+ if (inst->saturate)
+ continue;
+
+ /* Found a move of a constant to a GRF. Find anything else using the GRF
+ * before it's written, and replace it with the constant if we can.
+ */
+ exec_list_iterator scan_iter = iter;
+ scan_iter.next();
+ for (; scan_iter.has_next(); scan_iter.next()) {
+ fs_inst *scan_inst = (fs_inst *)scan_iter.get();
+
+ if (scan_inst->opcode == BRW_OPCODE_DO ||
+ scan_inst->opcode == BRW_OPCODE_WHILE ||
+ scan_inst->opcode == BRW_OPCODE_ELSE ||
+ scan_inst->opcode == BRW_OPCODE_ENDIF) {
+ break;
+ }
+
+ for (int i = 2; i >= 0; i--) {
+ if (scan_inst->src[i].file != GRF ||
+ scan_inst->src[i].reg != inst->dst.reg ||
+ scan_inst->src[i].reg_offset != inst->dst.reg_offset)
+ continue;
+
+ /* Don't bother with cases where we should have had the
+ * operation on the constant folded in GLSL already.
+ */
+ if (scan_inst->src[i].negate || scan_inst->src[i].abs)
+ continue;
+
+ switch (scan_inst->opcode) {
+ case BRW_OPCODE_MOV:
+ scan_inst->src[i] = inst->src[0];
+ progress = true;
+ break;
+
+ case BRW_OPCODE_MUL:
+ case BRW_OPCODE_ADD:
+ if (i == 1) {
+ scan_inst->src[i] = inst->src[0];
+ progress = true;
+ } else if (i == 0 && scan_inst->src[1].file != IMM) {
+ /* Fit this constant in by commuting the operands */
+ scan_inst->src[0] = scan_inst->src[1];
+ scan_inst->src[1] = inst->src[0];
+ }
+ break;
+ case BRW_OPCODE_CMP:
+ if (i == 1) {
+ scan_inst->src[i] = inst->src[0];
+ progress = true;
+ }
+ }
+ }
+
+ if (scan_inst->dst.file == GRF &&
+ scan_inst->dst.reg == inst->dst.reg &&
+ (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
+ scan_inst->opcode == FS_OPCODE_TEX)) {
+ break;
+ }
+ }
+ }
+
+ return progress;
+}
+/**
+ * Must be called after calculate_live_intervales() to remove unused
+ * writes to registers -- register allocation will fail otherwise
+ * because something deffed but not used won't be considered to
+ * interfere with other regs.
+ */
+bool
+fs_visitor::dead_code_eliminate()
+{
+ bool progress = false;
+ int num_vars = this->virtual_grf_next;
+ bool dead[num_vars];
+
+ for (int i = 0; i < num_vars; i++) {
+ dead[i] = this->virtual_grf_def[i] >= this->virtual_grf_use[i];
+
+ if (dead[i]) {
+ /* Mark off its interval so it won't interfere with anything. */
+ this->virtual_grf_def[i] = -1;
+ this->virtual_grf_use[i] = -1;
+ }
+ }
+
+ foreach_iter(exec_list_iterator, iter, this->instructions) {
+ fs_inst *inst = (fs_inst *)iter.get();
+
+ if (inst->dst.file == GRF && dead[inst->dst.reg]) {
+ inst->remove();
+ progress = true;
+ }
+ }
+
+ return progress;
+}
+
+bool
+fs_visitor::register_coalesce()
+{
+ bool progress = false;
+
+ foreach_iter(exec_list_iterator, iter, this->instructions) {
+ fs_inst *inst = (fs_inst *)iter.get();
+
+ if (inst->opcode != BRW_OPCODE_MOV ||
+ inst->predicated ||
+ inst->saturate ||
+ inst->dst.file != GRF || inst->src[0].file != GRF ||
+ inst->dst.type != inst->src[0].type)
+ continue;
+
+ /* Found a move of a GRF to a GRF. Let's see if we can coalesce
+ * them: check for no writes to either one until the exit of the
+ * program.
+ */
+ bool interfered = false;
+ exec_list_iterator scan_iter = iter;
+ scan_iter.next();
+ for (; scan_iter.has_next(); scan_iter.next()) {
+ fs_inst *scan_inst = (fs_inst *)scan_iter.get();
+
+ if (scan_inst->opcode == BRW_OPCODE_DO ||
+ scan_inst->opcode == BRW_OPCODE_WHILE ||
+ scan_inst->opcode == BRW_OPCODE_ENDIF) {
+ interfered = true;
+ iter = scan_iter;
+ break;
+ }
+
+ if (scan_inst->dst.file == GRF) {
+ if (scan_inst->dst.reg == inst->dst.reg &&
+ (scan_inst->dst.reg_offset == inst->dst.reg_offset ||
+ scan_inst->opcode == FS_OPCODE_TEX)) {
+ interfered = true;
+ break;
+ }
+ if (scan_inst->dst.reg == inst->src[0].reg &&
+ (scan_inst->dst.reg_offset == inst->src[0].reg_offset ||
+ scan_inst->opcode == FS_OPCODE_TEX)) {
+ interfered = true;
+ break;
+ }
+ }
+ }
+ if (interfered) {
+ continue;
+ }
+
+ /* Rewrite the later usage to point at the source of the move to
+ * be removed.
+ */
+ for (exec_list_iterator scan_iter = iter; scan_iter.has_next();
+ scan_iter.next()) {
+ fs_inst *scan_inst = (fs_inst *)scan_iter.get();
+
+ for (int i = 0; i < 3; i++) {
+ if (scan_inst->src[i].file == GRF &&
+ scan_inst->src[i].reg == inst->dst.reg &&
+ scan_inst->src[i].reg_offset == inst->dst.reg_offset) {
+ scan_inst->src[i].reg = inst->src[0].reg;
+ scan_inst->src[i].reg_offset = inst->src[0].reg_offset;
+ scan_inst->src[i].abs |= inst->src[0].abs;
+ scan_inst->src[i].negate ^= inst->src[0].negate;
+ }
+ }
+ }
+
+ inst->remove();
+ progress = true;
+ }
+
+ return progress;
+}
+
+
+bool
+fs_visitor::compute_to_mrf()
+{
+ bool progress = false;
+ int next_ip = 0;
+
+ foreach_iter(exec_list_iterator, iter, this->instructions) {
+ fs_inst *inst = (fs_inst *)iter.get();
+
+ int ip = next_ip;
+ next_ip++;
+
+ if (inst->opcode != BRW_OPCODE_MOV ||
+ inst->predicated ||
+ inst->dst.file != MRF || inst->src[0].file != GRF ||
+ inst->dst.type != inst->src[0].type ||
+ inst->src[0].abs || inst->src[0].negate)
+ continue;
+
+ /* Can't compute-to-MRF this GRF if someone else was going to
+ * read it later.
+ */
+ if (this->virtual_grf_use[inst->src[0].reg] > ip)
+ continue;
+
+ /* Found a move of a GRF to a MRF. Let's see if we can go
+ * rewrite the thing that made this GRF to write into the MRF.
+ */
+ bool found = false;
+ fs_inst *scan_inst;
+ for (scan_inst = (fs_inst *)inst->prev;
+ scan_inst->prev != NULL;
+ scan_inst = (fs_inst *)scan_inst->prev) {
+ /* We don't handle flow control here. Most computation of
+ * values that end up in MRFs are shortly before the MRF
+ * write anyway.
+ */
+ if (scan_inst->opcode == BRW_OPCODE_DO ||
+ scan_inst->opcode == BRW_OPCODE_WHILE ||
+ scan_inst->opcode == BRW_OPCODE_ENDIF) {
+ break;
+ }
+
+ /* You can't read from an MRF, so if someone else reads our
+ * MRF's source GRF that we wanted to rewrite, that stops us.
+ */
+ bool interfered = false;
+ for (int i = 0; i < 3; i++) {
+ if (scan_inst->src[i].file == GRF &&
+ scan_inst->src[i].reg == inst->src[0].reg &&
+ scan_inst->src[i].reg_offset == inst->src[0].reg_offset) {
+ interfered = true;
+ }
+ }
+ if (interfered)
+ break;
+
+ if (scan_inst->dst.file == MRF &&
+ scan_inst->dst.hw_reg == inst->dst.hw_reg) {
+ /* Somebody else wrote our MRF here, so we can't can't
+ * compute-to-MRF before that.
+ */
+ break;
+ }
+
+ if (scan_inst->mlen > 0) {
+ /* Found a SEND instruction, which will do some amount of
+ * implied write that may overwrite our MRF that we were
+ * hoping to compute-to-MRF somewhere above it. Nothing
+ * we have implied-writes more than 2 MRFs from base_mrf,
+ * though.
+ */
+ int implied_write_len = MIN2(scan_inst->mlen, 2);
+ if (inst->dst.hw_reg >= scan_inst->base_mrf &&
+ inst->dst.hw_reg < scan_inst->base_mrf + implied_write_len) {
+ break;
+ }
+ }
+
+ if (scan_inst->dst.file == GRF &&
+ scan_inst->dst.reg == inst->src[0].reg) {
+ /* Found the last thing to write our reg we want to turn
+ * into a compute-to-MRF.
+ */
+
+ if (scan_inst->opcode == FS_OPCODE_TEX) {
+ /* texturing writes several continuous regs, so we can't
+ * compute-to-mrf that.
+ */
+ break;
+ }
+
+ /* If it's predicated, it (probably) didn't populate all
+ * the channels.
+ */
+ if (scan_inst->predicated)
+ break;
+
+ /* SEND instructions can't have MRF as a destination. */
+ if (scan_inst->mlen)
+ break;
+
+ if (intel->gen >= 6) {
+ /* gen6 math instructions must have the destination be
+ * GRF, so no compute-to-MRF for them.
+ */
+ if (scan_inst->opcode == FS_OPCODE_RCP ||
+ scan_inst->opcode == FS_OPCODE_RSQ ||
+ scan_inst->opcode == FS_OPCODE_SQRT ||
+ scan_inst->opcode == FS_OPCODE_EXP2 ||
+ scan_inst->opcode == FS_OPCODE_LOG2 ||
+ scan_inst->opcode == FS_OPCODE_SIN ||
+ scan_inst->opcode == FS_OPCODE_COS ||
+ scan_inst->opcode == FS_OPCODE_POW) {
+ break;
+ }
+ }
+
+ if (scan_inst->dst.reg_offset == inst->src[0].reg_offset) {
+ /* Found the creator of our MRF's source value. */
+ found = true;
+ break;
+ }
+ }
+ }
+ if (found) {
+ scan_inst->dst.file = MRF;
+ scan_inst->dst.hw_reg = inst->dst.hw_reg;
+ scan_inst->saturate |= inst->saturate;
+ inst->remove();
+ progress = true;
+ }
+ }
+
+ return progress;
+}
+
bool
fs_visitor::virtual_grf_interferes(int a, int b)
{
int start = MAX2(this->virtual_grf_def[a], this->virtual_grf_def[b]);
int end = MIN2(this->virtual_grf_use[a], this->virtual_grf_use[b]);
- return start <= end;
+ /* For dead code, just check if the def interferes with the other range. */
+ if (this->virtual_grf_use[a] == -1) {
+ return (this->virtual_grf_def[a] >= this->virtual_grf_def[b] &&
+ this->virtual_grf_def[a] < this->virtual_grf_use[b]);
+ }
+ if (this->virtual_grf_use[b] == -1) {
+ return (this->virtual_grf_def[b] >= this->virtual_grf_def[a] &&
+ this->virtual_grf_def[b] < this->virtual_grf_use[a]);
+ }
+
+ return start < end;
}
static struct brw_reg brw_reg_from_fs_reg(fs_reg *reg)
case BRW_OPCODE_XOR:
brw_XOR(p, dst, src[0], src[1]);
break;
+ case BRW_OPCODE_NOT:
+ brw_NOT(p, dst, src[0]);
+ break;
+ case BRW_OPCODE_ASR:
+ brw_ASR(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_SHR:
+ brw_SHR(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_SHL:
+ brw_SHL(p, dst, src[0], src[1]);
+ break;
case BRW_OPCODE_CMP:
brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
case FS_OPCODE_TEX:
case FS_OPCODE_TXB:
case FS_OPCODE_TXL:
- generate_tex(inst, dst, src[0]);
+ generate_tex(inst, dst);
+ break;
+ case FS_OPCODE_DISCARD_NOT:
+ generate_discard_not(inst, dst);
break;
- case FS_OPCODE_DISCARD:
- generate_discard(inst, dst /* src0 == dst */);
+ case FS_OPCODE_DISCARD_AND:
+ generate_discard_and(inst, src[0]);
break;
case FS_OPCODE_DDX:
generate_ddx(inst, dst, src[0]);
{
struct brw_compile *p = &c->func;
struct intel_context *intel = &brw->intel;
- GLcontext *ctx = &intel->ctx;
+ struct gl_context *ctx = &intel->ctx;
struct brw_shader *shader = NULL;
struct gl_shader_program *prog = ctx->Shader.CurrentProgram;
v.emit_fb_writes();
v.assign_curb_setup();
v.assign_urb_setup();
+
+ bool progress;
+ do {
+ progress = false;
+
+ v.calculate_live_intervals();
+ progress = v.propagate_constants() || progress;
+ progress = v.register_coalesce() || progress;
+ progress = v.compute_to_mrf() || progress;
+ progress = v.dead_code_eliminate() || progress;
+ } while (progress);
+
if (0)
v.assign_regs_trivial();
else
v.assign_regs();
}
- v.generate_code();
+ if (!v.fail)
+ v.generate_code();
assert(!v.fail); /* FINISHME: Cleanly fail, tested at link time, etc. */
projects / mesa.git / blobdiff