#include <sys/types.h>
+#include "main/hash_table.h"
#include "main/macros.h"
#include "main/shaderobj.h"
-#include "main/uniforms.h"
#include "main/fbobject.h"
#include "program/prog_parameter.h"
#include "program/prog_print.h"
#include "brw_wm.h"
}
#include "brw_fs.h"
+#include "main/uniforms.h"
+#include "brw_fs_live_variables.h"
#include "glsl/glsl_types.h"
-#include "glsl/ir_print_visitor.h"
void
fs_inst::init()
this->src[0] = reg_undef;
this->src[1] = reg_undef;
this->src[2] = reg_undef;
+
+ /* This will be the case for almost all instructions. */
+ this->regs_written = 1;
}
fs_inst::fs_inst()
ALU2(SHR)
ALU2(ASR)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
+ALU3(MAD)
+ALU2(ADDC)
+ALU2(SUBB)
/** Gen4 predicated IF. */
fs_inst *
fs_inst *
fs_visitor::IF(fs_reg src0, fs_reg src1, uint32_t condition)
{
- assert(intel->gen >= 6);
+ assert(brw->gen >= 6);
fs_inst *inst = new(mem_ctx) fs_inst(BRW_OPCODE_IF,
reg_null_d, src0, src1);
inst->conditional_mod = condition;
* mostly work out for float-interpreted-as-int since our comparisons are
* for >0, =0, <0.
*/
- if (intel->gen == 4) {
+ if (brw->gen == 4) {
dst.type = src0.type;
- if (dst.file == FIXED_HW_REG)
+ if (dst.file == HW_REG)
dst.fixed_hw_reg.type = dst.type;
}
exec_list instructions;
fs_inst *inst;
- fs_reg offset = fs_reg(this, glsl_type::uint_type);
- instructions.push_tail(ADD(offset, varying_offset, fs_reg(const_offset)));
-
- if (intel->gen >= 7) {
- inst = new(mem_ctx) fs_inst(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7,
- dst, surf_index, offset);
- instructions.push_tail(inst);
- } else {
- int base_mrf = 13;
- bool header_present = true;
-
- fs_reg mrf = fs_reg(MRF, base_mrf + header_present);
- mrf.type = BRW_REGISTER_TYPE_D;
-
- /* On gen6+ we want the dword offset passed in, but on gen4/5 we need a
- * dword-aligned byte offset.
+ /* We have our constant surface use a pitch of 4 bytes, so our index can
+ * be any component of a vector, and then we load 4 contiguous
+ * components starting from that.
+ *
+ * We break down the const_offset to a portion added to the variable
+ * offset and a portion done using reg_offset, which means that if you
+ * have GLSL using something like "uniform vec4 a[20]; gl_FragColor =
+ * a[i]", we'll temporarily generate 4 vec4 loads from offset i * 4, and
+ * CSE can later notice that those loads are all the same and eliminate
+ * the redundant ones.
+ */
+ fs_reg vec4_offset = fs_reg(this, glsl_type::int_type);
+ instructions.push_tail(ADD(vec4_offset,
+ varying_offset, const_offset & ~3));
+
+ int scale = 1;
+ if (brw->gen == 4 && dispatch_width == 8) {
+ /* Pre-gen5, we can either use a SIMD8 message that requires (header,
+ * u, v, r) as parameters, or we can just use the SIMD16 message
+ * consisting of (header, u). We choose the second, at the cost of a
+ * longer return length.
*/
- if (intel->gen == 6) {
- instructions.push_tail(MOV(mrf, offset));
- } else {
- instructions.push_tail(MUL(mrf, offset, fs_reg(4)));
- }
- inst = new(mem_ctx) fs_inst(FS_OPCODE_VARYING_PULL_CONSTANT_LOAD,
- dst, surf_index);
- inst->header_present = header_present;
- inst->base_mrf = base_mrf;
- inst->mlen = header_present + dispatch_width / 8;
+ scale = 2;
+ }
- instructions.push_tail(inst);
+ enum opcode op;
+ if (brw->gen >= 7)
+ op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7;
+ else
+ op = FS_OPCODE_VARYING_PULL_CONSTANT_LOAD;
+ fs_reg vec4_result = fs_reg(GRF, virtual_grf_alloc(4 * scale), dst.type);
+ inst = new(mem_ctx) fs_inst(op, vec4_result, surf_index, vec4_offset);
+ inst->regs_written = 4 * scale;
+ instructions.push_tail(inst);
+
+ if (brw->gen < 7) {
+ inst->base_mrf = 13;
+ inst->header_present = true;
+ if (brw->gen == 4)
+ inst->mlen = 3;
+ else
+ inst->mlen = 1 + dispatch_width / 8;
}
+ vec4_result.reg_offset += (const_offset & 3) * scale;
+ instructions.push_tail(MOV(dst, vec4_result));
+
return instructions;
}
offset == inst->offset);
}
-int
-fs_inst::regs_written()
-{
- if (is_tex())
- return 4;
-
- /* The SINCOS and INT_DIV_QUOTIENT_AND_REMAINDER math functions return 2,
- * but we don't currently use them...nor do we have an opcode for them.
- */
-
- return 1;
-}
-
bool
fs_inst::overwrites_reg(const fs_reg ®)
{
return (reg.file == dst.file &&
reg.reg == dst.reg &&
reg.reg_offset >= dst.reg_offset &&
- reg.reg_offset < dst.reg_offset + regs_written());
-}
-
-bool
-fs_inst::is_tex()
-{
- return (opcode == SHADER_OPCODE_TEX ||
- opcode == FS_OPCODE_TXB ||
- opcode == SHADER_OPCODE_TXD ||
- opcode == SHADER_OPCODE_TXF ||
- opcode == SHADER_OPCODE_TXF_MS ||
- opcode == SHADER_OPCODE_TXL ||
- opcode == SHADER_OPCODE_TXS ||
- opcode == SHADER_OPCODE_LOD);
-}
-
-bool
-fs_inst::is_math()
-{
- return (opcode == SHADER_OPCODE_RCP ||
- opcode == SHADER_OPCODE_RSQ ||
- opcode == SHADER_OPCODE_SQRT ||
- opcode == SHADER_OPCODE_EXP2 ||
- opcode == SHADER_OPCODE_LOG2 ||
- opcode == SHADER_OPCODE_SIN ||
- opcode == SHADER_OPCODE_COS ||
- opcode == SHADER_OPCODE_INT_QUOTIENT ||
- opcode == SHADER_OPCODE_INT_REMAINDER ||
- opcode == SHADER_OPCODE_POW);
-}
-
-bool
-fs_inst::is_control_flow()
-{
- switch (opcode) {
- case BRW_OPCODE_DO:
- case BRW_OPCODE_WHILE:
- case BRW_OPCODE_IF:
- case BRW_OPCODE_ELSE:
- case BRW_OPCODE_ENDIF:
- case BRW_OPCODE_BREAK:
- case BRW_OPCODE_CONTINUE:
- return true;
- default:
- return false;
- }
+ reg.reg_offset < dst.reg_offset + regs_written);
}
bool
return (opcode == FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7 ||
opcode == SHADER_OPCODE_SHADER_TIME_ADD ||
(opcode == FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD &&
- src[1].file == GRF));
+ src[1].file == GRF) ||
+ (is_tex() && src[0].file == GRF));
}
bool
fs_visitor::can_do_source_mods(fs_inst *inst)
{
- if (intel->gen == 6 && inst->is_math())
+ if (brw->gen == 6 && inst->is_math())
return false;
if (inst->is_send_from_grf())
return false;
+ if (!inst->can_do_source_mods())
+ return false;
+
return true;
}
fs_reg::fs_reg(struct brw_reg fixed_hw_reg)
{
init();
- this->file = FIXED_HW_REG;
+ this->file = HW_REG;
this->fixed_hw_reg = fixed_hw_reg;
this->type = fixed_hw_reg.type;
}
imm.u == r.imm.u);
}
+fs_reg
+fs_reg::retype(uint32_t type)
+{
+ fs_reg result = *this;
+ result.type = type;
+ return result;
+}
+
bool
fs_reg::is_zero() const
{
return type == BRW_REGISTER_TYPE_F ? imm.f == 1.0 : imm.i == 1;
}
+bool
+fs_reg::is_null() const
+{
+ return file == HW_REG &&
+ fixed_hw_reg.file == BRW_ARCHITECTURE_REGISTER_FILE &&
+ fixed_hw_reg.nr == BRW_ARF_NULL;
+}
+
+bool
+fs_reg::is_valid_3src() const
+{
+ return file == GRF || file == UNIFORM;
+}
+
int
fs_visitor::type_size(const struct glsl_type *type)
{
* link time.
*/
return 0;
+ case GLSL_TYPE_ATOMIC_UINT:
+ return 0;
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
fs_reg
fs_visitor::get_timestamp()
{
- assert(intel->gen >= 7);
+ assert(brw->gen >= 7);
fs_reg ts = fs_reg(retype(brw_vec1_reg(BRW_ARCHITECTURE_REGISTER_FILE,
BRW_ARF_TIMESTAMP,
fs_visitor::emit_shader_time_write(enum shader_time_shader_type type,
fs_reg value)
{
- int shader_time_index = brw_get_shader_time_index(brw, prog, &fp->Base,
- type);
+ int shader_time_index =
+ brw_get_shader_time_index(brw, shader_prog, &fp->Base, type);
fs_reg offset = fs_reg(shader_time_index * SHADER_TIME_STRIDE);
fs_reg payload;
assert(force_sechalf_stack >= 0);
}
+/**
+ * Returns true if the instruction has a flag that means it won't
+ * update an entire destination register.
+ *
+ * For example, dead code elimination and live variable analysis want to know
+ * when a write to a variable screens off any preceding values that were in
+ * it.
+ */
+bool
+fs_inst::is_partial_write()
+{
+ return ((this->predicate && this->opcode != BRW_OPCODE_SEL) ||
+ this->force_uncompressed ||
+ this->force_sechalf);
+}
+
+int
+fs_inst::regs_read(fs_visitor *v, int arg)
+{
+ if (is_tex() && arg == 0 && src[0].file == GRF) {
+ if (v->dispatch_width == 16)
+ return (mlen + 1) / 2;
+ else
+ return mlen;
+ }
+ return 1;
+}
+
+bool
+fs_inst::reads_flag()
+{
+ return predicate;
+}
+
+bool
+fs_inst::writes_flag()
+{
+ return (conditional_mod && opcode != BRW_OPCODE_SEL) ||
+ opcode == FS_OPCODE_MOV_DISPATCH_TO_FLAGS;
+}
+
/**
* Returns how many MRFs an FS opcode will write over.
*
if (inst->mlen == 0)
return 0;
+ if (inst->base_mrf == -1)
+ return 0;
+
switch (inst->opcode) {
case SHADER_OPCODE_RCP:
case SHADER_OPCODE_RSQ:
case SHADER_OPCODE_TXD:
case SHADER_OPCODE_TXF:
case SHADER_OPCODE_TXF_MS:
+ case SHADER_OPCODE_TG4:
+ case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_TXL:
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_LOD:
case FS_OPCODE_FB_WRITE:
return 2;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
- case FS_OPCODE_UNSPILL:
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
return 1;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
- return inst->header_present;
- case FS_OPCODE_SPILL:
+ return inst->mlen;
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
return 2;
+ case SHADER_OPCODE_UNTYPED_ATOMIC:
+ case SHADER_OPCODE_UNTYPED_SURFACE_READ:
+ return 0;
default:
assert(!"not reached");
return inst->mlen;
import_uniforms_callback,
variable_ht);
this->params_remap = v->params_remap;
+ this->nr_params_remap = v->nr_params_remap;
}
/* Our support for uniforms is piggy-backed on the struct
* with our name, or the prefix of a component that starts with our name.
*/
unsigned params_before = c->prog_data.nr_params;
- for (unsigned u = 0; u < prog->NumUserUniformStorage; u++) {
- struct gl_uniform_storage *storage = &prog->UniformStorage[u];
+ for (unsigned u = 0; u < shader_prog->NumUserUniformStorage; u++) {
+ struct gl_uniform_storage *storage = &shader_prog->UniformStorage[u];
if (strncmp(ir->name, storage->name, namelen) != 0 ||
(storage->name[namelen] != 0 &&
/* Make sure we actually initialized the right amount of stuff here. */
assert(params_before + ir->type->component_slots() ==
c->prog_data.nr_params);
+ (void)params_before;
}
wpos.reg_offset++;
/* gl_FragCoord.z */
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
emit(MOV(wpos, fs_reg(brw_vec8_grf(c->source_depth_reg, 0))));
} else {
emit(FS_OPCODE_LINTERP, wpos,
bool is_centroid)
{
brw_wm_barycentric_interp_mode barycoord_mode;
- if (is_centroid) {
- if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
- barycoord_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
- else
- barycoord_mode = BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC;
+ if (brw->gen >= 6) {
+ if (is_centroid) {
+ if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
+ barycoord_mode = BRW_WM_PERSPECTIVE_CENTROID_BARYCENTRIC;
+ else
+ barycoord_mode = BRW_WM_NONPERSPECTIVE_CENTROID_BARYCENTRIC;
+ } else {
+ if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
+ barycoord_mode = BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
+ else
+ barycoord_mode = BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC;
+ }
} else {
- if (interpolation_mode == INTERP_QUALIFIER_SMOOTH)
- barycoord_mode = BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
- else
- barycoord_mode = BRW_WM_NONPERSPECTIVE_PIXEL_BARYCENTRIC;
+ /* On Ironlake and below, there is only one interpolation mode.
+ * Centroid interpolation doesn't mean anything on this hardware --
+ * there is no multisampling.
+ */
+ barycoord_mode = BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC;
}
return emit(FS_OPCODE_LINTERP, attr,
this->delta_x[barycoord_mode],
int location = ir->location;
for (unsigned int i = 0; i < array_elements; i++) {
for (unsigned int j = 0; j < type->matrix_columns; j++) {
- if (urb_setup[location] == -1) {
+ if (c->prog_data.urb_setup[location] == -1) {
/* If there's no incoming setup data for this slot, don't
* emit interpolation for it.
*/
* attribute, as well as making brw_vs_constval.c
* handle varyings other than gl_TexCoord.
*/
- if (location >= VARYING_SLOT_TEX0 &&
- location <= VARYING_SLOT_TEX7 &&
- k == 3 && !(c->key.proj_attrib_mask
- & BITFIELD64_BIT(location))) {
- emit(BRW_OPCODE_MOV, attr, fs_reg(1.0f));
- } else {
- struct brw_reg interp = interp_reg(location, k);
- emit_linterp(attr, fs_reg(interp), interpolation_mode,
- ir->centroid);
- if (brw->needs_unlit_centroid_workaround && ir->centroid) {
- /* Get the pixel/sample mask into f0 so that we know
- * which pixels are lit. Then, for each channel that is
- * unlit, replace the centroid data with non-centroid
- * data.
- */
- emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr);
- fs_inst *inst = emit_linterp(attr, fs_reg(interp),
- interpolation_mode, false);
- inst->predicate = BRW_PREDICATE_NORMAL;
- inst->predicate_inverse = true;
- }
- if (intel->gen < 6) {
- emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
- }
- }
+ struct brw_reg interp = interp_reg(location, k);
+ emit_linterp(attr, fs_reg(interp), interpolation_mode,
+ ir->centroid);
+ if (brw->needs_unlit_centroid_workaround && ir->centroid) {
+ /* Get the pixel/sample mask into f0 so that we know
+ * which pixels are lit. Then, for each channel that is
+ * unlit, replace the centroid data with non-centroid
+ * data.
+ */
+ emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
+ fs_inst *inst = emit_linterp(attr, fs_reg(interp),
+ interpolation_mode, false);
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ inst->predicate_inverse = true;
+ }
+ if (brw->gen < 6 && interpolation_mode == INTERP_QUALIFIER_SMOOTH) {
+ emit(BRW_OPCODE_MUL, attr, attr, this->pixel_w);
+ }
attr.reg_offset++;
}
fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
/* The frontfacing comes in as a bit in the thread payload. */
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
emit(BRW_OPCODE_ASR, *reg,
fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_D)),
fs_reg(15));
return reg;
}
+void
+fs_visitor::compute_sample_position(fs_reg dst, fs_reg int_sample_pos)
+{
+ assert(dst.type == BRW_REGISTER_TYPE_F);
+
+ if (c->key.compute_pos_offset) {
+ /* Convert int_sample_pos to floating point */
+ emit(MOV(dst, int_sample_pos));
+ /* Scale to the range [0, 1] */
+ emit(MUL(dst, dst, fs_reg(1 / 16.0f)));
+ }
+ else {
+ /* From ARB_sample_shading specification:
+ * "When rendering to a non-multisample buffer, or if multisample
+ * rasterization is disabled, gl_SamplePosition will always be
+ * (0.5, 0.5).
+ */
+ emit(MOV(dst, fs_reg(0.5f)));
+ }
+}
+
+fs_reg *
+fs_visitor::emit_samplepos_setup(ir_variable *ir)
+{
+ assert(brw->gen >= 6);
+ assert(ir->type == glsl_type::vec2_type);
+
+ this->current_annotation = "compute sample position";
+ fs_reg *reg = new(this->mem_ctx) fs_reg(this, ir->type);
+ fs_reg pos = *reg;
+ fs_reg int_sample_x = fs_reg(this, glsl_type::int_type);
+ fs_reg int_sample_y = fs_reg(this, glsl_type::int_type);
+
+ /* WM will be run in MSDISPMODE_PERSAMPLE. So, only one of SIMD8 or SIMD16
+ * mode will be enabled.
+ *
+ * From the Ivy Bridge PRM, volume 2 part 1, page 344:
+ * R31.1:0 Position Offset X/Y for Slot[3:0]
+ * R31.3:2 Position Offset X/Y for Slot[7:4]
+ * .....
+ *
+ * The X, Y sample positions come in as bytes in thread payload. So, read
+ * the positions using vstride=16, width=8, hstride=2.
+ */
+ struct brw_reg sample_pos_reg =
+ stride(retype(brw_vec1_grf(c->sample_pos_reg, 0),
+ BRW_REGISTER_TYPE_B), 16, 8, 2);
+
+ emit(MOV(int_sample_x, fs_reg(sample_pos_reg)));
+ if (dispatch_width == 16) {
+ int_sample_x.sechalf = true;
+ fs_inst *inst = emit(MOV(int_sample_x,
+ fs_reg(suboffset(sample_pos_reg, 16))));
+ inst->force_sechalf = true;
+ int_sample_x.sechalf = false;
+ }
+ /* Compute gl_SamplePosition.x */
+ compute_sample_position(pos, int_sample_x);
+ pos.reg_offset++;
+ emit(MOV(int_sample_y, fs_reg(suboffset(sample_pos_reg, 1))));
+ if (dispatch_width == 16) {
+ int_sample_y.sechalf = true;
+ fs_inst *inst = emit(MOV(int_sample_y,
+ fs_reg(suboffset(sample_pos_reg, 17))));
+ inst->force_sechalf = true;
+ int_sample_y.sechalf = false;
+ }
+ /* Compute gl_SamplePosition.y */
+ compute_sample_position(pos, int_sample_y);
+ return reg;
+}
+
fs_reg
fs_visitor::fix_math_operand(fs_reg src)
{
* The hardware ignores source modifiers (negate and abs) on math
* instructions, so we also move to a temp to set those up.
*/
- if (intel->gen == 6 && src.file != UNIFORM && src.file != IMM &&
+ if (brw->gen == 6 && src.file != UNIFORM && src.file != IMM &&
!src.abs && !src.negate)
return src;
/* Gen7 relaxes most of the above restrictions, but still can't use IMM
* operands to math
*/
- if (intel->gen >= 7 && src.file != IMM)
+ if (brw->gen >= 7 && src.file != IMM)
return src;
fs_reg expanded = fs_reg(this, glsl_type::float_type);
* Gen 6 hardware ignores source modifiers (negate and abs) on math
* instructions, so we also move to a temp to set those up.
*/
- if (intel->gen >= 6)
+ if (brw->gen >= 6)
src = fix_math_operand(src);
fs_inst *inst = emit(opcode, dst, src);
- if (intel->gen < 6) {
+ if (brw->gen < 6) {
inst->base_mrf = 2;
inst->mlen = dispatch_width / 8;
}
switch (opcode) {
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
- if (intel->gen >= 7 && dispatch_width == 16)
+ if (brw->gen >= 7 && dispatch_width == 16)
fail("16-wide INTDIV unsupported\n");
break;
case SHADER_OPCODE_POW:
return NULL;
}
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
src0 = fix_math_operand(src0);
src1 = fix_math_operand(src1);
constant_nr / 8,
constant_nr % 8);
- inst->src[i].file = FIXED_HW_REG;
+ inst->src[i].file = HW_REG;
inst->src[i].fixed_hw_reg = retype(brw_reg, inst->src[i].type);
}
}
fs_visitor::calculate_urb_setup()
{
for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
- urb_setup[i] = -1;
+ c->prog_data.urb_setup[i] = -1;
}
int urb_next = 0;
/* Figure out where each of the incoming setup attributes lands. */
- if (intel->gen >= 6) {
- for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
- if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
- urb_setup[i] = urb_next++;
- }
+ if (brw->gen >= 6) {
+ if (_mesa_bitcount_64(fp->Base.InputsRead &
+ BRW_FS_VARYING_INPUT_MASK) <= 16) {
+ /* The SF/SBE pipeline stage can do arbitrary rearrangement of the
+ * first 16 varying inputs, so we can put them wherever we want.
+ * Just put them in order.
+ *
+ * This is useful because it means that (a) inputs not used by the
+ * fragment shader won't take up valuable register space, and (b) we
+ * won't have to recompile the fragment shader if it gets paired with
+ * a different vertex (or geometry) shader.
+ */
+ for (unsigned int i = 0; i < VARYING_SLOT_MAX; i++) {
+ if (fp->Base.InputsRead & BRW_FS_VARYING_INPUT_MASK &
+ BITFIELD64_BIT(i)) {
+ c->prog_data.urb_setup[i] = urb_next++;
+ }
+ }
+ } else {
+ /* We have enough input varyings that the SF/SBE pipeline stage can't
+ * arbitrarily rearrange them to suit our whim; we have to put them
+ * in an order that matches the output of the previous pipeline stage
+ * (geometry or vertex shader).
+ */
+ struct brw_vue_map prev_stage_vue_map;
+ brw_compute_vue_map(brw, &prev_stage_vue_map,
+ c->key.input_slots_valid);
+ int first_slot = 2 * BRW_SF_URB_ENTRY_READ_OFFSET;
+ assert(prev_stage_vue_map.num_slots <= first_slot + 32);
+ for (int slot = first_slot; slot < prev_stage_vue_map.num_slots;
+ slot++) {
+ int varying = prev_stage_vue_map.slot_to_varying[slot];
+ /* Note that varying == BRW_VARYING_SLOT_COUNT when a slot is
+ * unused.
+ */
+ if (varying != BRW_VARYING_SLOT_COUNT &&
+ (fp->Base.InputsRead & BRW_FS_VARYING_INPUT_MASK &
+ BITFIELD64_BIT(varying))) {
+ c->prog_data.urb_setup[varying] = slot - first_slot;
+ }
+ }
+ urb_next = prev_stage_vue_map.num_slots - first_slot;
}
} else {
/* FINISHME: The sf doesn't map VS->FS inputs for us very well. */
* incremented, mapped or not.
*/
if (_mesa_varying_slot_in_fs((gl_varying_slot) i))
- urb_setup[i] = urb_next;
+ c->prog_data.urb_setup[i] = urb_next;
urb_next++;
}
}
* See compile_sf_prog() for more info.
*/
if (fp->Base.InputsRead & BITFIELD64_BIT(VARYING_SLOT_PNTC))
- urb_setup[VARYING_SLOT_PNTC] = urb_next++;
+ c->prog_data.urb_setup[VARYING_SLOT_PNTC] = urb_next++;
}
- /* Each attribute is 4 setup channels, each of which is half a reg. */
- c->prog_data.urb_read_length = urb_next * 2;
+ c->prog_data.num_varying_inputs = urb_next;
}
void
fs_inst *inst = (fs_inst *)node;
if (inst->opcode == FS_OPCODE_LINTERP) {
- assert(inst->src[2].file == FIXED_HW_REG);
+ assert(inst->src[2].file == HW_REG);
inst->src[2].fixed_hw_reg.nr += urb_start;
}
if (inst->opcode == FS_OPCODE_CINTERP) {
- assert(inst->src[0].file == FIXED_HW_REG);
+ assert(inst->src[0].file == HW_REG);
inst->src[0].fixed_hw_reg.nr += urb_start;
}
}
- this->first_non_payload_grf = urb_start + c->prog_data.urb_read_length;
+ /* Each attribute is 4 setup channels, each of which is half a reg. */
+ this->first_non_payload_grf =
+ urb_start + c->prog_data.num_varying_inputs * 2;
}
/**
/* If there's a SEND message that requires contiguous destination
* registers, no splitting is allowed.
*/
- if (inst->regs_written() > 1) {
+ if (inst->regs_written > 1) {
split_grf[inst->dst.reg] = false;
}
* the send is reading the whole thing.
*/
if (inst->is_send_from_grf()) {
- split_grf[inst->src[0].reg] = false;
+ for (int i = 0; i < 3; i++) {
+ if (inst->src[i].file == GRF) {
+ split_grf[inst->src[i].reg] = false;
+ }
+ }
}
}
}
}
}
- this->live_intervals_valid = false;
+ invalidate_live_intervals();
}
/**
if (remap_table[i] != -1) {
remap_table[i] = new_index;
virtual_grf_sizes[new_index] = virtual_grf_sizes[i];
- if (live_intervals_valid) {
- virtual_grf_use[new_index] = virtual_grf_use[i];
- virtual_grf_def[new_index] = virtual_grf_def[i];
- }
+ invalidate_live_intervals();
++new_index;
}
}
{
if (dispatch_width == 8) {
this->params_remap = ralloc_array(mem_ctx, int, c->prog_data.nr_params);
+ this->nr_params_remap = c->prog_data.nr_params;
for (unsigned int i = 0; i < c->prog_data.nr_params; i++)
this->params_remap[i] = -1;
if (inst->src[i].file != UNIFORM)
continue;
- assert(constant_nr < (int)c->prog_data.nr_params);
+ /* Section 5.11 of the OpenGL 4.3 spec says:
+ *
+ * "Out-of-bounds reads return undefined values, which include
+ * values from other variables of the active program or zero."
+ */
+ if (constant_nr < 0 || constant_nr >= (int)c->prog_data.nr_params) {
+ constant_nr = 0;
+ }
/* For now, set this to non-negative. We'll give it the
* actual new number in a moment, in order to keep the
if (inst->src[i].file != UNIFORM)
continue;
+ /* as above alias to 0 */
+ if (constant_nr < 0 || constant_nr >= (int)this->nr_params_remap) {
+ constant_nr = 0;
+ }
assert(this->params_remap[constant_nr] != -1);
inst->src[i].reg = this->params_remap[constant_nr];
inst->src[i].reg_offset = 0;
base_ir = inst->ir;
current_annotation = inst->annotation;
- fs_reg surf_index = fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER);
+ fs_reg surf_index = fs_reg(c->prog_data.base.binding_table.pull_constants_start);
fs_reg temp = fs_reg(this, glsl_type::float_type);
exec_list list = VARYING_PULL_CONSTANT_LOAD(temp,
surf_index,
assert(!inst->src[i].reladdr);
fs_reg dst = fs_reg(this, glsl_type::float_type);
- fs_reg index = fs_reg((unsigned)SURF_INDEX_FRAG_CONST_BUFFER);
+ fs_reg index = fs_reg(c->prog_data.base.binding_table.pull_constants_start);
fs_reg offset = fs_reg((unsigned)(pull_index * 4) & ~15);
fs_inst *pull =
new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
break;
}
break;
+ case BRW_OPCODE_OR:
+ if (inst->src[0].equals(inst->src[1])) {
+ inst->opcode = BRW_OPCODE_MOV;
+ inst->src[1] = reg_undef;
+ progress = true;
+ break;
+ }
+ break;
+ case BRW_OPCODE_SEL:
+ if (inst->saturate && inst->src[1].file == IMM) {
+ switch (inst->conditional_mod) {
+ case BRW_CONDITIONAL_LE:
+ case BRW_CONDITIONAL_L:
+ switch (inst->src[1].type) {
+ case BRW_REGISTER_TYPE_F:
+ if (inst->src[1].imm.f >= 1.0f) {
+ inst->opcode = BRW_OPCODE_MOV;
+ inst->src[1] = reg_undef;
+ progress = true;
+ }
+ break;
+ default:
+ break;
+ }
+ break;
+ case BRW_CONDITIONAL_GE:
+ case BRW_CONDITIONAL_G:
+ switch (inst->src[1].type) {
+ case BRW_REGISTER_TYPE_F:
+ if (inst->src[1].imm.f <= 0.0f) {
+ inst->opcode = BRW_OPCODE_MOV;
+ inst->src[1] = reg_undef;
+ inst->conditional_mod = BRW_CONDITIONAL_NONE;
+ progress = true;
+ }
+ break;
+ default:
+ break;
+ }
+ default:
+ break;
+ }
+ }
+ break;
default:
break;
}
}
/**
- * Must be called after calculate_live_intervales() to remove unused
- * writes to registers -- register allocation will fail otherwise
- * because something deffed but not used won't be considered to
- * interfere with other regs.
+ * Removes any instructions writing a VGRF where that VGRF is not used by any
+ * later instruction.
*/
bool
fs_visitor::dead_code_eliminate()
foreach_list_safe(node, &this->instructions) {
fs_inst *inst = (fs_inst *)node;
- if (inst->dst.file == GRF && this->virtual_grf_use[inst->dst.reg] <= pc) {
- inst->remove();
- progress = true;
+ if (inst->dst.file == GRF) {
+ bool dead = true;
+
+ for (int i = 0; i < inst->regs_written; i++) {
+ int var = live_intervals->var_from_vgrf[inst->dst.reg];
+ assert(live_intervals->end[var + inst->dst.reg_offset + i] >= pc);
+ if (live_intervals->end[var + inst->dst.reg_offset + i] != pc) {
+ dead = false;
+ break;
+ }
+ }
+
+ if (dead) {
+ /* Don't dead code eliminate instructions that write to the
+ * accumulator as a side-effect. Instead just set the destination
+ * to the null register to free it.
+ */
+ switch (inst->opcode) {
+ case BRW_OPCODE_ADDC:
+ case BRW_OPCODE_SUBB:
+ case BRW_OPCODE_MACH:
+ inst->dst = fs_reg(retype(brw_null_reg(), inst->dst.type));
+ break;
+ default:
+ inst->remove();
+ progress = true;
+ break;
+ }
+ }
}
pc++;
}
if (progress)
- live_intervals_valid = false;
+ invalidate_live_intervals();
+
+ return progress;
+}
+
+struct dead_code_hash_key
+{
+ int vgrf;
+ int reg_offset;
+};
+
+static bool
+dead_code_hash_compare(const void *a, const void *b)
+{
+ return memcmp(a, b, sizeof(struct dead_code_hash_key)) == 0;
+}
+
+static void
+clear_dead_code_hash(struct hash_table *ht)
+{
+ struct hash_entry *entry;
+
+ hash_table_foreach(ht, entry) {
+ _mesa_hash_table_remove(ht, entry);
+ }
+}
+
+static void
+insert_dead_code_hash(struct hash_table *ht,
+ int vgrf, int reg_offset, fs_inst *inst)
+{
+ /* We don't bother freeing keys, because they'll be GCed with the ht. */
+ struct dead_code_hash_key *key = ralloc(ht, struct dead_code_hash_key);
+
+ key->vgrf = vgrf;
+ key->reg_offset = reg_offset;
+
+ _mesa_hash_table_insert(ht, _mesa_hash_data(key, sizeof(*key)), key, inst);
+}
+
+static struct hash_entry *
+get_dead_code_hash_entry(struct hash_table *ht, int vgrf, int reg_offset)
+{
+ struct dead_code_hash_key key;
+
+ key.vgrf = vgrf;
+ key.reg_offset = reg_offset;
+
+ return _mesa_hash_table_search(ht, _mesa_hash_data(&key, sizeof(key)), &key);
+}
+
+static void
+remove_dead_code_hash(struct hash_table *ht,
+ int vgrf, int reg_offset)
+{
+ struct hash_entry *entry = get_dead_code_hash_entry(ht, vgrf, reg_offset);
+ if (!entry)
+ return;
+
+ _mesa_hash_table_remove(ht, entry);
+}
+
+/**
+ * Walks basic blocks, removing any regs that are written but not read before
+ * being redefined.
+ *
+ * The dead_code_eliminate() function implements a global dead code
+ * elimination, but it only handles the removing the last write to a register
+ * if it's never read. This one can handle intermediate writes, but only
+ * within a basic block.
+ */
+bool
+fs_visitor::dead_code_eliminate_local()
+{
+ struct hash_table *ht;
+ bool progress = false;
+
+ ht = _mesa_hash_table_create(mem_ctx, dead_code_hash_compare);
+
+ foreach_list_safe(node, &this->instructions) {
+ fs_inst *inst = (fs_inst *)node;
+
+ /* At a basic block, empty the HT since we don't understand dataflow
+ * here.
+ */
+ if (inst->is_control_flow()) {
+ clear_dead_code_hash(ht);
+ continue;
+ }
+
+ /* Clear the HT of any instructions that got read. */
+ for (int i = 0; i < 3; i++) {
+ fs_reg src = inst->src[i];
+ if (src.file != GRF)
+ continue;
+
+ int read = 1;
+ if (inst->is_send_from_grf())
+ read = virtual_grf_sizes[src.reg] - src.reg_offset;
+
+ for (int reg_offset = src.reg_offset;
+ reg_offset < src.reg_offset + read;
+ reg_offset++) {
+ remove_dead_code_hash(ht, src.reg, reg_offset);
+ }
+ }
+
+ /* Add any update of a GRF to the HT, removing a previous write if it
+ * wasn't read.
+ */
+ if (inst->dst.file == GRF) {
+ if (inst->regs_written > 1) {
+ /* We don't know how to trim channels from an instruction's
+ * writes, so we can't incrementally remove unread channels from
+ * it. Just remove whatever it overwrites from the table
+ */
+ for (int i = 0; i < inst->regs_written; i++) {
+ remove_dead_code_hash(ht,
+ inst->dst.reg,
+ inst->dst.reg_offset + i);
+ }
+ } else {
+ struct hash_entry *entry =
+ get_dead_code_hash_entry(ht, inst->dst.reg,
+ inst->dst.reg_offset);
+
+ if (inst->is_partial_write()) {
+ /* For a partial write, we can't remove any previous dead code
+ * candidate, since we're just modifying their result, but we can
+ * be dead code eliminiated ourselves.
+ */
+ if (entry) {
+ entry->data = inst;
+ } else {
+ insert_dead_code_hash(ht, inst->dst.reg, inst->dst.reg_offset,
+ inst);
+ }
+ } else {
+ if (entry) {
+ /* We're completely updating a channel, and there was a
+ * previous write to the channel that wasn't read. Kill it!
+ */
+ fs_inst *inst = (fs_inst *)entry->data;
+ inst->remove();
+ progress = true;
+ _mesa_hash_table_remove(ht, entry);
+ }
+
+ insert_dead_code_hash(ht, inst->dst.reg, inst->dst.reg_offset,
+ inst);
+ }
+ }
+ }
+ }
+
+ _mesa_hash_table_destroy(ht, NULL);
+
+ if (progress)
+ invalidate_live_intervals();
return progress;
}
fs_inst *inst = (fs_inst *)node;
if (inst->opcode != BRW_OPCODE_MOV ||
- inst->predicate ||
+ inst->is_partial_write() ||
inst->saturate ||
inst->src[0].file != GRF ||
inst->src[0].negate ||
inst->src[0].smear != -1 ||
inst->dst.file != GRF ||
inst->dst.type != inst->src[0].type ||
- virtual_grf_sizes[inst->src[0].reg] != 1 ||
- virtual_grf_interferes(inst->dst.reg, inst->src[0].reg)) {
+ virtual_grf_sizes[inst->src[0].reg] != 1) {
continue;
}
+ int var_from = live_intervals->var_from_reg(&inst->src[0]);
+ int var_to = live_intervals->var_from_reg(&inst->dst);
+
+ if (live_intervals->vars_interfere(var_from, var_to))
+ continue;
+
int reg_from = inst->src[0].reg;
assert(inst->src[0].reg_offset == 0);
int reg_to = inst->dst.reg;
}
inst->remove();
-
- /* We don't need to recalculate live intervals inside the loop despite
- * flagging live_intervals_valid because we only use live intervals for
- * the interferes test, and we must have had a situation where the
- * intervals were:
- *
- * from to
- * ^
- * |
- * v
- * ^
- * |
- * v
- *
- * Some register R that might get coalesced with one of these two could
- * only be referencing "to", otherwise "from"'s range would have been
- * longer. R's range could also only start at the end of "to" or later,
- * otherwise it will conflict with "to" when we try to coalesce "to"
- * into Rw anyway.
- */
- live_intervals_valid = false;
-
progress = true;
continue;
}
+ if (progress)
+ invalidate_live_intervals();
+
return progress;
}
continue;
if (inst->opcode != BRW_OPCODE_MOV ||
- inst->predicate ||
+ inst->is_partial_write() ||
inst->saturate ||
inst->dst.file != GRF || (inst->src[0].file != GRF &&
inst->src[0].file != UNIFORM)||
}
}
+ if (has_source_modifiers) {
+ for (int i = 0; i < 3; i++) {
+ if (scan_inst->src[i].file == GRF &&
+ scan_inst->src[i].reg == inst->dst.reg &&
+ scan_inst->src[i].reg_offset == inst->dst.reg_offset &&
+ inst->dst.type != scan_inst->src[i].type)
+ {
+ interfered = true;
+ break;
+ }
+ }
+ }
+
+
/* The gen6 MATH instruction can't handle source modifiers or
* unusual register regions, so avoid coalescing those for
* now. We should do something more specific.
break;
}
+ if (scan_inst->mlen > 0 && scan_inst->base_mrf == -1 &&
+ scan_inst->src[0].file == GRF &&
+ scan_inst->src[0].reg == inst->dst.reg) {
+ interfered = true;
+ break;
+ }
+
/* The accumulator result appears to get used for the
* conditional modifier generation. When negating a UD
* value, there is a 33rd bit generated for the sign in the
new_src.abs = 1;
}
new_src.negate ^= scan_inst->src[i].negate;
+ new_src.sechalf = scan_inst->src[i].sechalf;
scan_inst->src[i] = new_src;
}
}
}
if (progress)
- live_intervals_valid = false;
+ invalidate_live_intervals();
return progress;
}
next_ip++;
if (inst->opcode != BRW_OPCODE_MOV ||
- inst->predicate ||
+ inst->is_partial_write() ||
inst->dst.file != MRF || inst->src[0].file != GRF ||
inst->dst.type != inst->src[0].type ||
inst->src[0].abs || inst->src[0].negate || inst->src[0].smear != -1)
/* Can't compute-to-MRF this GRF if someone else was going to
* read it later.
*/
- if (this->virtual_grf_use[inst->src[0].reg] > ip)
+ if (this->virtual_grf_end[inst->src[0].reg] > ip)
continue;
/* Found a move of a GRF to a MRF. Let's see if we can go
* into a compute-to-MRF.
*/
- /* If it's predicated, it (probably) didn't populate all
- * the channels. We might be able to rewrite everything
+ /* If this one instruction didn't populate all the
+ * channels, bail. We might be able to rewrite everything
* that writes that reg, but it would require smarter
* tracking to delay the rewriting until complete success.
*/
- if (scan_inst->predicate)
+ if (scan_inst->is_partial_write())
break;
- /* If it's half of register setup and not the same half as
- * our MOV we're trying to remove, bail for now.
- */
- if (scan_inst->force_uncompressed != inst->force_uncompressed ||
- scan_inst->force_sechalf != inst->force_sechalf) {
- break;
- }
-
/* Things returning more than one register would need us to
* understand coalescing out more than one MOV at a time.
*/
- if (scan_inst->regs_written() > 1)
+ if (scan_inst->regs_written > 1)
break;
/* SEND instructions can't have MRF as a destination. */
if (scan_inst->mlen)
break;
- if (intel->gen == 6) {
+ if (brw->gen == 6) {
/* gen6 math instructions must have the destination be
* GRF, so no compute-to-MRF for them.
*/
}
}
- if (scan_inst->mlen > 0) {
+ if (scan_inst->mlen > 0 && scan_inst->base_mrf != -1) {
/* Found a SEND instruction, which means that there are
* live values in MRFs from base_mrf to base_mrf +
* scan_inst->mlen - 1. Don't go pushing our MRF write up
}
if (progress)
- live_intervals_valid = false;
+ invalidate_live_intervals();
return progress;
}
last_mrf_move[inst->dst.reg] = NULL;
}
- if (inst->mlen > 0) {
+ if (inst->mlen > 0 && inst->base_mrf != -1) {
/* Found a SEND instruction, which will include two or fewer
* implied MRF writes. We could do better here.
*/
if (inst->opcode == BRW_OPCODE_MOV &&
inst->dst.file == MRF &&
inst->src[0].file == GRF &&
- !inst->predicate) {
+ !inst->is_partial_write()) {
last_mrf_move[inst->dst.reg] = inst;
}
}
if (progress)
- live_intervals_valid = false;
+ invalidate_live_intervals();
return progress;
}
int grf;
if (inst->src[i].file == GRF) {
grf = inst->src[i].reg;
- } else if (inst->src[i].file == FIXED_HW_REG &&
+ } else if (inst->src[i].file == HW_REG &&
inst->src[i].fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
grf = inst->src[i].fixed_hw_reg.nr;
} else {
fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
{
int reg_size = dispatch_width / 8;
- int write_len = inst->regs_written() * reg_size;
+ int write_len = inst->regs_written * reg_size;
int first_write_grf = inst->dst.reg;
bool needs_dep[BRW_MAX_MRF];
assert(write_len < (int)sizeof(needs_dep) - 1);
inst->insert_before(DEP_RESOLVE_MOV(first_write_grf + i));
}
}
+ return;
}
bool scan_inst_16wide = (dispatch_width > 8 &&
* dependency has more latency than a MOV.
*/
if (scan_inst->dst.file == GRF) {
- for (int i = 0; i < scan_inst->regs_written(); i++) {
+ for (int i = 0; i < scan_inst->regs_written; i++) {
int reg = scan_inst->dst.reg + i * reg_size;
if (reg >= first_write_grf &&
void
fs_visitor::insert_gen4_post_send_dependency_workarounds(fs_inst *inst)
{
- int write_len = inst->regs_written() * dispatch_width / 8;
+ int write_len = inst->regs_written * dispatch_width / 8;
int first_write_grf = inst->dst.reg;
bool needs_dep[BRW_MAX_MRF];
assert(write_len < (int)sizeof(needs_dep) - 1);
if (needs_dep[i])
scan_inst->insert_before(DEP_RESOLVE_MOV(first_write_grf + i));
}
+ return;
}
/* Clear the flag for registers that actually got read (as expected). */
void
fs_visitor::insert_gen4_send_dependency_workarounds()
{
- if (intel->gen != 4 || intel->is_g4x)
+ if (brw->gen != 4 || brw->is_g4x)
return;
/* Note that we're done with register allocation, so GRF fs_regs always
if (inst->opcode != FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD)
continue;
- if (intel->gen >= 7) {
+ if (brw->gen >= 7) {
/* The offset arg before was a vec4-aligned byte offset. We need to
* turn it into a dword offset.
*/
inst->opcode = FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7;
inst->src[1] = payload;
- this->live_intervals_valid = false;
+ invalidate_live_intervals();
} else {
/* Before register allocation, we didn't tell the scheduler about the
* MRF we use. We know it's safe to use this MRF because nothing
}
void
-fs_visitor::dump_instruction(fs_inst *inst)
+fs_visitor::dump_instruction(backend_instruction *be_inst)
{
+ fs_inst *inst = (fs_inst *)be_inst;
+
if (inst->predicate) {
printf("(%cf0.%d) ",
inst->predicate_inverse ? '-' : '+',
if (inst->conditional_mod) {
printf(".cmod");
if (!inst->predicate &&
- (intel->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
+ (brw->gen < 5 || (inst->opcode != BRW_OPCODE_SEL &&
inst->opcode != BRW_OPCODE_IF &&
inst->opcode != BRW_OPCODE_WHILE))) {
- printf(".f0.%d\n", inst->flag_subreg);
+ printf(".f0.%d", inst->flag_subreg);
}
}
printf(" ");
case UNIFORM:
printf("***u%d***", inst->dst.reg);
break;
+ case HW_REG:
+ printf("hw_reg%d", inst->dst.fixed_hw_reg.nr);
+ if (inst->dst.fixed_hw_reg.subnr)
+ printf("+%d", inst->dst.fixed_hw_reg.subnr);
+ break;
default:
printf("???");
break;
break;
}
break;
+ case HW_REG:
+ if (inst->src[i].fixed_hw_reg.negate)
+ printf("-");
+ if (inst->src[i].fixed_hw_reg.abs)
+ printf("|");
+ printf("hw_reg%d", inst->src[i].fixed_hw_reg.nr);
+ if (inst->src[i].fixed_hw_reg.subnr)
+ printf("+%d", inst->src[i].fixed_hw_reg.subnr);
+ if (inst->src[i].fixed_hw_reg.abs)
+ printf("|");
+ break;
default:
printf("???");
break;
printf("\n");
}
-void
-fs_visitor::dump_instructions()
-{
- int ip = 0;
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
- printf("%d: ", ip++);
- dump_instruction(inst);
- }
-}
-
/**
* Possibly returns an instruction that set up @param reg.
*
fs_reg reg)
{
if (end == start ||
- end->predicate ||
- end->force_uncompressed ||
- end->force_sechalf ||
+ end->is_partial_write() ||
reg.reladdr ||
!reg.equals(end->dst)) {
return NULL;
void
fs_visitor::setup_payload_gen6()
{
- struct intel_context *intel = &brw->intel;
bool uses_depth =
(fp->Base.InputsRead & (1 << VARYING_SLOT_POS)) != 0;
unsigned barycentric_interp_modes = c->prog_data.barycentric_interp_modes;
- assert(intel->gen >= 6);
+ assert(brw->gen >= 6);
/* R0-1: masks, pixel X/Y coordinates. */
c->nr_payload_regs = 2;
c->nr_payload_regs++;
}
}
+
+ c->prog_data.uses_pos_offset = c->key.compute_pos_offset;
/* R31: MSAA position offsets. */
+ if (c->prog_data.uses_pos_offset) {
+ c->sample_pos_reg = c->nr_payload_regs;
+ c->nr_payload_regs++;
+ }
+
/* R32-: bary for 32-pixel. */
/* R58-59: interp W for 32-pixel. */
}
}
+void
+fs_visitor::assign_binding_table_offsets()
+{
+ uint32_t next_binding_table_offset = 0;
+
+ c->prog_data.binding_table.render_target_start = next_binding_table_offset;
+ next_binding_table_offset += c->key.nr_color_regions;
+
+ assign_common_binding_table_offsets(next_binding_table_offset);
+}
+
bool
fs_visitor::run()
{
sanity_param_count = fp->Base.Parameters->NumParameters;
uint32_t orig_nr_params = c->prog_data.nr_params;
- if (intel->gen >= 6)
+ assign_binding_table_offsets();
+
+ if (brw->gen >= 6)
setup_payload_gen6();
else
setup_payload_gen4();
emit_shader_time_begin();
calculate_urb_setup();
- if (intel->gen < 6)
- emit_interpolation_setup_gen4();
- else
- emit_interpolation_setup_gen6();
+ if (fp->Base.InputsRead > 0) {
+ if (brw->gen < 6)
+ emit_interpolation_setup_gen4();
+ else
+ emit_interpolation_setup_gen6();
+ }
/* We handle discards by keeping track of the still-live pixels in f0.1.
* Initialize it with the dispatched pixels.
split_virtual_grfs();
move_uniform_array_access_to_pull_constants();
+ remove_dead_constants();
setup_pull_constants();
bool progress;
progress = opt_cse() || progress;
progress = opt_copy_propagate() || progress;
progress = dead_code_eliminate() || progress;
+ progress = dead_code_eliminate_local() || progress;
progress = register_coalesce() || progress;
progress = register_coalesce_2() || progress;
progress = compute_to_mrf() || progress;
} while (progress);
- remove_dead_constants();
-
schedule_instructions(false);
lower_uniform_pull_constant_loads();
assign_curb_setup();
assign_urb_setup();
- if (0) {
- /* Debug of register spilling: Go spill everything. */
- for (int i = 0; i < virtual_grf_count; i++) {
- spill_reg(i);
- }
- }
-
if (0)
assign_regs_trivial();
else {
struct gl_shader_program *prog,
unsigned *final_assembly_size)
{
- struct intel_context *intel = &brw->intel;
bool start_busy = false;
float start_time = 0;
- if (unlikely(intel->perf_debug)) {
- start_busy = (intel->batch.last_bo &&
- drm_intel_bo_busy(intel->batch.last_bo));
+ if (unlikely(brw->perf_debug)) {
+ start_busy = (brw->batch.last_bo &&
+ drm_intel_bo_busy(brw->batch.last_bo));
start_time = get_time();
}
shader = (brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
if (unlikely(INTEL_DEBUG & DEBUG_WM)) {
- if (shader) {
+ if (prog) {
printf("GLSL IR for native fragment shader %d:\n", prog->Name);
_mesa_print_ir(shader->ir, NULL);
printf("\n\n");
*/
fs_visitor v(brw, c, prog, fp, 8);
if (!v.run()) {
- prog->LinkStatus = false;
- ralloc_strcat(&prog->InfoLog, v.fail_msg);
+ if (prog) {
+ prog->LinkStatus = false;
+ ralloc_strcat(&prog->InfoLog, v.fail_msg);
+ }
_mesa_problem(NULL, "Failed to compile fragment shader: %s\n",
- v.fail_msg);
+ v.fail_msg);
return NULL;
}
exec_list *simd16_instructions = NULL;
fs_visitor v2(brw, c, prog, fp, 16);
- bool no16 = INTEL_DEBUG & DEBUG_NO16;
- if (intel->gen >= 5 && c->prog_data.nr_pull_params == 0 && likely(!no16)) {
- v2.import_uniforms(&v);
- if (!v2.run()) {
- perf_debug("16-wide shader failed to compile, falling back to "
- "8-wide at a 10-20%% performance cost: %s", v2.fail_msg);
+ if (brw->gen >= 5 && likely(!(INTEL_DEBUG & DEBUG_NO16))) {
+ if (c->prog_data.nr_pull_params == 0) {
+ /* Try a 16-wide compile */
+ v2.import_uniforms(&v);
+ if (!v2.run()) {
+ perf_debug("16-wide shader failed to compile, falling back to "
+ "8-wide at a 10-20%% performance cost: %s", v2.fail_msg);
+ } else {
+ simd16_instructions = &v2.instructions;
+ }
} else {
- simd16_instructions = &v2.instructions;
+ perf_debug("Skipping 16-wide due to pull parameters.\n");
}
}
- c->prog_data.dispatch_width = 8;
-
fs_generator g(brw, c, prog, fp, v.dual_src_output.file != BAD_FILE);
const unsigned *generated = g.generate_assembly(&v.instructions,
simd16_instructions,
final_assembly_size);
- if (unlikely(intel->perf_debug) && shader) {
+ if (unlikely(brw->perf_debug) && shader) {
if (shader->compiled_once)
brw_wm_debug_recompile(brw, prog, &c->key);
shader->compiled_once = true;
- if (start_busy && !drm_intel_bo_busy(intel->batch.last_bo)) {
+ if (start_busy && !drm_intel_bo_busy(brw->batch.last_bo)) {
perf_debug("FS compile took %.03f ms and stalled the GPU\n",
(get_time() - start_time) * 1000);
}
brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog)
{
struct brw_context *brw = brw_context(ctx);
- struct intel_context *intel = &brw->intel;
struct brw_wm_prog_key key;
if (!prog->_LinkedShaders[MESA_SHADER_FRAGMENT])
memset(&key, 0, sizeof(key));
- if (intel->gen < 6) {
+ if (brw->gen < 6) {
if (fp->UsesKill)
key.iz_lookup |= IZ_PS_KILL_ALPHATEST_BIT;
key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
}
- if (prog->Name != 0)
- key.proj_attrib_mask = ~(GLbitfield64) 0;
- else {
- /* Bit VARYING_BIT_POS of key.proj_attrib_mask is never used, so to
- * avoid unnecessary recompiles, always set it to 1.
- */
- key.proj_attrib_mask |= VARYING_BIT_POS;
- }
-
- if (intel->gen < 6)
- key.input_slots_valid |= BITFIELD64_BIT(VARYING_SLOT_POS);
-
- for (int i = 0; i < VARYING_SLOT_MAX; i++) {
- if (!(fp->Base.InputsRead & BITFIELD64_BIT(i)))
- continue;
+ if (brw->gen < 6 || _mesa_bitcount_64(fp->Base.InputsRead &
+ BRW_FS_VARYING_INPUT_MASK) > 16)
+ key.input_slots_valid = fp->Base.InputsRead | VARYING_BIT_POS;
- if (prog->Name == 0)
- key.proj_attrib_mask |= BITFIELD64_BIT(i);
+ key.clamp_fragment_color = ctx->API == API_OPENGL_COMPAT;
- if (intel->gen < 6) {
- if (_mesa_varying_slot_in_fs((gl_varying_slot) i))
- key.input_slots_valid |= BITFIELD64_BIT(i);
- }
- }
-
- key.clamp_fragment_color = true;
-
- for (int i = 0; i < MAX_SAMPLERS; i++) {
+ unsigned sampler_count = _mesa_fls(fp->Base.SamplersUsed);
+ for (unsigned i = 0; i < sampler_count; i++) {
if (fp->Base.ShadowSamplers & (1 << i)) {
/* Assume DEPTH_TEXTURE_MODE is the default: X, X, X, 1 */
key.tex.swizzles[i] =
key.nr_color_regions = 1;
+ /* GL_FRAGMENT_SHADER_DERIVATIVE_HINT is almost always GL_DONT_CARE. The
+ * quality of the derivatives is likely to be determined by the driconf
+ * option.
+ */
+ key.high_quality_derivatives = brw->disable_derivative_optimization;
+
key.program_string_id = bfp->id;
- uint32_t old_prog_offset = brw->wm.prog_offset;
+ uint32_t old_prog_offset = brw->wm.base.prog_offset;
struct brw_wm_prog_data *old_prog_data = brw->wm.prog_data;
bool success = do_wm_prog(brw, prog, bfp, &key);
- brw->wm.prog_offset = old_prog_offset;
+ brw->wm.base.prog_offset = old_prog_offset;
brw->wm.prog_data = old_prog_data;
return success;
projects / mesa.git / blobdiff