uint32_t const_offset);
void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
- bool run_fs(bool do_rep_send);
+ bool run_fs(bool allow_spilling, bool do_rep_send);
bool run_vs(gl_clip_plane *clip_planes);
bool run_tcs_single_patch();
bool run_tes();
bool run_gs();
bool run_cs();
void optimize();
- void allocate_registers();
+ void allocate_registers(bool allow_spilling);
void setup_fs_payload_gen4();
void setup_fs_payload_gen6();
void setup_vs_payload();
void assign_tcs_single_patch_urb_setup();
void assign_tes_urb_setup();
void assign_gs_urb_setup();
- bool assign_regs(bool allow_spilling);
+ bool assign_regs(bool allow_spilling, bool spill_all);
void assign_regs_trivial();
void calculate_payload_ranges(int payload_node_count,
int *payload_last_use_ip);
void lower_uniform_pull_constant_loads();
bool lower_load_payload();
bool lower_pack();
- bool lower_d2f();
+ bool lower_d2x();
bool lower_logical_sends();
bool lower_integer_multiplication();
bool lower_minmax();
void generate_stencil_ref_packing(fs_inst *inst, struct brw_reg dst,
struct brw_reg src);
void generate_barrier(fs_inst *inst, struct brw_reg src);
- void generate_blorp_fb_write(fs_inst *inst, struct brw_reg payload);
void generate_linterp(fs_inst *inst, struct brw_reg dst,
struct brw_reg *src);
void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
bool brw_do_channel_expressions(struct exec_list *instructions);
bool brw_do_vector_splitting(struct exec_list *instructions);
+
+void shuffle_32bit_load_result_to_64bit_data(const brw::fs_builder &bld,
+ const fs_reg &dst,
+ const fs_reg &src,
+ uint32_t components);
+
+void shuffle_64bit_data_for_32bit_write(const brw::fs_builder &bld,
+ const fs_reg &dst,
+ const fs_reg &src,
+ uint32_t components);