#pragma once
#include "brw_shader.h"
+#include "brw_ir_fs.h"
extern "C" {
#include "program/prog_print.h"
#include "program/prog_optimize.h"
#include "util/register_allocate.h"
-#include "program/sampler.h"
#include "program/hash_table.h"
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_wm.h"
-#include "brw_shader.h"
#include "intel_asm_annotation.h"
}
#include "glsl/glsl_types.h"
#include "glsl/ir.h"
-
-#define MAX_SAMPLER_MESSAGE_SIZE 11
-#define MAX_VGRF_SIZE 16
+#include "glsl/nir/nir.h"
+#include "program/sampler.h"
struct bblock_t;
namespace {
class fs_live_variables;
}
-class fs_inst;
-class fs_visitor;
-
-class fs_reg : public backend_reg {
-public:
- DECLARE_RALLOC_CXX_OPERATORS(fs_reg)
-
- void init();
-
- fs_reg();
- explicit fs_reg(float f);
- explicit fs_reg(int32_t i);
- explicit fs_reg(uint32_t u);
- fs_reg(struct brw_reg fixed_hw_reg);
- fs_reg(enum register_file file, int reg);
- fs_reg(enum register_file file, int reg, enum brw_reg_type type);
- fs_reg(enum register_file file, int reg, enum brw_reg_type type, uint8_t width);
- fs_reg(fs_visitor *v, const struct glsl_type *type);
-
- bool equals(const fs_reg &r) const;
- bool is_valid_3src() const;
- bool is_contiguous() const;
-
- fs_reg &apply_stride(unsigned stride);
- /** Smear a channel of the reg to all channels. */
- fs_reg &set_smear(unsigned subreg);
-
- /**
- * Offset in bytes from the start of the register. Values up to a
- * backend_reg::reg_offset unit are valid.
- */
- int subreg_offset;
-
- fs_reg *reladdr;
-
- /**
- * The register width. This indicates how many hardware values are
- * represented by each virtual value. Valid values are 1, 8, or 16.
- * For immediate values, this is 1. Most of the rest of the time, it
- * will be equal to the dispatch width.
- */
- uint8_t width;
-
- /**
- * Returns the effective register width when used as a source in the
- * given instruction. Registers such as uniforms and immediates
- * effectively take on the width of the instruction in which they are
- * used.
- */
- uint8_t effective_width;
-
- /** Register region horizontal stride */
- uint8_t stride;
-};
-
-static inline fs_reg
-retype(fs_reg reg, enum brw_reg_type type)
-{
- reg.fixed_hw_reg.type = reg.type = type;
- return reg;
-}
-
-static inline fs_reg
-byte_offset(fs_reg reg, unsigned delta)
-{
- switch (reg.file) {
- case BAD_FILE:
- break;
- case GRF:
- reg.reg_offset += delta / 32;
- break;
- case MRF:
- reg.reg += delta / 32;
- break;
- default:
- assert(delta == 0);
- }
- reg.subreg_offset += delta % 32;
- return reg;
-}
-
-static inline fs_reg
-horiz_offset(fs_reg reg, unsigned delta)
-{
- switch (reg.file) {
- case BAD_FILE:
- case UNIFORM:
- case IMM:
- /* These only have a single component that is implicitly splatted. A
- * horizontal offset should be a harmless no-op.
- */
- break;
- case GRF:
- case MRF:
- return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
- default:
- assert(delta == 0);
- }
- return reg;
-}
-
-static inline fs_reg
-offset(fs_reg reg, unsigned delta)
-{
- assert(reg.stride > 0);
- switch (reg.file) {
- case BAD_FILE:
- break;
- case GRF:
- case MRF:
- return byte_offset(reg, delta * reg.width * reg.stride * type_sz(reg.type));
- case UNIFORM:
- reg.reg_offset += delta;
- break;
- default:
- assert(delta == 0);
- }
- return reg;
-}
-
-static inline fs_reg
-component(fs_reg reg, unsigned idx)
-{
- assert(reg.subreg_offset == 0);
- assert(idx < reg.width);
- reg.subreg_offset = idx * type_sz(reg.type);
- reg.width = 1;
- return reg;
-}
-
-/**
- * Get either of the 8-component halves of a 16-component register.
- *
- * Note: this also works if \c reg represents a SIMD16 pair of registers.
- */
-static inline fs_reg
-half(fs_reg reg, unsigned idx)
-{
- assert(idx < 2);
- assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
- assert(reg.width == 16);
- reg.width = 8;
- return horiz_offset(reg, 8 * idx);
-}
-
-static const fs_reg reg_undef;
-
-class ip_record : public exec_node {
-public:
- DECLARE_RALLOC_CXX_OPERATORS(ip_record)
-
- ip_record(int ip)
- {
- this->ip = ip;
- }
-
- int ip;
-};
-
-class fs_inst : public backend_instruction {
- fs_inst &operator=(const fs_inst &);
-
- void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
- fs_reg *src, int sources);
-
-public:
- DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
-
- fs_inst();
- fs_inst(enum opcode opcode, uint8_t exec_size);
- fs_inst(enum opcode opcode, const fs_reg &dst);
- fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
- const fs_reg &src0);
- fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
- fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
- const fs_reg &src0, const fs_reg &src1);
- fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
- const fs_reg &src1);
- fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
- const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
- fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
- const fs_reg &src1, const fs_reg &src2);
- fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
- fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
- fs_reg src[], int sources);
- fs_inst(const fs_inst &that);
-
- void resize_sources(uint8_t num_sources);
-
- bool equals(fs_inst *inst) const;
- bool overwrites_reg(const fs_reg ®) const;
- bool is_send_from_grf() const;
- bool is_partial_write() const;
- int regs_read(fs_visitor *v, int arg) const;
- bool can_do_source_mods(struct brw_context *brw);
-
- bool reads_flag() const;
- bool writes_flag() const;
-
- fs_reg dst;
- fs_reg *src;
-
- uint8_t sources; /**< Number of fs_reg sources. */
-
- /**
- * Execution size of the instruction. This is used by the generator to
- * generate the correct binary for the given fs_inst. Current valid
- * values are 1, 8, 16.
- */
- uint8_t exec_size;
-
- /* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
- * mod and predication.
- */
- uint8_t flag_subreg;
-
- uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
- bool eot:1;
- bool header_present:1;
- bool shadow_compare:1;
- bool force_uncompressed:1;
- bool force_sechalf:1;
- bool pi_noperspective:1; /**< Pixel interpolator noperspective flag */
-};
-
/**
* The fragment shader front-end.
*
struct gl_shader_program *shader_prog,
struct gl_fragment_program *fp,
unsigned dispatch_width);
+
+ fs_visitor(struct brw_context *brw,
+ void *mem_ctx,
+ const struct brw_vs_prog_key *key,
+ struct brw_vs_prog_data *prog_data,
+ struct gl_shader_program *shader_prog,
+ struct gl_vertex_program *cp,
+ unsigned dispatch_width);
+
~fs_visitor();
void init();
fs_reg *variable_storage(ir_variable *var);
- int virtual_grf_alloc(int size);
+ fs_reg vgrf(const glsl_type *const type);
+ fs_reg vgrf(int num_components);
void import_uniforms(fs_visitor *v);
+ void setup_uniform_clipplane_values();
+ void compute_clip_distance();
void visit(ir_variable *ir);
void visit(ir_assignment *ir);
void visit(ir_emit_vertex *);
void visit(ir_end_primitive *);
- uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
- void swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler);
+ uint32_t gather_channel(int orig_chan, uint32_t sampler);
+ void swizzle_result(ir_texture_opcode op, int dest_components,
+ fs_reg orig_val, uint32_t sampler);
fs_inst *emit(fs_inst *inst);
void emit(exec_list list);
const fs_reg &varying_offset,
uint32_t const_offset);
- bool run();
+ bool run_fs();
+ bool run_vs();
+ void optimize();
+ void allocate_registers();
void assign_binding_table_offsets();
void setup_payload_gen4();
void setup_payload_gen6();
+ void setup_vs_payload();
+ void fixup_3src_null_dest();
void assign_curb_setup();
void calculate_urb_setup();
void assign_urb_setup();
+ void assign_vs_urb_setup();
bool assign_regs(bool allow_spilling);
void assign_regs_trivial();
void get_used_mrfs(bool *mrf_used);
void calculate_live_intervals();
void calculate_register_pressure();
bool opt_algebraic();
+ bool opt_redundant_discard_jumps();
bool opt_cse();
bool opt_cse_local(bblock_t *block);
bool opt_copy_propagate();
bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
bool opt_copy_propagate_local(void *mem_ctx, bblock_t *block,
exec_list *acp);
- void opt_drop_redundant_mov_to_flags();
bool opt_register_renaming();
bool register_coalesce();
bool compute_to_mrf();
void no16(const char *msg, ...);
void lower_uniform_pull_constant_loads();
bool lower_load_payload();
-
- void push_force_uncompressed();
- void pop_force_uncompressed();
+ bool opt_combine_constants();
void emit_dummy_fs();
void emit_repclear_shader();
- fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
+ fs_reg *emit_fragcoord_interpolation(bool pixel_center_integer,
+ bool origin_upper_left);
fs_inst *emit_linterp(const fs_reg &attr, const fs_reg &interp,
glsl_interp_qualifier interpolation_mode,
bool is_centroid, bool is_sample);
fs_reg *emit_frontfacing_interpolation();
fs_reg *emit_samplepos_setup();
- fs_reg *emit_sampleid_setup(ir_variable *ir);
- fs_reg *emit_general_interpolation(ir_variable *ir);
+ fs_reg *emit_sampleid_setup();
+ void emit_general_interpolation(fs_reg attr, const char *name,
+ const glsl_type *type,
+ glsl_interp_qualifier interpolation_mode,
+ int location, bool mod_centroid,
+ bool mod_sample);
+ fs_reg *emit_vs_system_value(int location);
void emit_interpolation_setup_gen4();
void emit_interpolation_setup_gen6();
void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
- fs_reg rescale_texcoord(fs_reg coordinate, const glsl_type *coord_type,
+ fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
bool is_rect, uint32_t sampler, int texunit);
- fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst,
+ fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
fs_reg coordinate, int coord_components,
fs_reg shadow_comp,
fs_reg lod, fs_reg lod2, int grad_components,
uint32_t sampler);
- fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst,
+ fs_inst *emit_texture_gen4_simd16(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int vector_elements,
+ fs_reg shadow_c, fs_reg lod,
+ uint32_t sampler);
+ fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
fs_reg coordinate, int coord_components,
fs_reg shadow_comp,
fs_reg lod, fs_reg lod2, int grad_components,
fs_reg sample_index, uint32_t sampler,
bool has_offset);
- fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst,
+ fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
fs_reg coordinate, int coord_components,
fs_reg shadow_comp,
fs_reg lod, fs_reg lod2, int grad_components,
fs_reg sample_index, fs_reg mcs, fs_reg sampler,
fs_reg offset_value);
+ void emit_texture(ir_texture_opcode op,
+ const glsl_type *dest_type,
+ fs_reg coordinate, int components,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg dpdy, int grad_components,
+ fs_reg sample_index,
+ fs_reg offset,
+ fs_reg mcs,
+ int gather_component,
+ bool is_cube_array,
+ bool is_rect,
+ uint32_t sampler,
+ fs_reg sampler_reg,
+ int texunit);
fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
+ void resolve_source_modifiers(fs_reg *src);
fs_reg fix_math_operand(fs_reg src);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0, fs_reg src1);
- void emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
- const fs_reg &a);
+ fs_inst *emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
+ const fs_reg &a);
void emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
const fs_reg &src0, const fs_reg &src1);
+ void emit_discard_jump();
+ bool try_emit_b2f_of_comparison(ir_expression *ir);
bool try_emit_saturate(ir_expression *ir);
+ bool try_emit_line(ir_expression *ir);
bool try_emit_mad(ir_expression *ir);
- void try_replace_with_sel();
+ bool try_replace_with_sel();
+ bool try_opt_frontfacing_ternary(ir_if *ir);
bool opt_peephole_sel();
bool opt_peephole_predicated_break();
bool opt_saturate_propagation();
+ bool opt_cmod_propagation();
void emit_bool_to_cond_code(ir_rvalue *condition);
+ void emit_bool_to_cond_code_of_reg(ir_expression *expr, fs_reg op[3]);
void emit_if_gen6(ir_if *ir);
void emit_unspill(bblock_t *block, fs_inst *inst, fs_reg reg,
uint32_t spill_offset, int count);
const struct prog_instruction *fpi,
fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
- int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components);
+ void emit_nir_code();
+ void nir_setup_inputs(nir_shader *shader);
+ void nir_setup_outputs(nir_shader *shader);
+ void nir_setup_uniforms(nir_shader *shader);
+ void nir_setup_uniform(nir_variable *var);
+ void nir_setup_builtin_uniform(nir_variable *var);
+ void nir_emit_system_values(nir_shader *shader);
+ void nir_emit_impl(nir_function_impl *impl);
+ void nir_emit_cf_list(exec_list *list);
+ void nir_emit_if(nir_if *if_stmt);
+ void nir_emit_loop(nir_loop *loop);
+ void nir_emit_block(nir_block *block);
+ void nir_emit_instr(nir_instr *instr);
+ void nir_emit_alu(nir_alu_instr *instr);
+ void nir_emit_intrinsic(nir_intrinsic_instr *instr);
+ void nir_emit_texture(nir_tex_instr *instr);
+ void nir_emit_jump(nir_jump_instr *instr);
+ fs_reg get_nir_src(nir_src src);
+ fs_reg get_nir_dest(nir_dest dest);
+ void emit_percomp(fs_inst *inst, unsigned wr_mask);
+
+ bool optimize_frontfacing_ternary(nir_alu_instr *instr,
+ const fs_reg &result);
+
+ int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
+ bool use_2nd_half);
void emit_alpha_test();
fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
- fs_reg src0_alpha, unsigned components);
+ fs_reg src0_alpha, unsigned components,
+ bool use_2nd_half = false);
void emit_fb_writes();
+ void emit_urb_writes();
void emit_shader_time_begin();
void emit_shader_time_end();
- void emit_shader_time_write(enum shader_time_shader_type type,
- fs_reg value);
+ fs_inst *SHADER_TIME_ADD(enum shader_time_shader_type type, fs_reg value);
void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
fs_reg dst, fs_reg offset, fs_reg src0,
void resolve_ud_negate(fs_reg *reg);
void resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg);
- fs_reg get_timestamp();
+ fs_reg get_timestamp(fs_inst **out_mov);
struct brw_reg interp_reg(int location, int channel);
void setup_uniform_values(ir_variable *ir);
void visit_atomic_counter_intrinsic(ir_call *ir);
const void *const key;
+ const struct brw_sampler_prog_key_data *key_tex;
+
struct brw_stage_prog_data *prog_data;
unsigned int sanity_param_count;
int *param_size;
- int *virtual_grf_sizes;
- int virtual_grf_count;
- int virtual_grf_array_size;
int *virtual_grf_start;
int *virtual_grf_end;
brw::fs_live_variables *live_intervals;
/** Number of uniform variable components visited. */
unsigned uniforms;
+ /** Total number of direct uniforms we can get from NIR */
+ unsigned num_direct_uniforms;
+
/** Byte-offset for the next available spot in the scratch space buffer. */
unsigned last_scratch;
struct hash_table *variable_ht;
fs_reg frag_depth;
fs_reg sample_mask;
- fs_reg outputs[BRW_MAX_DRAW_BUFFERS];
- unsigned output_components[BRW_MAX_DRAW_BUFFERS];
+ fs_reg outputs[VARYING_SLOT_MAX];
+ unsigned output_components[VARYING_SLOT_MAX];
fs_reg dual_src_output;
bool do_dual_src;
int first_non_payload_grf;
/** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
- int max_grf;
+ unsigned max_grf;
fs_reg *fp_temp_regs;
fs_reg *fp_input_regs;
+ fs_reg *nir_locals;
+ fs_reg *nir_globals;
+ fs_reg nir_inputs;
+ fs_reg nir_outputs;
+ fs_reg *nir_system_values;
+
/** @{ debug annotation info */
const char *current_annotation;
const void *base_ir;
fs_reg delta_x[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
fs_reg delta_y[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
fs_reg shader_start_time;
+ fs_reg userplane[MAX_CLIP_PLANES];
- int grf_used;
+ unsigned grf_used;
bool spilled_any_registers;
const unsigned dispatch_width; /**< 8 or 16 */
- int force_uncompressed_stack;
+ unsigned promoted_constants;
};
/**
public:
fs_generator(struct brw_context *brw,
void *mem_ctx,
- const struct brw_wm_prog_key *key,
- struct brw_wm_prog_data *prog_data,
- struct gl_shader_program *shader_prog,
- struct gl_fragment_program *fp,
+ const void *key,
+ struct brw_stage_prog_data *prog_data,
+ struct gl_program *fp,
+ unsigned promoted_constants,
bool runtime_check_aads_emit,
- bool debug_flag);
+ const char *stage_abbrev);
~fs_generator();
- const unsigned *generate_assembly(const cfg_t *simd8_cfg,
- const cfg_t *simd16_cfg,
- unsigned *assembly_size);
+ void enable_debug(const char *shader_name);
+ int generate_code(const cfg_t *cfg, int dispatch_width);
+ const unsigned *get_assembly(unsigned int *assembly_size);
private:
- void generate_code(const cfg_t *cfg);
void fire_fb_write(fs_inst *inst,
struct brw_reg payload,
struct brw_reg implied_header,
GLuint nr);
void generate_fb_write(fs_inst *inst, struct brw_reg payload);
+ void generate_urb_write(fs_inst *inst, struct brw_reg payload);
void generate_blorp_fb_write(fs_inst *inst);
void generate_pixel_xy(struct brw_reg dst, bool is_x);
void generate_linterp(fs_inst *inst, struct brw_reg dst,
void generate_math_g45(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src);
- void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src, struct brw_reg quality);
- void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
- struct brw_reg quality, bool negate_value);
+ void generate_ddx(enum opcode op, struct brw_reg dst, struct brw_reg src);
+ void generate_ddy(enum opcode op, struct brw_reg dst, struct brw_reg src,
+ bool negate_value);
void generate_scratch_write(fs_inst *inst, struct brw_reg src);
void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
struct gl_context *ctx;
struct brw_compile *p;
- gl_shader_stage stage;
const void * const key;
struct brw_stage_prog_data * const prog_data;
- struct gl_shader_program * const shader_prog;
const struct gl_program *prog;
unsigned dispatch_width; /**< 8 or 16 */
exec_list discard_halt_patches;
+ unsigned promoted_constants;
bool runtime_check_aads_emit;
- const bool debug_flag;
+ bool debug_flag;
+ const char *shader_name;
+ const char *stage_abbrev;
void *mem_ctx;
};
bool brw_do_channel_expressions(struct exec_list *instructions);
bool brw_do_vector_splitting(struct exec_list *instructions);
-bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
-
-struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);
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