public:
fs_visitor(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
- gl_shader_stage stage,
const void *key,
struct brw_stage_prog_data *prog_data,
- struct gl_shader_program *shader_prog,
struct gl_program *prog,
+ nir_shader *shader,
unsigned dispatch_width,
int shader_time_index);
void swizzle_result(ir_texture_opcode op, int dest_components,
fs_reg orig_val, uint32_t sampler);
- int type_size(const struct glsl_type *type);
fs_inst *get_instruction_generating_reg(fs_inst *start,
fs_inst *end,
const fs_reg ®);
bool run_cs();
void optimize();
void allocate_registers();
- void assign_binding_table_offsets();
void setup_payload_gen4();
void setup_payload_gen6();
void setup_vs_payload();
void spill_reg(int spill_reg);
void split_virtual_grfs();
bool compact_virtual_grfs();
- void move_uniform_array_access_to_pull_constants();
void assign_constant_locations();
void demote_pull_constants();
void invalidate_live_intervals();
void calculate_live_intervals();
void calculate_register_pressure();
+ void validate();
bool opt_algebraic();
bool opt_redundant_discard_jumps();
bool opt_cse();
bool lower_load_payload();
bool lower_logical_sends();
bool lower_integer_multiplication();
+ bool lower_simd_width();
bool opt_combine_constants();
void emit_dummy_fs();
void emit_interpolation_setup_gen6();
void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
fs_reg rescale_texcoord(fs_reg coordinate, int coord_components,
- bool is_rect, uint32_t sampler, int texunit);
- fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
- fs_reg coordinate, int coord_components,
- fs_reg shadow_comp,
- fs_reg lod, fs_reg lod2, int grad_components,
- uint32_t sampler);
- fs_inst *emit_texture_gen4_simd16(ir_texture_opcode op, fs_reg dst,
- fs_reg coordinate, int vector_elements,
- fs_reg shadow_c, fs_reg lod,
- uint32_t sampler);
- fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
- fs_reg coordinate, int coord_components,
- fs_reg shadow_comp,
- fs_reg lod, fs_reg lod2, int grad_components,
- fs_reg sample_index, uint32_t sampler,
- bool has_offset);
- fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
- fs_reg coordinate, int coord_components,
- fs_reg shadow_comp,
- fs_reg lod, fs_reg lod2, int grad_components,
- fs_reg sample_index, fs_reg mcs, fs_reg sampler,
- fs_reg offset_value);
+ bool is_rect, uint32_t sampler);
void emit_texture(ir_texture_opcode op,
const glsl_type *dest_type,
fs_reg coordinate, int components,
bool is_cube_array,
bool is_rect,
uint32_t sampler,
- fs_reg sampler_reg,
- int texunit);
- fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
+ fs_reg sampler_reg);
+ fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
+ const fs_reg &sampler);
void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
- void resolve_source_modifiers(fs_reg *src);
+ fs_reg resolve_source_modifiers(const fs_reg &src);
void emit_discard_jump();
- bool try_replace_with_sel();
bool opt_peephole_sel();
bool opt_peephole_predicated_break();
bool opt_saturate_propagation();
uint32_t spill_offset, int count);
void emit_nir_code();
- void nir_setup_inputs(nir_shader *shader);
- void nir_setup_outputs(nir_shader *shader);
- void nir_setup_uniforms(nir_shader *shader);
- void nir_setup_uniform(nir_variable *var);
- void nir_setup_builtin_uniform(nir_variable *var);
- void nir_emit_system_values(nir_shader *shader);
+ void nir_setup_inputs();
+ void nir_setup_outputs();
+ void nir_setup_uniforms();
+ void nir_emit_system_values();
void nir_emit_impl(nir_function_impl *impl);
void nir_emit_cf_list(exec_list *list);
void nir_emit_if(nir_if *if_stmt);
nir_ssa_undef_instr *instr);
void nir_emit_intrinsic(const brw::fs_builder &bld,
nir_intrinsic_instr *instr);
+ void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
+ int op, nir_intrinsic_instr *instr);
void nir_emit_texture(const brw::fs_builder &bld,
nir_tex_instr *instr);
void nir_emit_jump(const brw::fs_builder &bld,
nir_jump_instr *instr);
fs_reg get_nir_src(nir_src src);
fs_reg get_nir_dest(nir_dest dest);
+ fs_reg get_nir_image_deref(const nir_deref_var *deref);
void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
unsigned wr_mask);
bool optimize_frontfacing_ternary(nir_alu_instr *instr,
const fs_reg &result);
- void setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
- unsigned exec_size, bool use_2nd_half);
void emit_alpha_test();
fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
fs_reg color1, fs_reg color2,
- fs_reg src0_alpha, unsigned components,
- unsigned exec_size, bool use_2nd_half = false);
+ fs_reg src0_alpha, unsigned components);
void emit_fb_writes();
void emit_urb_writes();
void emit_cs_terminate();
+ fs_reg *emit_cs_local_invocation_id_setup();
+ fs_reg *emit_cs_work_group_id_setup();
void emit_barrier();
int shader_time_subindex,
fs_reg value);
- void emit_untyped_atomic(unsigned atomic_op, unsigned surf_index,
- fs_reg dst, fs_reg offset, fs_reg src0,
- fs_reg src1);
-
- void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
- fs_reg offset);
-
fs_reg get_timestamp(const brw::fs_builder &bld);
struct brw_reg interp_reg(int location, int channel);
+
int implied_mrf_writes(fs_inst *inst);
virtual void dump_instructions();
const struct brw_sampler_prog_key_data *key_tex;
struct brw_stage_prog_data *prog_data;
- unsigned int sanity_param_count;
+ struct gl_program *prog;
int *param_size;
/** Number of uniform variable components visited. */
unsigned uniforms;
- /** Total number of direct uniforms we can get from NIR */
- unsigned num_direct_uniforms;
-
/** Byte-offset for the next available spot in the scratch space buffer. */
unsigned last_scratch;
fs_reg result;
/** Register numbers for thread payload fields. */
- struct {
+ struct thread_payload {
uint8_t source_depth_reg;
uint8_t source_w_reg;
uint8_t aa_dest_stencil_reg;
uint8_t sample_pos_reg;
uint8_t sample_mask_in_reg;
uint8_t barycentric_coord_reg[BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT];
+ uint8_t local_invocation_id_reg;
/** The number of thread payload registers the hardware will supply. */
uint8_t num_regs;
struct brw_reg *src);
void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
struct brw_reg sampler_index);
+ void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
+ struct brw_reg src,
+ struct brw_reg surf_index);
void generate_math_gen6(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,
struct brw_reg msg_data,
unsigned msg_type);
- void generate_set_omask(fs_inst *inst,
- struct brw_reg dst,
- struct brw_reg sample_mask);
-
void generate_set_sample_id(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,
bool brw_do_channel_expressions(struct exec_list *instructions);
bool brw_do_vector_splitting(struct exec_list *instructions);
-void brw_setup_tex_for_precompile(struct brw_context *brw,
- struct brw_sampler_prog_key_data *tex,
- struct gl_program *prog);