#include "glsl/ir.h"
#define MAX_SAMPLER_MESSAGE_SIZE 11
+#define MAX_VGRF_SIZE 16
struct bblock_t;
namespace {
class fs_live_variables;
}
+class fs_inst;
class fs_visitor;
class fs_reg : public backend_reg {
fs_reg(fs_visitor *v, const struct glsl_type *type);
bool equals(const fs_reg &r) const;
- bool is_valid_3src() const;
bool is_contiguous() const;
- fs_reg &apply_stride(unsigned stride);
/** Smear a channel of the reg to all channels. */
fs_reg &set_smear(unsigned subreg);
* effectively take on the width of the instruction in which they are
* used.
*/
- uint8_t effective_width(const fs_visitor *v) const;
+ uint8_t effective_width;
/** Register region horizontal stride */
uint8_t stride;
return reg;
}
+static inline fs_reg
+horiz_offset(fs_reg reg, unsigned delta)
+{
+ switch (reg.file) {
+ case BAD_FILE:
+ case UNIFORM:
+ case IMM:
+ /* These only have a single component that is implicitly splatted. A
+ * horizontal offset should be a harmless no-op.
+ */
+ break;
+ case GRF:
+ case MRF:
+ return byte_offset(reg, delta * reg.stride * type_sz(reg.type));
+ default:
+ assert(delta == 0);
+ }
+ return reg;
+}
+
static inline fs_reg
offset(fs_reg reg, unsigned delta)
{
return reg;
}
+static inline fs_reg
+component(fs_reg reg, unsigned idx)
+{
+ assert(reg.subreg_offset == 0);
+ assert(idx < reg.width);
+ reg.subreg_offset = idx * type_sz(reg.type);
+ reg.width = 1;
+ return reg;
+}
+
/**
* Get either of the 8-component halves of a 16-component register.
*
assert(idx == 0 || (reg.file != HW_REG && reg.file != IMM));
assert(reg.width == 16);
reg.width = 8;
- return byte_offset(reg, 8 * idx * reg.stride * type_sz(reg.type));
+ return horiz_offset(reg, 8 * idx);
}
static const fs_reg reg_undef;
-class ip_record : public exec_node {
-public:
- DECLARE_RALLOC_CXX_OPERATORS(ip_record)
-
- ip_record(int ip)
- {
- this->ip = ip;
- }
-
- int ip;
-};
-
class fs_inst : public backend_instruction {
fs_inst &operator=(const fs_inst &);
+ void init(enum opcode opcode, uint8_t exec_width, const fs_reg &dst,
+ fs_reg *src, int sources);
+
public:
DECLARE_RALLOC_CXX_OPERATORS(fs_inst)
- void init(enum opcode opcode, const fs_reg &dst, fs_reg *src, int sources);
-
- fs_inst(enum opcode opcode = BRW_OPCODE_NOP, const fs_reg &dst = reg_undef);
+ fs_inst();
+ fs_inst(enum opcode opcode, uint8_t exec_size);
+ fs_inst(enum opcode opcode, const fs_reg &dst);
+ fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
+ const fs_reg &src0);
fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0);
+ fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
+ const fs_reg &src0, const fs_reg &src1);
fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
const fs_reg &src1);
+ fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
+ const fs_reg &src0, const fs_reg &src1, const fs_reg &src2);
fs_inst(enum opcode opcode, const fs_reg &dst, const fs_reg &src0,
const fs_reg &src1, const fs_reg &src2);
fs_inst(enum opcode opcode, const fs_reg &dst, fs_reg src[], int sources);
+ fs_inst(enum opcode opcode, uint8_t exec_size, const fs_reg &dst,
+ fs_reg src[], int sources);
fs_inst(const fs_inst &that);
void resize_sources(uint8_t num_sources);
uint8_t sources; /**< Number of fs_reg sources. */
+ /**
+ * Execution size of the instruction. This is used by the generator to
+ * generate the correct binary for the given fs_inst. Current valid
+ * values are 1, 8, 16.
+ */
+ uint8_t exec_size;
+
/* Chooses which flag subregister (f0.0 or f0.1) is used for conditional
* mod and predication.
*/
uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
bool eot:1;
- bool header_present:1;
- bool shadow_compare:1;
bool force_uncompressed:1;
bool force_sechalf:1;
bool pi_noperspective:1; /**< Pixel interpolator noperspective flag */
void visit(ir_emit_vertex *);
void visit(ir_end_primitive *);
- uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
- void swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler);
+ uint32_t gather_channel(int orig_chan, uint32_t sampler);
+ void swizzle_result(ir_texture_opcode op, int dest_components,
+ fs_reg orig_val, uint32_t sampler);
fs_inst *emit(fs_inst *inst);
void emit(exec_list list);
uint32_t const_offset);
bool run();
+ void optimize();
+ void allocate_registers();
void assign_binding_table_offsets();
void setup_payload_gen4();
void setup_payload_gen6();
void lower_uniform_pull_constant_loads();
bool lower_load_payload();
- void push_force_uncompressed();
- void pop_force_uncompressed();
-
void emit_dummy_fs();
void emit_repclear_shader();
fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
bool is_centroid, bool is_sample);
fs_reg *emit_frontfacing_interpolation();
fs_reg *emit_samplepos_setup();
- fs_reg *emit_sampleid_setup(ir_variable *ir);
+ fs_reg *emit_sampleid_setup();
fs_reg *emit_general_interpolation(ir_variable *ir);
void emit_interpolation_setup_gen4();
void emit_interpolation_setup_gen6();
void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
- fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
+ fs_reg rescale_texcoord(fs_reg coordinate, const glsl_type *coord_type,
bool is_rect, uint32_t sampler, int texunit);
- fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
+ fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_comp,
+ fs_reg lod, fs_reg lod2, int grad_components,
uint32_t sampler);
- fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
- fs_reg sample_index, uint32_t sampler);
- fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
- fs_reg sample_index, fs_reg mcs, fs_reg sampler);
- fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler);
+ fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_comp,
+ fs_reg lod, fs_reg lod2, int grad_components,
+ fs_reg sample_index, uint32_t sampler,
+ bool has_offset);
+ fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_comp,
+ fs_reg lod, fs_reg lod2, int grad_components,
+ fs_reg sample_index, fs_reg mcs, fs_reg sampler,
+ fs_reg offset_value);
+ void emit_texture(ir_texture_opcode op,
+ const glsl_type *dest_type,
+ fs_reg coordinate, const struct glsl_type *coord_type,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg dpdy, int grad_components,
+ fs_reg sample_index,
+ fs_reg offset, unsigned offset_components,
+ fs_reg mcs,
+ int gather_component,
+ bool is_cube_array,
+ bool is_rect,
+ uint32_t sampler,
+ fs_reg sampler_reg,
+ int texunit);
+ fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
fs_reg fix_math_operand(fs_reg src);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
const struct prog_instruction *fpi,
fs_reg dst, fs_reg src0, fs_reg src1, fs_reg one);
- void emit_color_write(fs_reg color, int index, int first_color_mrf);
+ int setup_color_payload(fs_reg *dst, fs_reg color, unsigned components);
void emit_alpha_test();
fs_inst *emit_single_fb_write(fs_reg color1, fs_reg color2,
fs_reg src0_alpha, unsigned components);
bool spilled_any_registers;
const unsigned dispatch_width; /**< 8 or 16 */
-
- int force_uncompressed_stack;
};
/**
bool debug_flag);
~fs_generator();
- const unsigned *generate_assembly(const cfg_t *simd8_cfg,
- const cfg_t *simd16_cfg,
- unsigned *assembly_size);
+ int generate_code(const cfg_t *cfg, int dispatch_width);
+ const unsigned *get_assembly(unsigned int *assembly_size);
private:
- void generate_code(const cfg_t *cfg);
void fire_fb_write(fs_inst *inst,
- GLuint base_reg,
+ struct brw_reg payload,
struct brw_reg implied_header,
GLuint nr);
- void generate_fb_write(fs_inst *inst);
+ void generate_fb_write(fs_inst *inst, struct brw_reg payload);
void generate_blorp_fb_write(fs_inst *inst);
- void generate_rep_fb_write(fs_inst *inst);
void generate_pixel_xy(struct brw_reg dst, bool is_x);
void generate_linterp(fs_inst *inst, struct brw_reg dst,
struct brw_reg *src);
void generate_untyped_atomic(fs_inst *inst,
struct brw_reg dst,
+ struct brw_reg payload,
struct brw_reg atomic_op,
struct brw_reg surf_index);
void generate_untyped_surface_read(fs_inst *inst,
struct brw_reg dst,
+ struct brw_reg payload,
struct brw_reg surf_index);
bool patch_discard_jumps_to_fb_writes();
bool brw_do_channel_expressions(struct exec_list *instructions);
bool brw_do_vector_splitting(struct exec_list *instructions);
-bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);
projects / mesa.git / blobdiff