i965: Make precompile functions accessible from C.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs.h

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h
index 943e6387b8eae55794ca4390cf224a491a7149dc..ee612079f2a8860e18b8fbb52219e69d1470d301 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -83,10 +83,8 @@ public:
    fs_reg(fs_visitor *v, const struct glsl_type *type);
 
    bool equals(const fs_reg &r) const;
-   bool is_valid_3src() const;
    bool is_contiguous() const;
 
-   fs_reg &apply_stride(unsigned stride);
    /** Smear a channel of the reg to all channels. */
    fs_reg &set_smear(unsigned subreg);
 
@@ -210,18 +208,6 @@ half(fs_reg reg, unsigned idx)
 
 static const fs_reg reg_undef;
 
-class ip_record : public exec_node {
-public:
-   DECLARE_RALLOC_CXX_OPERATORS(ip_record)
-
-   ip_record(int ip)
-   {
-      this->ip = ip;
-   }
-
-   int ip;
-};
-
 class fs_inst : public backend_instruction {
    fs_inst &operator=(const fs_inst &);
 
@@ -281,8 +267,6 @@ public:
 
    uint8_t regs_written; /**< Number of vgrfs written by a SEND message, or 1 */
    bool eot:1;
-   bool header_present:1;
-   bool shadow_compare:1;
    bool force_uncompressed:1;
    bool force_sechalf:1;
    bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
@@ -334,8 +318,9 @@ public:
    void visit(ir_emit_vertex *);
    void visit(ir_end_primitive *);
 
-   uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
-   void swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler);
+   uint32_t gather_channel(int orig_chan, uint32_t sampler);
+   void swizzle_result(ir_texture_opcode op, int dest_components,
+                       fs_reg orig_val, uint32_t sampler);
 
    fs_inst *emit(fs_inst *inst);
    void emit(exec_list list);
@@ -402,6 +387,8 @@ public:
                                         uint32_t const_offset);
 
    bool run();
+   void optimize();
+   void allocate_registers();
    void assign_binding_table_offsets();
    void setup_payload_gen4();
    void setup_payload_gen6();
@@ -452,9 +439,6 @@ public:
    void lower_uniform_pull_constant_loads();
    bool lower_load_payload();
 
-   void push_force_uncompressed();
-   void pop_force_uncompressed();
-
    void emit_dummy_fs();
    void emit_repclear_shader();
    fs_reg *emit_fragcoord_interpolation(ir_variable *ir);
@@ -463,23 +447,45 @@ public:
                          bool is_centroid, bool is_sample);
    fs_reg *emit_frontfacing_interpolation();
    fs_reg *emit_samplepos_setup();
-   fs_reg *emit_sampleid_setup(ir_variable *ir);
+   fs_reg *emit_sampleid_setup();
    fs_reg *emit_general_interpolation(ir_variable *ir);
    void emit_interpolation_setup_gen4();
    void emit_interpolation_setup_gen6();
    void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
-   fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
+   fs_reg rescale_texcoord(fs_reg coordinate, const glsl_type *coord_type,
                            bool is_rect, uint32_t sampler, int texunit);
-   fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
-                              fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
+   fs_inst *emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
+                              fs_reg coordinate, int coord_components,
+                              fs_reg shadow_comp,
+                              fs_reg lod, fs_reg lod2, int grad_components,
                               uint32_t sampler);
-   fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
-                              fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
-                              fs_reg sample_index, uint32_t sampler);
-   fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
-                              fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
-                              fs_reg sample_index, fs_reg mcs, fs_reg sampler);
-   fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler);
+   fs_inst *emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
+                              fs_reg coordinate, int coord_components,
+                              fs_reg shadow_comp,
+                              fs_reg lod, fs_reg lod2, int grad_components,
+                              fs_reg sample_index, uint32_t sampler,
+                              bool has_offset);
+   fs_inst *emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
+                              fs_reg coordinate, int coord_components,
+                              fs_reg shadow_comp,
+                              fs_reg lod, fs_reg lod2, int grad_components,
+                              fs_reg sample_index, fs_reg mcs, fs_reg sampler,
+                              fs_reg offset_value);
+   void emit_texture(ir_texture_opcode op,
+                     const glsl_type *dest_type,
+                     fs_reg coordinate, const struct glsl_type *coord_type,
+                     fs_reg shadow_c,
+                     fs_reg lod, fs_reg dpdy, int grad_components,
+                     fs_reg sample_index,
+                     fs_reg offset, unsigned offset_components,
+                     fs_reg mcs,
+                     int gather_component,
+                     bool is_cube_array,
+                     bool is_rect,
+                     uint32_t sampler,
+                     fs_reg sampler_reg,
+                     int texunit);
+   fs_reg emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler);
    void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
    fs_reg fix_math_operand(fs_reg src);
    fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
@@ -657,8 +663,6 @@ public:
    bool spilled_any_registers;
 
    const unsigned dispatch_width; /**< 8 or 16 */
-
-   int force_uncompressed_stack;
 };
 
 /**
@@ -679,12 +683,10 @@ public:
                 bool debug_flag);
    ~fs_generator();
 
-   const unsigned *generate_assembly(const cfg_t *simd8_cfg,
-                                     const cfg_t *simd16_cfg,
-                                     unsigned *assembly_size);
+   int generate_code(const cfg_t *cfg, int dispatch_width);
+   const unsigned *get_assembly(unsigned int *assembly_size);
 
 private:
-   void generate_code(const cfg_t *cfg);
    void fire_fb_write(fs_inst *inst,
                       struct brw_reg payload,
                       struct brw_reg implied_header,
@@ -795,6 +797,5 @@ private:
 
 bool brw_do_channel_expressions(struct exec_list *instructions);
 bool brw_do_vector_splitting(struct exec_list *instructions);
-bool brw_fs_precompile(struct gl_context *ctx, struct gl_shader_program *prog);
 
 struct brw_reg brw_reg_from_fs_reg(fs_reg *reg);