#define ACP_HASH_SIZE 16
-#include "main/bitset.h"
+#include "util/bitset.h"
#include "brw_fs.h"
#include "brw_cfg.h"
struct acp_entry : public exec_node {
fs_reg dst;
fs_reg src;
+ uint8_t regs_written;
enum opcode opcode;
bool saturate;
};
opcode == BRW_OPCODE_NOT);
}
+static bool
+can_change_source_types(fs_inst *inst)
+{
+ return !inst->src[0].abs && !inst->src[0].negate &&
+ (inst->opcode == BRW_OPCODE_MOV ||
+ (inst->opcode == BRW_OPCODE_SEL &&
+ inst->predicate != BRW_PREDICATE_NONE &&
+ !inst->src[1].abs && !inst->src[1].negate));
+}
+
bool
fs_visitor::try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry)
{
+ if (inst->src[arg].file != GRF)
+ return false;
+
if (entry->src.file == IMM)
return false;
+ assert(entry->src.file == GRF || entry->src.file == UNIFORM ||
+ entry->src.file == ATTR);
if (entry->opcode == SHADER_OPCODE_LOAD_PAYLOAD &&
inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD)
return false;
- /* Bail if inst is reading more than entry is writing. */
- if ((inst->regs_read(this, arg) * inst->src[arg].stride *
- type_sz(inst->src[arg].type)) > type_sz(entry->dst.type))
+ assert(entry->dst.file == GRF);
+ if (inst->src[arg].reg != entry->dst.reg)
return false;
- if (inst->src[arg].file != entry->dst.file ||
- inst->src[arg].reg != entry->dst.reg ||
- inst->src[arg].reg_offset != entry->dst.reg_offset ||
- inst->src[arg].subreg_offset != entry->dst.subreg_offset) {
+ /* Bail if inst is reading a range that isn't contained in the range
+ * that entry is writing.
+ */
+ if (inst->src[arg].reg_offset < entry->dst.reg_offset ||
+ (inst->src[arg].reg_offset * 32 + inst->src[arg].subreg_offset +
+ inst->regs_read(arg) * inst->src[arg].stride * 32) >
+ (entry->dst.reg_offset + entry->regs_written) * 32)
return false;
- }
- /* See resolve_ud_negate() and comment in brw_fs_emit.cpp. */
- if (inst->conditional_mod &&
- inst->src[arg].type == BRW_REGISTER_TYPE_UD &&
+ /* we can't generally copy-propagate UD negations because we
+ * can end up accessing the resulting values as signed integers
+ * instead. See also resolve_ud_negate() and comment in
+ * fs_generator::generate_code.
+ */
+ if (entry->src.type == BRW_REGISTER_TYPE_UD &&
entry->src.negate)
return false;
if ((has_source_modifiers || entry->src.file == UNIFORM ||
!entry->src.is_contiguous()) &&
- !inst->can_do_source_mods(brw))
+ !inst->can_do_source_mods(devinfo))
return false;
if (has_source_modifiers &&
if (entry->src.stride * inst->src[arg].stride > 4)
return false;
+ /* Bail if the instruction type is larger than the execution type of the
+ * copy, what implies that each channel is reading multiple channels of the
+ * destination of the copy, and simply replacing the sources would give a
+ * program with different semantics.
+ */
+ if (type_sz(entry->dst.type) < type_sz(inst->src[arg].type))
+ return false;
+
/* Bail if the result of composing both strides cannot be expressed
* as another stride. This avoids, for example, trying to transform
* this:
type_sz(inst->src[arg].type)) % type_sz(entry->src.type) != 0)
return false;
- if (has_source_modifiers && entry->dst.type != inst->src[arg].type)
+ if (has_source_modifiers &&
+ entry->dst.type != inst->src[arg].type &&
+ !can_change_source_types(inst))
return false;
- if (brw->gen >= 8 && (entry->src.negate || entry->src.abs) &&
+ if (devinfo->gen >= 8 && (entry->src.negate || entry->src.abs) &&
is_logic_op(inst->opcode)) {
return false;
}
inst->src[arg].file = entry->src.file;
inst->src[arg].reg = entry->src.reg;
- inst->src[arg].reg_offset = entry->src.reg_offset;
- inst->src[arg].subreg_offset = entry->src.subreg_offset;
inst->src[arg].stride *= entry->src.stride;
inst->saturate = inst->saturate || entry->saturate;
- if (!inst->src[arg].abs) {
- inst->src[arg].abs = entry->src.abs;
- inst->src[arg].negate ^= entry->src.negate;
+ switch (entry->src.file) {
+ case UNIFORM:
+ case BAD_FILE:
+ case HW_REG:
+ inst->src[arg].reg_offset = entry->src.reg_offset;
+ inst->src[arg].subreg_offset = entry->src.subreg_offset;
+ break;
+ case ATTR:
+ case GRF:
+ {
+ /* In this case, we'll just leave the width alone. The source
+ * register could have different widths depending on how it is
+ * being used. For instance, if only half of the register was
+ * used then we want to preserve that and continue to only use
+ * half.
+ *
+ * Also, we have to deal with mapping parts of vgrfs to other
+ * parts of vgrfs so we have to do some reg_offset magic.
+ */
+
+ /* Compute the offset of inst->src[arg] relative to inst->dst */
+ assert(entry->dst.subreg_offset == 0);
+ int rel_offset = inst->src[arg].reg_offset - entry->dst.reg_offset;
+ int rel_suboffset = inst->src[arg].subreg_offset;
+
+ /* Compute the final register offset (in bytes) */
+ int offset = entry->src.reg_offset * 32 + entry->src.subreg_offset;
+ offset += rel_offset * 32 + rel_suboffset;
+ inst->src[arg].reg_offset = offset / 32;
+ inst->src[arg].subreg_offset = offset % 32;
+ }
+ break;
+ default:
+ unreachable("Invalid register file");
+ break;
+ }
+
+ if (has_source_modifiers) {
+ if (entry->dst.type != inst->src[arg].type) {
+ /* We are propagating source modifiers from a MOV with a different
+ * type. If we got here, then we can just change the source and
+ * destination types of the instruction and keep going.
+ */
+ assert(can_change_source_types(inst));
+ for (int i = 0; i < inst->sources; i++) {
+ inst->src[i].type = entry->dst.type;
+ }
+ inst->dst.type = entry->dst.type;
+ }
+
+ if (!inst->src[arg].abs) {
+ inst->src[arg].abs = entry->src.abs;
+ inst->src[arg].negate ^= entry->src.negate;
+ }
}
return true;
}
-static bool
-try_constant_propagate(struct brw_context *brw, fs_inst *inst,
- acp_entry *entry)
+bool
+fs_visitor::try_constant_propagate(fs_inst *inst, acp_entry *entry)
{
bool progress = false;
if (entry->src.file != IMM)
return false;
+ if (entry->saturate)
+ return false;
for (int i = inst->sources - 1; i >= 0; i--) {
- if (inst->src[i].file != entry->dst.file ||
- inst->src[i].reg != entry->dst.reg ||
- inst->src[i].reg_offset != entry->dst.reg_offset ||
- inst->src[i].subreg_offset != entry->dst.subreg_offset ||
- inst->src[i].type != entry->dst.type ||
- inst->src[i].stride > 1)
+ if (inst->src[i].file != GRF)
+ continue;
+
+ assert(entry->dst.file == GRF);
+ if (inst->src[i].reg != entry->dst.reg)
continue;
- /* Don't bother with cases that should have been taken care of by the
- * GLSL compiler's constant folding pass.
+ /* Bail if inst is reading a range that isn't contained in the range
+ * that entry is writing.
*/
- if (inst->src[i].negate || inst->src[i].abs)
+ if (inst->src[i].reg_offset < entry->dst.reg_offset ||
+ (inst->src[i].reg_offset * 32 + inst->src[i].subreg_offset +
+ inst->regs_read(i) * inst->src[i].stride * 32) >
+ (entry->dst.reg_offset + entry->regs_written) * 32)
continue;
+ fs_reg val = entry->src;
+ val.type = inst->src[i].type;
+
+ if (inst->src[i].abs) {
+ if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
+ !brw_abs_immediate(val.type, &val.fixed_hw_reg)) {
+ continue;
+ }
+ }
+
+ if (inst->src[i].negate) {
+ if ((devinfo->gen >= 8 && is_logic_op(inst->opcode)) ||
+ !brw_negate_immediate(val.type, &val.fixed_hw_reg)) {
+ continue;
+ }
+ }
+
switch (inst->opcode) {
case BRW_OPCODE_MOV:
- inst->src[i] = entry->src;
+ case SHADER_OPCODE_LOAD_PAYLOAD:
+ inst->src[i] = val;
progress = true;
break;
- case SHADER_OPCODE_POW:
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
- if (brw->gen < 8)
+ /* FINISHME: Promote non-float constants and remove this. */
+ if (devinfo->gen < 8)
+ break;
+ /* fallthrough */
+ case SHADER_OPCODE_POW:
+ /* Allow constant propagation into src1 (except on Gen 6), and let
+ * constant combining promote the constant on Gen < 8.
+ *
+ * While Gen 6 MATH can take a scalar source, its source and
+ * destination offsets must be equal and we cannot ensure that.
+ */
+ if (devinfo->gen == 6)
break;
/* fallthrough */
case BRW_OPCODE_BFI1:
case BRW_OPCODE_SHR:
case BRW_OPCODE_SUBB:
if (i == 1) {
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
}
break;
case BRW_OPCODE_MACH:
case BRW_OPCODE_MUL:
+ case SHADER_OPCODE_MULH:
case BRW_OPCODE_ADD:
case BRW_OPCODE_OR:
case BRW_OPCODE_AND:
case BRW_OPCODE_XOR:
case BRW_OPCODE_ADDC:
if (i == 1) {
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
} else if (i == 0 && inst->src[1].file != IMM) {
/* Fit this constant in by commuting the operands.
* Exception: we can't do this for 32-bit integer MUL/MACH
* because it's asymmetric.
+ *
+ * The BSpec says for Broadwell that
+ *
+ * "When multiplying DW x DW, the dst cannot be accumulator."
+ *
+ * Integer MUL with a non-accumulator destination will be lowered
+ * by lower_integer_multiplication(), so don't restrict it.
*/
- if ((inst->opcode == BRW_OPCODE_MUL ||
+ if (((inst->opcode == BRW_OPCODE_MUL &&
+ inst->dst.is_accumulator()) ||
inst->opcode == BRW_OPCODE_MACH) &&
(inst->src[1].type == BRW_REGISTER_TYPE_D ||
inst->src[1].type == BRW_REGISTER_TYPE_UD))
break;
inst->src[0] = inst->src[1];
- inst->src[1] = entry->src;
+ inst->src[1] = val;
progress = true;
}
break;
case BRW_OPCODE_CMP:
case BRW_OPCODE_IF:
if (i == 1) {
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
} else if (i == 0 && inst->src[1].file != IMM) {
enum brw_conditional_mod new_cmod;
* flipping the test
*/
inst->src[0] = inst->src[1];
- inst->src[1] = entry->src;
+ inst->src[1] = val;
inst->conditional_mod = new_cmod;
progress = true;
}
case BRW_OPCODE_SEL:
if (i == 1) {
- inst->src[i] = entry->src;
+ inst->src[i] = val;
progress = true;
} else if (i == 0 && inst->src[1].file != IMM) {
inst->src[0] = inst->src[1];
- inst->src[1] = entry->src;
+ inst->src[1] = val;
/* If this was predicated, flipping operands means
* we also need to flip the predicate.
assert(i == 0);
if (inst->src[0].fixed_hw_reg.dw1.f != 0.0f) {
inst->opcode = BRW_OPCODE_MOV;
- inst->src[0] = entry->src;
+ inst->src[0] = val;
inst->src[0].fixed_hw_reg.dw1.f = 1.0f / inst->src[0].fixed_hw_reg.dw1.f;
progress = true;
}
break;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
- inst->src[i] = entry->src;
+ case SHADER_OPCODE_BROADCAST:
+ inst->src[i] = val;
+ progress = true;
+ break;
+
+ case BRW_OPCODE_MAD:
+ case BRW_OPCODE_LRP:
+ inst->src[i] = val;
progress = true;
break;
((inst->src[0].file == GRF &&
(inst->src[0].reg != inst->dst.reg ||
inst->src[0].reg_offset != inst->dst.reg_offset)) ||
+ inst->src[0].file == ATTR ||
inst->src[0].file == UNIFORM ||
inst->src[0].file == IMM) &&
inst->src[0].type == inst->dst.type &&
continue;
foreach_in_list(acp_entry, entry, &acp[inst->src[i].reg % ACP_HASH_SIZE]) {
- if (try_constant_propagate(brw, inst, entry))
+ if (try_constant_propagate(inst, entry))
progress = true;
if (try_copy_propagate(inst, i, entry))
acp_entry *entry = ralloc(copy_prop_ctx, acp_entry);
entry->dst = inst->dst;
entry->src = inst->src[0];
+ entry->regs_written = inst->regs_written;
entry->opcode = inst->opcode;
entry->saturate = inst->saturate;
acp[entry->dst.reg % ACP_HASH_SIZE].push_tail(entry);
} else if (inst->opcode == SHADER_OPCODE_LOAD_PAYLOAD &&
inst->dst.file == GRF) {
+ int offset = 0;
for (int i = 0; i < inst->sources; i++) {
+ int effective_width = i < inst->header_size ? 8 : inst->exec_size;
+ int regs_written = effective_width / 8;
if (inst->src[i].file == GRF) {
acp_entry *entry = ralloc(copy_prop_ctx, acp_entry);
entry->dst = inst->dst;
- entry->dst.reg_offset = i;
+ entry->dst.reg_offset = offset;
entry->src = inst->src[i];
+ entry->regs_written = regs_written;
entry->opcode = inst->opcode;
if (!entry->dst.equals(inst->src[i])) {
acp[entry->dst.reg % ACP_HASH_SIZE].push_tail(entry);
ralloc_free(entry);
}
}
+ offset += regs_written;
}
}
}
projects / mesa.git / blobdiff