#include "brw_context.h"
#include "brw_fs.h"
-static fs_reg
-regoffset(fs_reg reg, int i)
-{
- reg.reg_offset += i;
- return reg;
-}
-
void
fs_visitor::emit_fp_alu1(enum opcode opcode,
const struct prog_instruction *fpi,
{
for (int i = 0; i < 4; i++) {
if (fpi->DstReg.WriteMask & (1 << i))
- emit(opcode, regoffset(dst, i), regoffset(src, i));
+ emit(opcode, offset(dst, i), offset(src, i));
}
}
{
for (int i = 0; i < 4; i++) {
if (fpi->DstReg.WriteMask & (1 << i))
- emit(opcode, regoffset(dst, i),
- regoffset(src0, i), regoffset(src1, i));
+ emit(opcode, offset(dst, i),
+ offset(src0, i), offset(src1, i));
}
}
fs_visitor::emit_fp_minmax(const prog_instruction *fpi,
fs_reg dst, fs_reg src0, fs_reg src1)
{
- uint32_t conditionalmod;
+ enum brw_conditional_mod conditionalmod;
if (fpi->Opcode == OPCODE_MIN)
conditionalmod = BRW_CONDITIONAL_L;
else
for (int i = 0; i < 4; i++) {
if (fpi->DstReg.WriteMask & (1 << i)) {
- emit_minmax(conditionalmod, regoffset(dst, i),
- regoffset(src0, i), regoffset(src1, i));
+ emit_minmax(conditionalmod, offset(dst, i),
+ offset(src0, i), offset(src1, i));
}
}
}
void
-fs_visitor::emit_fp_sop(uint32_t conditional_mod,
+fs_visitor::emit_fp_sop(enum brw_conditional_mod conditional_mod,
const struct prog_instruction *fpi,
fs_reg dst, fs_reg src0, fs_reg src1,
fs_reg one)
if (fpi->DstReg.WriteMask & (1 << i)) {
fs_inst *inst;
- emit(CMP(reg_null_d, regoffset(src0, i), regoffset(src1, i),
+ emit(CMP(reg_null_d, offset(src0, i), offset(src1, i),
conditional_mod));
- inst = emit(BRW_OPCODE_SEL, regoffset(dst, i), one, fs_reg(0.0f));
+ inst = emit(BRW_OPCODE_SEL, offset(dst, i), one, fs_reg(0.0f));
inst->predicate = BRW_PREDICATE_NORMAL;
}
}
{
for (int i = 0; i < 4; i++) {
if (fpi->DstReg.WriteMask & (1 << i))
- emit(MOV(regoffset(dst, i), src));
+ emit(MOV(offset(dst, i), src));
}
}
fs_reg one = fs_reg(this, glsl_type::float_type);
emit(MOV(one, fs_reg(1.0f)));
- for (unsigned int insn = 0; insn < fp->Base.NumInstructions; insn++) {
- const struct prog_instruction *fpi = &fp->Base.Instructions[insn];
+ for (unsigned int insn = 0; insn < prog->NumInstructions; insn++) {
+ const struct prog_instruction *fpi = &prog->Instructions[insn];
base_ir = fpi;
//_mesa_print_instruction(fpi);
if (fpi->DstReg.WriteMask & (1 << i)) {
fs_inst *inst;
- emit(CMP(null, regoffset(src[0], i), fs_reg(0.0f),
+ emit(CMP(null, offset(src[0], i), fs_reg(0.0f),
BRW_CONDITIONAL_L));
- inst = emit(BRW_OPCODE_SEL, regoffset(dst, i),
- regoffset(src[1], i), regoffset(src[2], i));
+ inst = emit(BRW_OPCODE_SEL, offset(dst, i),
+ offset(src[1], i), offset(src[2], i));
inst->predicate = BRW_PREDICATE_NORMAL;
}
}
case OPCODE_DP3: count = 3; break;
case OPCODE_DP4: count = 4; break;
case OPCODE_DPH: count = 3; break;
- default: assert(!"not reached"); count = 0; break;
+ default: unreachable("not reached");
}
- emit(MUL(acc, regoffset(src[0], 0), regoffset(src[1], 0)));
+ emit(MUL(acc, offset(src[0], 0), offset(src[1], 0)));
for (int i = 1; i < count; i++) {
- emit(MUL(mul, regoffset(src[0], i), regoffset(src[1], i)));
+ emit(MUL(mul, offset(src[0], i), offset(src[1], i)));
emit(ADD(acc, acc, mul));
}
if (fpi->Opcode == OPCODE_DPH)
- emit(ADD(acc, acc, regoffset(src[1], 3)));
+ emit(ADD(acc, acc, offset(src[1], 3)));
emit_fp_scalar_write(fpi, dst, acc);
break;
if (fpi->DstReg.WriteMask & WRITEMASK_X)
emit(MOV(dst, fs_reg(1.0f)));
if (fpi->DstReg.WriteMask & WRITEMASK_Y) {
- emit(MUL(regoffset(dst, 1),
- regoffset(src[0], 1), regoffset(src[1], 1)));
+ emit(MUL(offset(dst, 1),
+ offset(src[0], 1), offset(src[1], 1)));
}
if (fpi->DstReg.WriteMask & WRITEMASK_Z)
- emit(MOV(regoffset(dst, 2), regoffset(src[0], 2)));
+ emit(MOV(offset(dst, 2), offset(src[0], 2)));
if (fpi->DstReg.WriteMask & WRITEMASK_W)
- emit(MOV(regoffset(dst, 3), regoffset(src[1], 3)));
+ emit(MOV(offset(dst, 3), offset(src[1], 3)));
break;
case OPCODE_EX2:
continue;
}
- emit(CMP(null, regoffset(src[0], i), fs_reg(0.0f),
- BRW_CONDITIONAL_L));
- if (intel->gen < 6 && dispatch_width == 16)
- fail("Can't support (non-uniform) control flow on 16-wide");
- emit(IF(BRW_PREDICATE_NORMAL));
- emit(FS_OPCODE_DISCARD);
- emit(BRW_OPCODE_ENDIF);
+ /* Emit an instruction that's predicated on the current
+ * undiscarded pixels, and updates just those pixels to be
+ * turned off.
+ */
+ fs_inst *cmp = emit(CMP(null, offset(src[0], i), fs_reg(0.0f),
+ BRW_CONDITIONAL_GE));
+ cmp->predicate = BRW_PREDICATE_NORMAL;
+ cmp->flag_subreg = 1;
}
break;
}
* brw_wm_emit.c either.
*/
if (fpi->DstReg.WriteMask & WRITEMASK_X)
- emit(MOV(regoffset(dst, 0), fs_reg(1.0f)));
+ emit(MOV(offset(dst, 0), fs_reg(1.0f)));
if (fpi->DstReg.WriteMask & WRITEMASK_YZ) {
fs_inst *inst;
- emit(CMP(null, regoffset(src[0], 0), fs_reg(0.0f),
+ emit(CMP(null, offset(src[0], 0), fs_reg(0.0f),
BRW_CONDITIONAL_LE));
if (fpi->DstReg.WriteMask & WRITEMASK_Y) {
- emit(MOV(regoffset(dst, 1), regoffset(src[0], 0)));
- inst = emit(MOV(regoffset(dst, 1), fs_reg(0.0f)));
+ emit(MOV(offset(dst, 1), offset(src[0], 0)));
+ inst = emit(MOV(offset(dst, 1), fs_reg(0.0f)));
inst->predicate = BRW_PREDICATE_NORMAL;
}
if (fpi->DstReg.WriteMask & WRITEMASK_Z) {
- emit_math(SHADER_OPCODE_POW, regoffset(dst, 2),
- regoffset(src[0], 1), regoffset(src[0], 3));
+ emit_math(SHADER_OPCODE_POW, offset(dst, 2),
+ offset(src[0], 1), offset(src[0], 3));
- inst = emit(MOV(regoffset(dst, 2), fs_reg(0.0f)));
+ inst = emit(MOV(offset(dst, 2), fs_reg(0.0f)));
inst->predicate = BRW_PREDICATE_NORMAL;
}
}
if (fpi->DstReg.WriteMask & WRITEMASK_W)
- emit(MOV(regoffset(dst, 3), fs_reg(1.0f)));
+ emit(MOV(offset(dst, 3), fs_reg(1.0f)));
break;
case OPCODE_LRP:
for (int i = 0; i < 4; i++) {
if (fpi->DstReg.WriteMask & (1 << i)) {
- fs_reg neg_src0 = regoffset(src[0], i);
- neg_src0.negate = !neg_src0.negate;
- fs_reg temp = fs_reg(this, glsl_type::float_type);
- fs_reg temp2 = fs_reg(this, glsl_type::float_type);
- emit(ADD(temp, neg_src0, fs_reg(1.0f)));
- emit(MUL(temp, temp, regoffset(src[2], i)));
- emit(MUL(temp2, regoffset(src[0], i), regoffset(src[1], i)));
- emit(ADD(regoffset(dst, i), temp, temp2));
+ fs_reg a = offset(src[0], i);
+ fs_reg y = offset(src[1], i);
+ fs_reg x = offset(src[2], i);
+ emit_lrp(offset(dst, i), x, y, a);
}
}
break;
for (int i = 0; i < 4; i++) {
if (fpi->DstReg.WriteMask & (1 << i)) {
fs_reg temp = fs_reg(this, glsl_type::float_type);
- emit(MUL(temp, regoffset(src[0], i), regoffset(src[1], i)));
- emit(ADD(regoffset(dst, i), temp, regoffset(src[2], i)));
+ emit(MUL(temp, offset(src[0], i), offset(src[1], i)));
+ emit(ADD(offset(dst, i), temp, offset(src[2], i)));
}
}
break;
case OPCODE_SCS:
if (fpi->DstReg.WriteMask & WRITEMASK_X) {
- emit_math(SHADER_OPCODE_COS, regoffset(dst, 0),
- regoffset(src[0], 0));
+ emit_math(SHADER_OPCODE_COS, offset(dst, 0),
+ offset(src[0], 0));
}
if (fpi->DstReg.WriteMask & WRITEMASK_Y) {
- emit_math(SHADER_OPCODE_SIN, regoffset(dst, 1),
- regoffset(src[0], 1));
+ emit_math(SHADER_OPCODE_SIN, offset(dst, 1),
+ offset(src[0], 1));
}
break;
fs_reg dpdy;
fs_reg coordinate = src[0];
fs_reg shadow_c;
+ fs_reg sample_index;
switch (fpi->Opcode) {
case OPCODE_TEX:
coordinate = fs_reg(this, glsl_type::vec3_type);
fs_reg invproj = fs_reg(this, glsl_type::float_type);
- emit_math(SHADER_OPCODE_RCP, invproj, regoffset(src[0], 3));
+ emit_math(SHADER_OPCODE_RCP, invproj, offset(src[0], 3));
for (int i = 0; i < 3; i++) {
- emit(MUL(regoffset(coordinate, i),
- regoffset(src[0], i), invproj));
+ emit(MUL(offset(coordinate, i),
+ offset(src[0], i), invproj));
}
break;
}
case OPCODE_TXB:
ir = new(mem_ctx) ir_texture(ir_txb);
- lod = regoffset(src[0], 3);
+ lod = offset(src[0], 3);
break;
default:
- assert(!"not reached");
- break;
+ unreachable("not reached");
}
+ ir->type = glsl_type::vec4_type;
+
const glsl_type *coordinate_type;
switch (fpi->TexSrcTarget) {
case TEXTURE_1D_INDEX:
abscoord.negate = false;
abscoord.abs = true;
emit_minmax(BRW_CONDITIONAL_GE, temp,
- regoffset(abscoord, 0), regoffset(abscoord, 1));
+ offset(abscoord, 0), offset(abscoord, 1));
emit_minmax(BRW_CONDITIONAL_GE, temp,
- temp, regoffset(abscoord, 2));
+ temp, offset(abscoord, 2));
emit_math(SHADER_OPCODE_RCP, temp, temp);
for (int i = 0; i < 3; i++) {
- emit(MUL(regoffset(cubecoord, i),
- regoffset(coordinate, i), temp));
+ emit(MUL(offset(cubecoord, i),
+ offset(coordinate, i), temp));
}
coordinate = cubecoord;
}
default:
- assert(!"not reached");
- coordinate_type = glsl_type::vec2_type;
- break;
+ unreachable("not reached");
}
ir_constant_data junk_data;
ir->coordinate = new(mem_ctx) ir_constant(coordinate_type, &junk_data);
- coordinate = rescale_texcoord(ir, coordinate,
- fpi->TexSrcTarget == TEXTURE_RECT_INDEX,
- fpi->TexSrcUnit, fpi->TexSrcUnit);
-
if (fpi->TexShadow) {
- shadow_c = regoffset(coordinate, 2);
+ shadow_c = offset(coordinate, 2);
ir->shadow_comparitor = new(mem_ctx) ir_constant(0.0f);
}
+ coordinate = rescale_texcoord(ir, coordinate,
+ fpi->TexSrcTarget == TEXTURE_RECT_INDEX,
+ fpi->TexSrcUnit, fpi->TexSrcUnit);
+
fs_inst *inst;
- if (intel->gen >= 7) {
- inst = emit_texture_gen7(ir, dst, coordinate, shadow_c, lod, dpdy);
- } else if (intel->gen >= 5) {
- inst = emit_texture_gen5(ir, dst, coordinate, shadow_c, lod, dpdy);
+ if (brw->gen >= 7) {
+ inst = emit_texture_gen7(ir, dst, coordinate, shadow_c, lod, dpdy, sample_index, fs_reg(0u), fpi->TexSrcUnit);
+ } else if (brw->gen >= 5) {
+ inst = emit_texture_gen5(ir, dst, coordinate, shadow_c, lod, dpdy, sample_index, fpi->TexSrcUnit);
} else {
- inst = emit_texture_gen4(ir, dst, coordinate, shadow_c, lod, dpdy);
+ inst = emit_texture_gen4(ir, dst, coordinate, shadow_c, lod, dpdy, fpi->TexSrcUnit);
}
- inst->sampler = fpi->TexSrcUnit;
inst->shadow_compare = fpi->TexShadow;
/* Reuse the GLSL swizzle_result() handler. */
int i2 = (i + 2) % 3;
fs_reg temp = fs_reg(this, glsl_type::float_type);
- fs_reg neg_src1_1 = regoffset(src[1], i1);
+ fs_reg neg_src1_1 = offset(src[1], i1);
neg_src1_1.negate = !neg_src1_1.negate;
- emit(MUL(temp, regoffset(src[0], i2), neg_src1_1));
- emit(MUL(regoffset(dst, i),
- regoffset(src[0], i1), regoffset(src[1], i2)));
- emit(ADD(regoffset(dst, i), regoffset(dst, i), temp));
+ emit(MUL(temp, offset(src[0], i2), neg_src1_1));
+ emit(MUL(offset(dst, i),
+ offset(src[0], i1), offset(src[1], i2)));
+ emit(ADD(offset(dst, i), offset(dst, i), temp));
}
}
break;
for (int i = 0; i < 4; i++) {
if (fpi->DstReg.WriteMask & (1 << i)) {
- fs_inst *inst = emit(MOV(regoffset(real_dst, i),
- regoffset(dst, i)));
+ fs_inst *inst = emit(MOV(offset(real_dst, i),
+ offset(dst, i)));
inst->saturate = fpi->SaturateMode;
}
}
this->current_annotation = "result.depth write";
if (frag_depth.file != BAD_FILE) {
fs_reg temp = fs_reg(this, glsl_type::float_type);
- emit(MOV(temp, regoffset(frag_depth, 2)));
+ emit(MOV(temp, offset(frag_depth, 2)));
frag_depth = temp;
}
}
fs_visitor::setup_fp_regs()
{
/* PROGRAM_TEMPORARY */
- int num_temp = fp->Base.NumTemporaries;
+ int num_temp = prog->NumTemporaries;
fp_temp_regs = rzalloc_array(mem_ctx, fs_reg, num_temp);
for (int i = 0; i < num_temp; i++)
fp_temp_regs[i] = fs_reg(this, glsl_type::vec4_type);
/* PROGRAM_STATE_VAR etc. */
if (dispatch_width == 8) {
for (unsigned p = 0;
- p < fp->Base.Parameters->NumParameters; p++) {
+ p < prog->Parameters->NumParameters; p++) {
for (unsigned int i = 0; i < 4; i++) {
- this->param_index[c->prog_data.nr_params] = p;
- this->param_offset[c->prog_data.nr_params] = i;
- c->prog_data.nr_params++;
+ stage_prog_data->param[uniforms++] =
+ &prog->Parameters->ParameterValues[p][i];
}
}
}
- fp_input_regs = rzalloc_array(mem_ctx, fs_reg, FRAG_ATTRIB_MAX);
- for (int i = 0; i < FRAG_ATTRIB_MAX; i++) {
- if (fp->Base.InputsRead & BITFIELD64_BIT(i)) {
+ fp_input_regs = rzalloc_array(mem_ctx, fs_reg, VARYING_SLOT_MAX);
+ for (int i = 0; i < VARYING_SLOT_MAX; i++) {
+ if (prog->InputsRead & BITFIELD64_BIT(i)) {
/* Make up a dummy instruction to reuse code for emitting
* interpolation.
*/
ir_variable *ir = new(mem_ctx) ir_variable(glsl_type::vec4_type,
"fp_input",
- ir_var_in);
- ir->location = i;
+ ir_var_shader_in);
+ ir->data.location = i;
this->current_annotation = ralloc_asprintf(ctx, "interpolate input %d",
i);
switch (i) {
- case FRAG_ATTRIB_WPOS:
- ir->pixel_center_integer = fp->PixelCenterInteger;
- ir->origin_upper_left = fp->OriginUpperLeft;
+ case VARYING_SLOT_POS:
+ ir->data.pixel_center_integer = fp->PixelCenterInteger;
+ ir->data.origin_upper_left = fp->OriginUpperLeft;
fp_input_regs[i] = *emit_fragcoord_interpolation(ir);
break;
- case FRAG_ATTRIB_FACE:
+ case VARYING_SLOT_FACE:
fp_input_regs[i] = *emit_frontfacing_interpolation(ir);
break;
default:
fp_input_regs[i] = *emit_general_interpolation(ir);
- if (i == FRAG_ATTRIB_FOGC) {
- emit(MOV(regoffset(fp_input_regs[i], 1), fs_reg(0.0f)));
- emit(MOV(regoffset(fp_input_regs[i], 2), fs_reg(0.0f)));
- emit(MOV(regoffset(fp_input_regs[i], 3), fs_reg(1.0f)));
+ if (i == VARYING_SLOT_FOGC) {
+ emit(MOV(offset(fp_input_regs[i], 1), fs_reg(0.0f)));
+ emit(MOV(offset(fp_input_regs[i], 2), fs_reg(0.0f)));
+ emit(MOV(offset(fp_input_regs[i], 3), fs_reg(1.0f)));
}
break;
/* Tell emit_fb_writes() to smear fragment.color across all the
* color attachments.
*/
- for (int i = 1; i < c->key.nr_color_regions; i++) {
+ for (int i = 1; i < key->nr_color_regions; i++) {
outputs[i] = outputs[0];
output_components[i] = output_components[0];
}
fs_reg
fs_visitor::get_fp_src_reg(const prog_src_register *src)
{
- struct gl_program_parameter_list *plist = fp->Base.Parameters;
+ struct gl_program_parameter_list *plist = prog->Parameters;
fs_reg result;
result = fs_reg(this, glsl_type::vec4_type);
for (int i = 0; i < 4; i++) {
- emit(MOV(regoffset(result, i),
+ emit(MOV(offset(result, i),
fs_reg(plist->ParameterValues[src->Index][i].f)));
}
break;
*/
int src_swiz = GET_SWZ(src->Swizzle, i);
if (src_swiz == SWIZZLE_ZERO) {
- emit(MOV(regoffset(result, i), fs_reg(0.0f)));
+ emit(MOV(offset(result, i), fs_reg(0.0f)));
} else if (src_swiz == SWIZZLE_ONE) {
- emit(MOV(regoffset(result, i),
+ emit(MOV(offset(result, i),
negate ? fs_reg(-1.0f) : fs_reg(1.0f)));
} else {
- fs_reg src = regoffset(unswizzled, src_swiz);
+ fs_reg src = offset(unswizzled, src_swiz);
if (negate)
src.negate = !src.negate;
- emit(MOV(regoffset(result, i), src));
+ emit(MOV(offset(result, i), src));
}
}
}
projects / mesa.git / blobdiff