return brw_reg;
}
-fs_generator::fs_generator(struct brw_context *brw,
+fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const void *key,
struct brw_stage_prog_data *prog_data,
bool runtime_check_aads_emit,
const char *stage_abbrev)
- : brw(brw), key(key),
+ : compiler(compiler), log_data(log_data),
+ devinfo(compiler->devinfo), key(key),
prog_data(prog_data),
prog(prog), promoted_constants(promoted_constants),
runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
{
- ctx = &brw->ctx;
-
- p = rzalloc(mem_ctx, struct brw_compile);
- brw_init_compile(brw, p, mem_ctx);
+ p = rzalloc(mem_ctx, struct brw_codegen);
+ brw_init_codegen(devinfo, p, mem_ctx);
}
fs_generator::~fs_generator()
bool
fs_generator::patch_discard_jumps_to_fb_writes()
{
- if (brw->gen < 6 || this->discard_halt_patches.is_empty())
+ if (devinfo->gen < 6 || this->discard_halt_patches.is_empty())
return false;
int scale = brw_jump_scale(p->devinfo);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
0,
inst->eot,
last_render_target,
- inst->header_present);
+ inst->header_size != 0);
brw_mark_surface_used(&prog_data->base, surf_index);
}
const brw_wm_prog_key * const key = (brw_wm_prog_key * const) this->key;
struct brw_reg implied_header;
- if (brw->gen < 8 && !brw->is_haswell) {
+ if (devinfo->gen < 8 && !devinfo->is_haswell) {
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
}
/* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
* move, here's g1.
*/
- if (inst->header_present) {
+ if (inst->header_size != 0) {
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
if (prog_data->uses_kill) {
struct brw_reg pixel_mask;
- if (brw->gen >= 6)
+ if (devinfo->gen >= 6)
pixel_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
else
pixel_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
brw_MOV(p, pixel_mask, brw_flag_reg(0, 1));
}
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
brw_push_insn_state(p);
brw_set_default_exec_size(p, BRW_EXECUTE_16);
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
fire_fb_write(inst, payload, implied_header, inst->mlen);
} else {
/* This can only happen in gen < 6 */
- assert(brw->gen < 6);
+ assert(devinfo->gen < 6);
struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(), BRW_REGISTER_TYPE_UD));
brw_inst_set_urb_global_offset(p->devinfo, insn, inst->offset);
}
+void
+fs_generator::generate_cs_terminate(fs_inst *inst, struct brw_reg payload)
+{
+ struct brw_inst *insn;
+
+ insn = brw_next_insn(p, BRW_OPCODE_SEND);
+
+ brw_set_dest(p, insn, brw_null_reg());
+ brw_set_src0(p, insn, payload);
+ brw_set_src1(p, insn, brw_imm_d(0));
+
+ /* Terminate a compute shader by sending a message to the thread spawner.
+ */
+ brw_inst_set_sfid(devinfo, insn, BRW_SFID_THREAD_SPAWNER);
+ brw_inst_set_mlen(devinfo, insn, 1);
+ brw_inst_set_rlen(devinfo, insn, 0);
+ brw_inst_set_eot(devinfo, insn, inst->eot);
+ brw_inst_set_header_present(devinfo, insn, false);
+
+ brw_inst_set_ts_opcode(devinfo, insn, 0); /* Dereference resource */
+ brw_inst_set_ts_request_type(devinfo, insn, 0); /* Root thread */
+
+ /* Note that even though the thread has a URB resource associated with it,
+ * we set the "do not dereference URB" bit, because the URB resource is
+ * managed by the fixed-function unit, so it will free it automatically.
+ */
+ brw_inst_set_ts_resource_select(devinfo, insn, 1); /* Do not dereference URB */
+
+ brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
+}
+
+void
+fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
+{
+ brw_barrier(p, src);
+ brw_WAIT(p);
+}
+
void
fs_generator::generate_blorp_fb_write(fs_inst *inst)
{
0,
true,
true,
- inst->header_present);
+ inst->header_size != 0);
}
void
struct brw_reg delta_y = offset(src[0], dispatch_width / 8);
struct brw_reg interp = src[1];
- if (brw->has_pln &&
- (brw->gen >= 7 || (delta_x.nr & 1) == 0)) {
+ if (devinfo->has_pln &&
+ (devinfo->gen >= 7 || (delta_x.nr & 1) == 0)) {
brw_PLN(p, dst, interp, delta_x);
} else {
brw_LINE(p, brw_null_reg(), interp, delta_x);
unreachable("Invalid width for texture instruction");
}
- if (brw->gen >= 5) {
+ if (devinfo->gen >= 5) {
switch (inst->opcode) {
case SHADER_OPCODE_TEX:
if (inst->shadow_compare) {
case SHADER_OPCODE_TXD:
if (inst->shadow_compare) {
/* Gen7.5+. Otherwise, lowered by brw_lower_texture_gradients(). */
- assert(brw->gen >= 8 || brw->is_haswell);
+ assert(devinfo->gen >= 8 || devinfo->is_haswell);
msg_type = HSW_SAMPLER_MESSAGE_SAMPLE_DERIV_COMPARE;
} else {
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_DERIVS;
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_CMS:
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DMS;
else
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
break;
case SHADER_OPCODE_TXF_UMS:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD2DSS;
break;
case SHADER_OPCODE_TXF_MCS:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_LD_MCS;
break;
case SHADER_OPCODE_LOD:
break;
case SHADER_OPCODE_TG4:
if (inst->shadow_compare) {
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_C;
} else {
- assert(brw->gen >= 6);
+ assert(devinfo->gen >= 6);
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4;
}
break;
case SHADER_OPCODE_TG4_OFFSET:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
if (inst->shadow_compare) {
msg_type = GEN7_SAMPLER_MESSAGE_SAMPLE_GATHER4_PO_C;
} else {
}
if (is_combined_send) {
- assert(brw->gen >= 9 || brw->is_cherryview);
+ assert(devinfo->gen >= 9 || devinfo->is_cherryview);
rlen = 0;
}
- assert(brw->gen < 7 || !inst->header_present ||
+ assert(devinfo->gen < 7 || inst->header_size == 0 ||
src.file == BRW_GENERAL_REGISTER_FILE);
assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
* we need to set it up explicitly and load the offset bitfield.
* Otherwise, we can use an implied move from g0 to the first message reg.
*/
- if (inst->header_present) {
- if (brw->gen < 6 && !inst->offset) {
+ if (inst->header_size != 0) {
+ if (devinfo->gen < 6 && !inst->offset) {
/* Set up an implied move from g0 to the MRF. */
src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
} else {
struct brw_reg header_reg;
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
header_reg = src;
} else {
assert(inst->base_mrf != -1);
msg_type,
rlen,
inst->mlen,
- inst->header_present,
+ inst->header_size != 0,
simd_mode,
return_format);
brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
} else {
/* Non-const sampler index */
- /* Note: this clobbers `dst` as a temporary before emitting the send */
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
- struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
-
struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_access_mode(p, BRW_ALIGN_1);
- /* Some care required: `sampler` and `temp` may alias:
- * addr = sampler & 0xff
- * temp = (sampler << 8) & 0xf00
- * addr = addr | temp
- */
- brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
- brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
- brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
- brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
- brw_OR(p, addr, addr, temp);
+ /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
+ brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
+ if (base_binding_table_index)
+ brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
+ brw_AND(p, addr, addr, brw_imm_ud(0xfff));
brw_pop_insn_state(p);
msg_type,
rlen,
inst->mlen /* mlen */,
- inst->header_present /* header */,
+ inst->header_size != 0 /* header */,
simd_mode,
return_format);
*/
bool unroll_to_simd8 =
(dispatch_width == 16 &&
- (brw->gen == 4 || (brw->gen == 7 && !brw->is_haswell)));
+ (devinfo->gen == 4 || (devinfo->gen == 7 && !devinfo->is_haswell)));
/* produce accurate derivatives */
struct brw_reg src0 = brw_reg(src.file, src.nr, 0,
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_16);
if (unroll_to_simd8) {
+ brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
if (negate_value) {
brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
void
fs_generator::generate_discard_jump(fs_inst *inst)
{
- assert(brw->gen >= 6);
+ assert(devinfo->gen >= 6);
/* This HALT will be patched up at FB write time to point UIP at the end of
* the program, and at brw_uip_jip() JIP will be set to the end of the
bool header_present = false;
int mlen = 1;
- if (brw->gen >= 9) {
+ if (devinfo->gen >= 9) {
/* Skylake requires a message header in order to use SIMD4x2 mode. */
src = retype(brw_vec4_grf(offset.nr - 1, 0), BRW_REGISTER_TYPE_UD);
mlen = 2;
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+ brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_MOV(p, vec8(src), retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
brw_set_default_access_mode(p, BRW_ALIGN_1);
struct brw_reg index,
struct brw_reg offset)
{
- assert(brw->gen < 7); /* Should use the gen7 variant. */
- assert(inst->header_present);
+ assert(devinfo->gen < 7); /* Should use the gen7 variant. */
+ assert(inst->header_size != 0);
assert(inst->mlen);
assert(index.file == BRW_IMMEDIATE_VALUE &&
rlen = 4;
}
- if (brw->gen >= 5)
+ if (devinfo->gen >= 5)
msg_type = GEN5_SAMPLER_MESSAGE_SAMPLE_LD;
else {
/* We always use the SIMD16 message so that we only have to load U, and
brw_inst_set_qtr_control(p->devinfo, send, BRW_COMPRESSION_NONE);
brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UW));
brw_set_src0(p, send, header);
- if (brw->gen < 6)
+ if (devinfo->gen < 6)
brw_inst_set_base_mrf(p->devinfo, send, inst->base_mrf);
/* Our surface is set up as floats, regardless of what actual data is
msg_type,
rlen,
inst->mlen,
- inst->header_present,
+ inst->header_size != 0,
simd_mode,
return_format);
struct brw_reg index,
struct brw_reg offset)
{
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
/* Varying-offset pull constant loads are treated as a normal expression on
* gen7, so the fact that it's a send message is hidden at the IR level.
*/
- assert(!inst->header_present);
+ assert(inst->header_size == 0);
assert(!inst->mlen);
assert(index.type == BRW_REGISTER_TYPE_UD);
struct brw_reg flags = brw_flag_reg(0, inst->flag_subreg);
struct brw_reg dispatch_mask;
- if (brw->gen >= 6)
+ if (devinfo->gen >= 6)
dispatch_mask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW);
else
dispatch_mask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW);
struct brw_reg x,
struct brw_reg y)
{
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
assert(dst.type == BRW_REGISTER_TYPE_UD);
assert(x.type == BRW_REGISTER_TYPE_F);
assert(y.type == BRW_REGISTER_TYPE_F);
struct brw_reg dst,
struct brw_reg src)
{
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
assert(dst.type == BRW_REGISTER_TYPE_F);
assert(src.type == BRW_REGISTER_TYPE_UD);
struct brw_reg offset,
struct brw_reg value)
{
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
brw_push_insn_state(p);
brw_set_default_mask_control(p, true);
prog_data->binding_table.shader_time_start);
}
-void
-fs_generator::generate_untyped_atomic(fs_inst *inst, struct brw_reg dst,
- struct brw_reg payload,
- struct brw_reg atomic_op,
- struct brw_reg surf_index)
-{
- assert(atomic_op.file == BRW_IMMEDIATE_VALUE &&
- atomic_op.type == BRW_REGISTER_TYPE_UD &&
- surf_index.file == BRW_IMMEDIATE_VALUE &&
- surf_index.type == BRW_REGISTER_TYPE_UD);
-
- brw_untyped_atomic(p, dst, payload,
- atomic_op.dw1.ud, surf_index.dw1.ud,
- inst->mlen, true);
-
- brw_mark_surface_used(prog_data, surf_index.dw1.ud);
-}
-
-void
-fs_generator::generate_untyped_surface_read(fs_inst *inst, struct brw_reg dst,
- struct brw_reg payload,
- struct brw_reg surf_index)
-{
- assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
- surf_index.type == BRW_REGISTER_TYPE_UD);
-
- brw_untyped_surface_read(p, dst, payload, surf_index.dw1.ud, inst->mlen, 1);
-
- brw_mark_surface_used(prog_data, surf_index.dw1.ud);
-}
-
void
fs_generator::enable_debug(const char *shader_name)
{
this->shader_name = shader_name;
}
-/**
- * Some hardware doesn't support SIMD16 instructions with 3 sources.
- */
-static bool
-brw_supports_simd16_3src(const struct brw_context *brw)
-{
- /* WaDisableSIMD16On3SrcInstr: 3-source instructions don't work in SIMD16
- * on a few steppings of Skylake.
- */
- if (brw->gen == 9)
- return brw->revision != 2 && brw->revision != 3 && brw->revision != -1;
-
- return brw->is_haswell || brw->gen >= 8;
-}
-
int
fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
{
bool multiple_instructions_emitted = false;
if (unlikely(debug_flag))
- annotate(brw, &annotation, cfg, inst, p->next_insn_offset);
+ annotate(p->devinfo, &annotation, cfg, inst, p->next_insn_offset);
for (unsigned int i = 0; i < inst->sources; i++) {
src[i] = brw_reg_from_fs_reg(&inst->src[i]);
break;
case 16:
case 32:
- if (type_sz(inst->dst.type) < sizeof(float))
- brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
- else
+ /* If the instruction writes to more than one register, it needs to
+ * be a "compressed" instruction on Gen <= 5.
+ */
+ if (inst->exec_size * inst->dst.stride * type_sz(inst->dst.type) > 32)
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ else
+ brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
break;
default:
unreachable("Invalid instruction width");
break;
case BRW_OPCODE_MAD:
- assert(brw->gen >= 6);
+ assert(devinfo->gen >= 6);
brw_set_default_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
+ if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_inst *f = brw_MAD(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
break;
case BRW_OPCODE_LRP:
- assert(brw->gen >= 6);
+ assert(devinfo->gen >= 6);
brw_set_default_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
+ if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_inst *f = brw_LRP(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
brw_SHL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_F32TO16:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
brw_F32TO16(p, dst, src[0]);
break;
case BRW_OPCODE_F16TO32:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
brw_F16TO32(p, dst, src[0]);
break;
case BRW_OPCODE_CMP:
* coissuing would affect CMP instructions not otherwise affected by
* the errata.
*/
- if (dispatch_width == 16 && brw->gen == 7 && !brw->is_haswell) {
+ if (dispatch_width == 16 && devinfo->gen == 7 && !devinfo->is_haswell) {
if (dst.file == BRW_GENERAL_REGISTER_FILE) {
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_SEL(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_BFREV:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
/* BFREV only supports UD type for src and dst. */
brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
retype(src[0], BRW_REGISTER_TYPE_UD));
break;
case BRW_OPCODE_FBH:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
/* FBH only supports UD type for dst. */
brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_FBL:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
/* FBL only supports UD type for dst. */
brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_CBIT:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
/* CBIT only supports UD type for dst. */
brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
break;
case BRW_OPCODE_ADDC:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
brw_ADDC(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_SUBB:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
brw_SUBB(p, dst, src[0], src[1]);
break;
case BRW_OPCODE_MAC:
break;
case BRW_OPCODE_BFE:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
brw_set_default_access_mode(p, BRW_ALIGN_16);
- if (dispatch_width == 16 && !brw_supports_simd16_3src(brw)) {
+ if (dispatch_width == 16 && !devinfo->supports_simd16_3src) {
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_BFE(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
break;
case BRW_OPCODE_BFI1:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
/* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
* should
*
* "Force BFI instructions to be executed always in SIMD8."
*/
- if (dispatch_width == 16 && brw->is_haswell) {
+ if (dispatch_width == 16 && devinfo->is_haswell) {
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_BFI1(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]));
}
break;
case BRW_OPCODE_BFI2:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
brw_set_default_access_mode(p, BRW_ALIGN_16);
/* The Haswell WaForceSIMD8ForBFIInstruction workaround says that we
* should
* do for the other three-source instructions.
*/
if (dispatch_width == 16 &&
- (brw->is_haswell || !brw_supports_simd16_3src(brw))) {
+ (devinfo->is_haswell || !devinfo->supports_simd16_3src)) {
brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_BFI2(p, firsthalf(dst), firsthalf(src[0]), firsthalf(src[1]), firsthalf(src[2]));
case BRW_OPCODE_IF:
if (inst->src[0].file != BAD_FILE) {
/* The instruction has an embedded compare (only allowed on gen6) */
- assert(brw->gen == 6);
+ assert(devinfo->gen == 6);
gen6_IF(p, inst->conditional_mod, src[0], src[1]);
} else {
brw_IF(p, dispatch_width == 16 ? BRW_EXECUTE_16 : BRW_EXECUTE_8);
case SHADER_OPCODE_LOG2:
case SHADER_OPCODE_SIN:
case SHADER_OPCODE_COS:
- assert(brw->gen < 6 || inst->mlen == 0);
+ assert(devinfo->gen < 6 || inst->mlen == 0);
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
gen6_math(p, dst, brw_math_function(inst->opcode), src[0],
brw_null_reg());
- } else if (brw->gen == 6) {
+ } else if (devinfo->gen == 6) {
generate_math_gen6(inst, dst, src[0], brw_null_reg());
- } else if (brw->gen == 5 || brw->is_g4x) {
+ } else if (devinfo->gen == 5 || devinfo->is_g4x) {
generate_math_g45(inst, dst, src[0]);
} else {
generate_math_gen4(inst, dst, src[0]);
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
case SHADER_OPCODE_POW:
- assert(brw->gen < 6 || inst->mlen == 0);
+ assert(devinfo->gen < 6 || inst->mlen == 0);
assert(inst->conditional_mod == BRW_CONDITIONAL_NONE);
- if (brw->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
+ if (devinfo->gen >= 7 && inst->opcode == SHADER_OPCODE_POW) {
gen6_math(p, dst, brw_math_function(inst->opcode), src[0], src[1]);
- } else if (brw->gen >= 6) {
+ } else if (devinfo->gen >= 6) {
generate_math_gen6(inst, dst, src[0], src[1]);
} else {
generate_math_gen4(inst, dst, src[0]);
break;
case SHADER_OPCODE_UNTYPED_ATOMIC:
- generate_untyped_atomic(inst, dst, src[0], src[1], src[2]);
+ assert(src[1].file == BRW_IMMEDIATE_VALUE &&
+ src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_untyped_atomic(p, dst, src[0], src[1], src[2].dw1.ud,
+ inst->mlen, !inst->dst.is_null());
+ brw_mark_surface_used(prog_data, src[1].dw1.ud);
break;
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
- generate_untyped_surface_read(inst, dst, src[0], src[1]);
+ assert(src[1].file == BRW_IMMEDIATE_VALUE &&
+ src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_untyped_surface_read(p, dst, src[0], src[1],
+ inst->mlen, src[2].dw1.ud);
+ brw_mark_surface_used(prog_data, src[1].dw1.ud);
+ break;
+
+ case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_untyped_surface_write(p, src[0], src[1],
+ inst->mlen, src[2].dw1.ud);
+ break;
+
+ case SHADER_OPCODE_TYPED_ATOMIC:
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_typed_atomic(p, dst, src[0], src[1],
+ src[2].dw1.ud, inst->mlen, !inst->dst.is_null());
+ break;
+
+ case SHADER_OPCODE_TYPED_SURFACE_READ:
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_typed_surface_read(p, dst, src[0], src[1],
+ inst->mlen, src[2].dw1.ud);
+ break;
+
+ case SHADER_OPCODE_TYPED_SURFACE_WRITE:
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].dw1.ud);
+ break;
+
+ case SHADER_OPCODE_MEMORY_FENCE:
+ brw_memory_fence(p, dst);
break;
case FS_OPCODE_SET_SIMD4X2_OFFSET:
generate_set_simd4x2_offset(inst, dst, src[0]);
break;
+ case SHADER_OPCODE_FIND_LIVE_CHANNEL:
+ brw_find_live_channel(p, dst);
+ break;
+
+ case SHADER_OPCODE_BROADCAST:
+ brw_broadcast(p, dst, src[0], src[1]);
+ break;
+
case FS_OPCODE_SET_OMASK:
generate_set_omask(inst, dst, src[0]);
break;
GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET);
break;
+ case CS_OPCODE_CS_TERMINATE:
+ generate_cs_terminate(inst, src[0]);
+ break;
+
+ case SHADER_OPCODE_BARRIER:
+ generate_barrier(inst, src[0]);
+ break;
+
default:
- if (inst->opcode < (int) ARRAY_SIZE(opcode_descs)) {
- _mesa_problem(ctx, "Unsupported opcode `%s' in %s",
- opcode_descs[inst->opcode].name, stage_abbrev);
- } else {
- _mesa_problem(ctx, "Unsupported opcode %d in %s", inst->opcode,
- stage_abbrev);
- }
- abort();
+ unreachable("Unsupported opcode");
case SHADER_OPCODE_LOAD_PAYLOAD:
unreachable("Should be lowered by lower_load_payload()");
spill_count, fill_count, promoted_constants, before_size, after_size,
100.0f * (before_size - after_size) / before_size);
- dump_assembly(p->store, annotation.ann_count, annotation.ann, brw, prog);
+ dump_assembly(p->store, annotation.ann_count, annotation.ann,
+ p->devinfo, prog);
ralloc_free(annotation.ann);
}
- static GLuint msg_id = 0;
- _mesa_gl_debug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_OTHER,
- MESA_DEBUG_SEVERITY_NOTIFICATION,
- "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
- "Promoted %u constants, compacted %d to %d bytes.\n",
- stage_abbrev, dispatch_width, before_size / 16, loop_count,
- spill_count, fill_count, promoted_constants, before_size, after_size);
+ compiler->shader_debug_log(log_data,
+ "%s SIMD%d shader: %d inst, %d loops, "
+ "%d:%d spills:fills, Promoted %u constants, "
+ "compacted %d to %d bytes.\n",
+ stage_abbrev, dispatch_width, before_size / 16,
+ loop_count, spill_count, fill_count,
+ promoted_constants, before_size, after_size);
return start_offset;
}
projects / mesa.git / blobdiff