return brw_reg;
}
-fs_generator::fs_generator(struct brw_context *brw,
+fs_generator::fs_generator(const struct brw_compiler *compiler, void *log_data,
void *mem_ctx,
const void *key,
struct brw_stage_prog_data *prog_data,
bool runtime_check_aads_emit,
const char *stage_abbrev)
- : brw(brw), devinfo(brw->intelScreen->devinfo), key(key),
+ : compiler(compiler), log_data(log_data),
+ devinfo(compiler->devinfo), key(key),
prog_data(prog_data),
prog(prog), promoted_constants(promoted_constants),
runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
0,
inst->eot,
last_render_target,
- inst->header_present);
+ inst->header_size != 0);
brw_mark_surface_used(&prog_data->base, surf_index);
}
/* Header is 2 regs, g0 and g1 are the contents. g0 will be implied
* move, here's g1.
*/
- if (inst->header_present) {
+ if (inst->header_size != 0) {
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_predicate_control(p, BRW_PREDICATE_NONE);
brw_inst_set_mask_control(devinfo, insn, BRW_MASK_DISABLE);
}
+void
+fs_generator::generate_barrier(fs_inst *inst, struct brw_reg src)
+{
+ brw_barrier(p, src);
+ brw_WAIT(p);
+}
+
void
fs_generator::generate_blorp_fb_write(fs_inst *inst)
{
0,
true,
true,
- inst->header_present);
+ inst->header_size != 0);
}
void
rlen = 0;
}
- assert(devinfo->gen < 7 || !inst->header_present ||
+ assert(devinfo->gen < 7 || inst->header_size == 0 ||
src.file == BRW_GENERAL_REGISTER_FILE);
assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
* we need to set it up explicitly and load the offset bitfield.
* Otherwise, we can use an implied move from g0 to the first message reg.
*/
- if (inst->header_present) {
+ if (inst->header_size != 0) {
if (devinfo->gen < 6 && !inst->offset) {
/* Set up an implied move from g0 to the MRF. */
src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
msg_type,
rlen,
inst->mlen,
- inst->header_present,
+ inst->header_size != 0,
simd_mode,
return_format);
brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
} else {
/* Non-const sampler index */
- /* Note: this clobbers `dst` as a temporary before emitting the send */
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
- struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
-
struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_access_mode(p, BRW_ALIGN_1);
- /* Some care required: `sampler` and `temp` may alias:
- * addr = sampler & 0xff
- * temp = (sampler << 8) & 0xf00
- * addr = addr | temp
- */
- brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
- brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
- brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
- brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
- brw_OR(p, addr, addr, temp);
+ /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
+ brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
+ if (base_binding_table_index)
+ brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
+ brw_AND(p, addr, addr, brw_imm_ud(0xfff));
brw_pop_insn_state(p);
msg_type,
rlen,
inst->mlen /* mlen */,
- inst->header_present /* header */,
+ inst->header_size != 0 /* header */,
simd_mode,
return_format);
brw_push_insn_state(p);
brw_set_default_access_mode(p, BRW_ALIGN_16);
if (unroll_to_simd8) {
+ brw_set_default_exec_size(p, BRW_EXECUTE_8);
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
if (negate_value) {
brw_ADD(p, firsthalf(dst), firsthalf(src1), negate(firsthalf(src0)));
struct brw_reg offset)
{
assert(devinfo->gen < 7); /* Should use the gen7 variant. */
- assert(inst->header_present);
+ assert(inst->header_size != 0);
assert(inst->mlen);
assert(index.file == BRW_IMMEDIATE_VALUE &&
msg_type,
rlen,
inst->mlen,
- inst->header_present,
+ inst->header_size != 0,
simd_mode,
return_format);
/* Varying-offset pull constant loads are treated as a normal expression on
* gen7, so the fact that it's a send message is hidden at the IR level.
*/
- assert(!inst->header_present);
+ assert(inst->header_size == 0);
assert(!inst->mlen);
assert(index.type == BRW_REGISTER_TYPE_UD);
break;
case 16:
case 32:
- if (type_sz(inst->dst.type) < sizeof(float))
- brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
- else
+ /* If the instruction writes to more than one register, it needs to
+ * be a "compressed" instruction on Gen <= 5.
+ */
+ if (inst->exec_size * inst->dst.stride * type_sz(inst->dst.type) > 32)
brw_set_default_compression_control(p, BRW_COMPRESSION_COMPRESSED);
+ else
+ brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
break;
default:
unreachable("Invalid instruction width");
brw_mark_surface_used(prog_data, src[1].dw1.ud);
break;
+ case SHADER_OPCODE_UNTYPED_SURFACE_WRITE:
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_untyped_surface_write(p, src[0], src[1],
+ inst->mlen, src[2].dw1.ud);
+ break;
+
+ case SHADER_OPCODE_TYPED_ATOMIC:
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_typed_atomic(p, dst, src[0], src[1],
+ src[2].dw1.ud, inst->mlen, !inst->dst.is_null());
+ break;
+
+ case SHADER_OPCODE_TYPED_SURFACE_READ:
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_typed_surface_read(p, dst, src[0], src[1],
+ inst->mlen, src[2].dw1.ud);
+ break;
+
+ case SHADER_OPCODE_TYPED_SURFACE_WRITE:
+ assert(src[2].file == BRW_IMMEDIATE_VALUE);
+ brw_typed_surface_write(p, src[0], src[1], inst->mlen, src[2].dw1.ud);
+ break;
+
+ case SHADER_OPCODE_MEMORY_FENCE:
+ brw_memory_fence(p, dst);
+ break;
+
case FS_OPCODE_SET_SIMD4X2_OFFSET:
generate_set_simd4x2_offset(inst, dst, src[0]);
break;
+ case SHADER_OPCODE_FIND_LIVE_CHANNEL:
+ brw_find_live_channel(p, dst);
+ break;
+
+ case SHADER_OPCODE_BROADCAST:
+ brw_broadcast(p, dst, src[0], src[1]);
+ break;
+
case FS_OPCODE_SET_OMASK:
generate_set_omask(inst, dst, src[0]);
break;
generate_cs_terminate(inst, src[0]);
break;
+ case SHADER_OPCODE_BARRIER:
+ generate_barrier(inst, src[0]);
+ break;
+
default:
unreachable("Unsupported opcode");
ralloc_free(annotation.ann);
}
- static GLuint msg_id = 0;
- _mesa_gl_debug(&brw->ctx, &msg_id,
- MESA_DEBUG_SOURCE_SHADER_COMPILER,
- MESA_DEBUG_TYPE_OTHER,
- MESA_DEBUG_SEVERITY_NOTIFICATION,
- "%s SIMD%d shader: %d inst, %d loops, %d:%d spills:fills, "
- "Promoted %u constants, compacted %d to %d bytes.\n",
- stage_abbrev, dispatch_width, before_size / 16, loop_count,
- spill_count, fill_count, promoted_constants, before_size, after_size);
+ compiler->shader_debug_log(log_data,
+ "%s SIMD%d shader: %d inst, %d loops, "
+ "%d:%d spills:fills, Promoted %u constants, "
+ "compacted %d to %d bytes.\n",
+ stage_abbrev, dispatch_width, before_size / 16,
+ loop_count, spill_count, fill_count,
+ promoted_constants, before_size, after_size);
return start_offset;
}
projects / mesa.git / blobdiff