* native instructions.
*/
-#include "main/macros.h"
-#include "brw_context.h"
#include "brw_eu.h"
#include "brw_fs.h"
#include "brw_cfg.h"
+#include "brw_program.h"
static enum brw_reg_file
brw_file_from_reg(fs_reg *reg)
case ARF:
case FIXED_GRF:
case IMM:
- brw_reg = *static_cast<struct brw_reg *>(reg);
+ brw_reg = reg->as_brw_reg();
break;
case BAD_FILE:
/* Probably unused. */
struct brw_stage_prog_data *prog_data,
unsigned promoted_constants,
bool runtime_check_aads_emit,
- const char *stage_abbrev)
+ gl_shader_stage stage)
: compiler(compiler), log_data(log_data),
devinfo(compiler->devinfo), key(key),
prog_data(prog_data),
promoted_constants(promoted_constants),
runtime_check_aads_emit(runtime_check_aads_emit), debug_flag(false),
- stage_abbrev(stage_abbrev), mem_ctx(mem_ctx)
+ stage(stage), mem_ctx(mem_ctx)
{
p = rzalloc(mem_ctx, struct brw_codegen);
brw_init_codegen(devinfo, p, mem_ctx);
assert(inst->exec_size == 8 || devinfo->gen >= 8);
brw_MOV(p, addr, indirect_byte_offset);
- brw_inst_set_mask_control(devinfo, brw_last_inst, BRW_MASK_DISABLE);
brw_MOV(p, dst, retype(brw_VxH_indirect(0, imm_byte_offset), dst.type));
}
insn = brw_next_insn(p, BRW_OPCODE_SEND);
- brw_set_dest(p, insn, brw_null_reg());
+ brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_UW));
brw_set_src0(p, insn, payload);
brw_set_src1(p, insn, brw_imm_d(0));
void
fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
+ struct brw_reg surface_index,
struct brw_reg sampler_index)
{
int msg_type = -1;
break;
}
+ /* Stomp the resinfo output type to UINT32. On gens 4-5, the output type
+ * is set as part of the message descriptor. On gen4, the PRM seems to
+ * allow UINT32 and FLOAT32 (i965 PRM, Vol. 4 Section 4.8.1.1), but on
+ * later gens UINT32 is required. Once you hit Sandy Bridge, the bit is
+ * gone from the message descriptor entirely and you just get UINT32 all
+ * the time regasrdless. Since we can really only do non-UINT32 on gen4,
+ * just stomp it to UINT32 all the time.
+ */
+ if (inst->opcode == SHADER_OPCODE_TXS)
+ return_format = BRW_SAMPLER_RETURN_FORMAT_UINT32;
+
switch (inst->exec_size) {
case 8:
simd_mode = BRW_SAMPLER_SIMD_MODE_SIMD8;
/* Set the offset bits in DWord 2. */
brw_MOV(p, get_element_ud(header_reg, 2),
brw_imm_ud(inst->offset));
+ } else if (stage != MESA_SHADER_VERTEX &&
+ stage != MESA_SHADER_FRAGMENT) {
+ /* The vertex and fragment stages have g0.2 set to 0, so
+ * header0.2 is 0 when g0 is copied. Other stages may not, so we
+ * must set it to 0 to avoid setting undesirable bits in the
+ * message.
+ */
+ brw_MOV(p, get_element_ud(header_reg, 2), brw_imm_ud(0));
}
brw_adjust_sampler_state_pointer(p, header_reg, sampler_index);
? prog_data->binding_table.gather_texture_start
: prog_data->binding_table.texture_start;
- if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
+ if (surface_index.file == BRW_IMMEDIATE_VALUE &&
+ sampler_index.file == BRW_IMMEDIATE_VALUE) {
+ uint32_t surface = surface_index.ud;
uint32_t sampler = sampler_index.ud;
brw_SAMPLE(p,
retype(dst, BRW_REGISTER_TYPE_UW),
inst->base_mrf,
src,
- sampler + base_binding_table_index,
+ surface + base_binding_table_index,
sampler % 16,
msg_type,
rlen,
simd_mode,
return_format);
- brw_mark_surface_used(prog_data, sampler + base_binding_table_index);
+ brw_mark_surface_used(prog_data, surface + base_binding_table_index);
} else {
/* Non-const sampler index */
struct brw_reg addr = vec1(retype(brw_address_reg(0), BRW_REGISTER_TYPE_UD));
+ struct brw_reg surface_reg = vec1(retype(surface_index, BRW_REGISTER_TYPE_UD));
struct brw_reg sampler_reg = vec1(retype(sampler_index, BRW_REGISTER_TYPE_UD));
brw_push_insn_state(p);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_set_default_access_mode(p, BRW_ALIGN_1);
- /* addr = ((sampler * 0x101) + base_binding_table_index) & 0xfff */
- brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
+ if (memcmp(&surface_reg, &sampler_reg, sizeof(surface_reg)) == 0) {
+ brw_MUL(p, addr, sampler_reg, brw_imm_uw(0x101));
+ } else {
+ brw_SHL(p, addr, sampler_reg, brw_imm_ud(8));
+ brw_OR(p, addr, addr, surface_reg);
+ }
if (base_binding_table_index)
brw_ADD(p, addr, addr, brw_imm_ud(base_binding_table_index));
brw_AND(p, addr, addr, brw_imm_ud(0xfff));
brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
brw_set_default_mask_control(p, BRW_MASK_DISABLE);
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
+ brw_inst_set_exec_size(devinfo, send, BRW_EXECUTE_4);
brw_pop_insn_state(p);
brw_set_dest(p, send, dst);
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
case SHADER_OPCODE_SAMPLEINFO:
- generate_tex(inst, dst, src[0], src[1]);
+ generate_tex(inst, dst, src[0], src[1], src[2]);
break;
case FS_OPCODE_DDX_COARSE:
case FS_OPCODE_DDX_FINE:
brw_broadcast(p, dst, src[0], src[1]);
break;
+ case SHADER_OPCODE_EXTRACT_BYTE: {
+ assert(src[0].type == BRW_REGISTER_TYPE_D ||
+ src[0].type == BRW_REGISTER_TYPE_UD);
+
+ enum brw_reg_type type =
+ src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_B
+ : BRW_REGISTER_TYPE_UB;
+ brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 4));
+ break;
+ }
+
+ case SHADER_OPCODE_EXTRACT_WORD: {
+ assert(src[0].type == BRW_REGISTER_TYPE_D ||
+ src[0].type == BRW_REGISTER_TYPE_UD);
+
+ enum brw_reg_type type =
+ src[0].type == BRW_REGISTER_TYPE_D ? BRW_REGISTER_TYPE_W
+ : BRW_REGISTER_TYPE_UW;
+ brw_MOV(p, dst, spread(suboffset(retype(src[0], type), src[1].ud), 2));
+ break;
+ }
+
case FS_OPCODE_SET_SAMPLE_ID:
generate_set_sample_id(inst, dst, src[0], src[1]);
break;
compiler->shader_debug_log(log_data,
"%s SIMD%d shader: %d inst, %d loops, %u cycles, "
"%d:%d spills:fills, Promoted %u constants, "
- "compacted %d to %d bytes.\n",
- stage_abbrev, dispatch_width, before_size / 16,
+ "compacted %d to %d bytes.",
+ _mesa_shader_stage_to_abbrev(stage),
+ dispatch_width, before_size / 16,
loop_count, cfg->cycle_count, spill_count,
fill_count, promoted_constants, before_size,
after_size);
projects / mesa.git / blobdiff