using namespace brw;
+#define MAX_INSTRUCTION (1 << 30)
+
/** @file brw_fs_live_variables.cpp
*
* Support for calculating liveness information about virtual GRFs.
* VGRF is ultimately used or defined. Tracking individual components
* allows us to easily assemble this information.
*
- * See Muchnik's Advanced Compiler Design and Implementation, section
+ * See Muchnick's Advanced Compiler Design and Implementation, section
* 14.1 (p444).
*/
+void
+fs_live_variables::setup_one_read(struct block_data *bd, fs_inst *inst,
+ int ip, const fs_reg ®)
+{
+ int var = var_from_reg(reg);
+ assert(var < num_vars);
+
+ start[var] = MIN2(start[var], ip);
+ end[var] = MAX2(end[var], ip);
+
+ /* The use[] bitset marks when the block makes use of a variable (VGRF
+ * channel) without having completely defined that variable within the
+ * block.
+ */
+ if (!BITSET_TEST(bd->def, var))
+ BITSET_SET(bd->use, var);
+}
+
+void
+fs_live_variables::setup_one_write(struct block_data *bd, fs_inst *inst,
+ int ip, const fs_reg ®)
+{
+ int var = var_from_reg(reg);
+ assert(var < num_vars);
+
+ start[var] = MIN2(start[var], ip);
+ end[var] = MAX2(end[var], ip);
+
+ /* The def[] bitset marks when an initialization in a block completely
+ * screens off previous updates of that variable (VGRF channel).
+ */
+ if (inst->dst.file == VGRF && !inst->is_partial_write()) {
+ if (!BITSET_TEST(bd->use, var))
+ BITSET_SET(bd->def, var);
+ }
+}
+
/**
* Sets up the use[] and def[] bitsets.
*
{
int ip = 0;
- for (int b = 0; b < cfg->num_blocks; b++) {
- bblock_t *block = cfg->blocks[b];
-
+ foreach_block (block, cfg) {
assert(ip == block->start_ip);
- if (b > 0)
- assert(cfg->blocks[b - 1]->end_ip == ip - 1);
+ if (block->num > 0)
+ assert(cfg->blocks[block->num - 1]->end_ip == ip - 1);
- for (fs_inst *inst = (fs_inst *)block->start;
- inst != block->end->next;
- inst = (fs_inst *)inst->next) {
+ struct block_data *bd = &block_data[block->num];
+ foreach_inst_in_block(fs_inst, inst, block) {
/* Set use[] for this instruction */
- for (unsigned int i = 0; i < 3; i++) {
- if (inst->src[i].file != GRF)
- continue;
-
- int regs_read = 1;
- /* We don't know how many components are read in a send-from-grf,
- * so just assume "all of them."
- */
- if (inst->is_send_from_grf())
- regs_read = v->virtual_grf_sizes[inst->src[i].reg];
+ for (unsigned int i = 0; i < inst->sources; i++) {
+ fs_reg reg = inst->src[i];
- for (int j = 0; j < regs_read; j++) {
- int var = var_from_vgrf[inst->src[i].reg] +
- inst->src[i].reg_offset + j;
+ if (reg.file != VGRF)
+ continue;
- if (!BITSET_TEST(bd[b].def, var))
- BITSET_SET(bd[b].use, var);
+ for (int j = 0; j < inst->regs_read(i); j++) {
+ setup_one_read(bd, inst, ip, reg);
+ reg.reg_offset++;
}
}
+ if (inst->reads_flag()) {
+ /* The vertical combination predicates read f0.0 and f0.1. */
+ if (inst->predicate == BRW_PREDICATE_ALIGN1_ANYV ||
+ inst->predicate == BRW_PREDICATE_ALIGN1_ALLV) {
+ assert(inst->flag_subreg == 0);
+ if (!BITSET_TEST(bd->flag_def, 1)) {
+ BITSET_SET(bd->flag_use, 1);
+ }
+ }
+ if (!BITSET_TEST(bd->flag_def, inst->flag_subreg)) {
+ BITSET_SET(bd->flag_use, inst->flag_subreg);
+ }
+ }
- /* Check for unconditional writes to whole registers. These
- * are the things that screen off preceding definitions of a
- * variable, and thus qualify for being in def[].
- */
- if (inst->dst.file == GRF && !inst->is_partial_write()) {
- int var = var_from_vgrf[inst->dst.reg] + inst->dst.reg_offset;
+ /* Set def[] for this instruction */
+ if (inst->dst.file == VGRF) {
+ fs_reg reg = inst->dst;
for (int j = 0; j < inst->regs_written; j++) {
- if (!BITSET_TEST(bd[b].use, var + j))
- BITSET_SET(bd[b].def, var + j);
+ setup_one_write(bd, inst, ip, reg);
+ reg.reg_offset++;
}
}
+ if (inst->writes_flag()) {
+ if (!BITSET_TEST(bd->flag_use, inst->flag_subreg)) {
+ BITSET_SET(bd->flag_def, inst->flag_subreg);
+ }
+ }
ip++;
}
while (cont) {
cont = false;
- for (int b = 0; b < cfg->num_blocks; b++) {
- /* Update livein */
- for (int i = 0; i < bitset_words; i++) {
- BITSET_WORD new_livein = (bd[b].use[i] |
- (bd[b].liveout[i] & ~bd[b].def[i]));
- if (new_livein & ~bd[b].livein[i]) {
- bd[b].livein[i] |= new_livein;
- cont = true;
- }
- }
+ foreach_block_reverse (block, cfg) {
+ struct block_data *bd = &block_data[block->num];
/* Update liveout */
- foreach_list(block_node, &cfg->blocks[b]->children) {
- bblock_link *link = (bblock_link *)block_node;
- bblock_t *block = link->block;
+ foreach_list_typed(bblock_link, child_link, link, &block->children) {
+ struct block_data *child_bd = &block_data[child_link->block->num];
for (int i = 0; i < bitset_words; i++) {
- BITSET_WORD new_liveout = (bd[block->block_num].livein[i] &
- ~bd[b].liveout[i]);
+ BITSET_WORD new_liveout = (child_bd->livein[i] &
+ ~bd->liveout[i]);
if (new_liveout) {
- bd[b].liveout[i] |= new_liveout;
+ bd->liveout[i] |= new_liveout;
cont = true;
}
}
+ BITSET_WORD new_liveout = (child_bd->flag_livein[0] &
+ ~bd->flag_liveout[0]);
+ if (new_liveout) {
+ bd->flag_liveout[0] |= new_liveout;
+ cont = true;
+ }
}
+
+ /* Update livein */
+ for (int i = 0; i < bitset_words; i++) {
+ BITSET_WORD new_livein = (bd->use[i] |
+ (bd->liveout[i] &
+ ~bd->def[i]));
+ if (new_livein & ~bd->livein[i]) {
+ bd->livein[i] |= new_livein;
+ cont = true;
+ }
+ }
+ BITSET_WORD new_livein = (bd->flag_use[0] |
+ (bd->flag_liveout[0] &
+ ~bd->flag_def[0]));
+ if (new_livein & ~bd->flag_livein[0]) {
+ bd->flag_livein[0] |= new_livein;
+ cont = true;
+ }
+ }
+ }
+}
+
+/**
+ * Extend the start/end ranges for each variable to account for the
+ * new information calculated from control flow.
+ */
+void
+fs_live_variables::compute_start_end()
+{
+ foreach_block (block, cfg) {
+ struct block_data *bd = &block_data[block->num];
+
+ for (int i = 0; i < num_vars; i++) {
+ if (BITSET_TEST(bd->livein, i)) {
+ start[i] = MIN2(start[i], block->start_ip);
+ end[i] = MAX2(end[i], block->start_ip);
+ }
+
+ if (BITSET_TEST(bd->liveout, i)) {
+ start[i] = MIN2(start[i], block->end_ip);
+ end[i] = MAX2(end[i], block->end_ip);
+ }
}
}
}
-fs_live_variables::fs_live_variables(fs_visitor *v, cfg_t *cfg)
+fs_live_variables::fs_live_variables(fs_visitor *v, const cfg_t *cfg)
: v(v), cfg(cfg)
{
- mem_ctx = ralloc_context(cfg->mem_ctx);
+ mem_ctx = ralloc_context(NULL);
- num_vgrfs = v->virtual_grf_count;
+ num_vgrfs = v->alloc.count;
num_vars = 0;
var_from_vgrf = rzalloc_array(mem_ctx, int, num_vgrfs);
for (int i = 0; i < num_vgrfs; i++) {
var_from_vgrf[i] = num_vars;
- num_vars += v->virtual_grf_sizes[i];
+ num_vars += v->alloc.sizes[i];
}
vgrf_from_var = rzalloc_array(mem_ctx, int, num_vars);
for (int i = 0; i < num_vgrfs; i++) {
- for (int j = 0; j < v->virtual_grf_sizes[i]; j++) {
+ for (unsigned j = 0; j < v->alloc.sizes[i]; j++) {
vgrf_from_var[var_from_vgrf[i] + j] = i;
}
}
- bd = rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
+ start = ralloc_array(mem_ctx, int, num_vars);
+ end = rzalloc_array(mem_ctx, int, num_vars);
+ for (int i = 0; i < num_vars; i++) {
+ start[i] = MAX_INSTRUCTION;
+ end[i] = -1;
+ }
+
+ block_data= rzalloc_array(mem_ctx, struct block_data, cfg->num_blocks);
bitset_words = BITSET_WORDS(num_vars);
for (int i = 0; i < cfg->num_blocks; i++) {
- bd[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
- bd[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
- bd[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
- bd[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
+ block_data[i].def = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
+ block_data[i].use = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
+ block_data[i].livein = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
+ block_data[i].liveout = rzalloc_array(mem_ctx, BITSET_WORD, bitset_words);
+
+ block_data[i].flag_def[0] = 0;
+ block_data[i].flag_use[0] = 0;
+ block_data[i].flag_livein[0] = 0;
+ block_data[i].flag_liveout[0] = 0;
}
setup_def_use();
compute_live_variables();
+ compute_start_end();
}
fs_live_variables::~fs_live_variables()
ralloc_free(mem_ctx);
}
-#define MAX_INSTRUCTION (1 << 30)
-
void
fs_visitor::invalidate_live_intervals()
{
- this->live_intervals_valid = false;
+ ralloc_free(live_intervals);
+ live_intervals = NULL;
}
/**
void
fs_visitor::calculate_live_intervals()
{
- if (this->live_intervals_valid)
+ if (this->live_intervals)
return;
- int num_vgrfs = this->virtual_grf_count;
- int *start = ralloc_array(mem_ctx, int, num_vgrfs);
- int *end = ralloc_array(mem_ctx, int, num_vgrfs);
+ int num_vgrfs = this->alloc.count;
ralloc_free(this->virtual_grf_start);
ralloc_free(this->virtual_grf_end);
- this->virtual_grf_start = start;
- this->virtual_grf_end = end;
+ virtual_grf_start = ralloc_array(mem_ctx, int, num_vgrfs);
+ virtual_grf_end = ralloc_array(mem_ctx, int, num_vgrfs);
for (int i = 0; i < num_vgrfs; i++) {
- start[i] = MAX_INSTRUCTION;
- end[i] = -1;
- }
-
- /* Start by setting up the intervals with no knowledge of control
- * flow.
- */
- int ip = 0;
- foreach_list(node, &this->instructions) {
- fs_inst *inst = (fs_inst *)node;
-
- for (unsigned int i = 0; i < 3; i++) {
- if (inst->src[i].file == GRF) {
- int reg = inst->src[i].reg;
- int end_ip = ip;
-
- /* In most cases, a register can be written over safely by the
- * same instruction that is its last use. For a single
- * instruction, the sources are dereferenced before writing of the
- * destination starts (naturally). This gets more complicated for
- * simd16, because the instruction:
- *
- * mov(16) g4<1>F g4<8,8,1>F g6<8,8,1>F
- *
- * is actually decoded in hardware as:
- *
- * mov(8) g4<1>F g4<8,8,1>F g6<8,8,1>F
- * mov(8) g5<1>F g5<8,8,1>F g7<8,8,1>F
- *
- * Which is safe. However, if we have uniform accesses
- * happening, we get into trouble:
- *
- * mov(8) g4<1>F g4<0,1,0>F g6<8,8,1>F
- * mov(8) g5<1>F g4<0,1,0>F g7<8,8,1>F
- *
- * Now our destination for the first instruction overwrote the
- * second instruction's src0, and we get garbage for those 8
- * pixels. There's a similar issue for the pre-gen6
- * pixel_x/pixel_y, which are registers of 16-bit values and thus
- * would get stomped by the first decode as well.
- */
- if (dispatch_width == 16 && (inst->src[i].smear >= 0 ||
- (this->pixel_x.reg == reg ||
- this->pixel_y.reg == reg))) {
- end_ip++;
- }
-
- start[reg] = MIN2(start[reg], ip);
- end[reg] = MAX2(end[reg], end_ip);
- }
- }
-
- if (inst->dst.file == GRF) {
- int reg = inst->dst.reg;
-
- start[reg] = MIN2(start[reg], ip);
- end[reg] = MAX2(end[reg], ip);
- }
-
- ip++;
+ virtual_grf_start[i] = MAX_INSTRUCTION;
+ virtual_grf_end[i] = -1;
}
- /* Now, extend those intervals using our analysis of control flow. */
- cfg_t cfg(this);
- fs_live_variables livevars(this, &cfg);
-
- for (int b = 0; b < cfg.num_blocks; b++) {
- for (int i = 0; i < livevars.num_vars; i++) {
- int vgrf = livevars.vgrf_from_var[i];
- if (BITSET_TEST(livevars.bd[b].livein, i)) {
- start[vgrf] = MIN2(start[vgrf], cfg.blocks[b]->start_ip);
- end[vgrf] = MAX2(end[vgrf], cfg.blocks[b]->start_ip);
- }
+ this->live_intervals = new(mem_ctx) fs_live_variables(this, cfg);
- if (BITSET_TEST(livevars.bd[b].liveout, i)) {
- start[vgrf] = MIN2(start[vgrf], cfg.blocks[b]->end_ip);
- end[vgrf] = MAX2(end[vgrf], cfg.blocks[b]->end_ip);
- }
- }
+ /* Merge the per-component live ranges to whole VGRF live ranges. */
+ for (int i = 0; i < live_intervals->num_vars; i++) {
+ int vgrf = live_intervals->vgrf_from_var[i];
+ virtual_grf_start[vgrf] = MIN2(virtual_grf_start[vgrf],
+ live_intervals->start[i]);
+ virtual_grf_end[vgrf] = MAX2(virtual_grf_end[vgrf],
+ live_intervals->end[i]);
}
+}
- this->live_intervals_valid = true;
+bool
+fs_live_variables::vars_interfere(int a, int b)
+{
+ return !(end[b] <= start[a] ||
+ end[a] <= start[b]);
}
bool
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