* IN THE SOFTWARE.
*/
+#include "glsl/ir.h"
+#include "glsl/ir_optimization.h"
#include "glsl/nir/glsl_to_nir.h"
#include "brw_fs.h"
-static glsl_interp_qualifier
-determine_interpolation_mode(nir_variable *var, bool flat_shade)
-{
- if (var->data.interpolation != INTERP_QUALIFIER_NONE)
- return (glsl_interp_qualifier) var->data.interpolation;
- int location = var->data.location;
- bool is_gl_Color =
- location == VARYING_SLOT_COL0 || location == VARYING_SLOT_COL1;
- if (flat_shade && is_gl_Color)
- return INTERP_QUALIFIER_FLAT;
- else
- return INTERP_QUALIFIER_SMOOTH;
-}
-
void
fs_visitor::emit_nir_code()
{
/* first, lower the GLSL IR shader to NIR */
+ lower_output_reads(shader->base.ir);
nir_shader *nir = glsl_to_nir(shader->base.ir, NULL, true);
nir_validate_shader(nir);
- /* lower some of the GLSL-isms into NIR-isms - after this point, we no
- * longer have to deal with variables inside the shader
- */
+ nir_lower_global_vars_to_local(nir);
+ nir_validate_shader(nir);
- nir_lower_variables_scalar(nir, true, true, true, true);
+ nir_split_var_copies(nir);
+ nir_validate_shader(nir);
+
+ bool progress;
+ do {
+ progress = false;
+ nir_lower_variables(nir);
+ nir_validate_shader(nir);
+ progress |= nir_copy_prop(nir);
+ nir_validate_shader(nir);
+ progress |= nir_opt_dce(nir);
+ nir_validate_shader(nir);
+ progress |= nir_opt_cse(nir);
+ nir_validate_shader(nir);
+ progress |= nir_opt_peephole_select(nir);
+ nir_validate_shader(nir);
+ progress |= nir_opt_algebraic(nir);
+ nir_validate_shader(nir);
+ progress |= nir_opt_constant_folding(nir);
+ nir_validate_shader(nir);
+ } while (progress);
+
+ /* Lower a bunch of stuff */
+ nir_lower_io(nir);
+ nir_validate_shader(nir);
+
+ nir_lower_locals_to_regs(nir);
+ nir_validate_shader(nir);
+
+ nir_remove_dead_variables(nir);
nir_validate_shader(nir);
nir_lower_samplers(nir, shader_prog, shader->base.Program);
nir_lower_atomics(nir);
nir_validate_shader(nir);
- nir_remove_dead_variables(nir);
- nir_opt_global_to_local(nir);
+ nir_lower_to_source_mods(nir);
+ nir_validate_shader(nir);
+ nir_copy_prop(nir);
+ nir_validate_shader(nir);
+ nir_convert_from_ssa(nir);
+ nir_validate_shader(nir);
+ nir_lower_vec_to_movs(nir);
nir_validate_shader(nir);
-
- if (1)
- nir_print_shader(nir, stderr);
/* emit the arrays used for inputs and outputs - load/store intrinsics will
* be converted to reads/writes of these arrays
nir_setup_uniforms(nir);
}
- nir_setup_registers(&nir->registers);
+ nir_globals = ralloc_array(mem_ctx, fs_reg, nir->reg_alloc);
+ foreach_list_typed(nir_register, reg, node, &nir->registers) {
+ unsigned array_elems =
+ reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
+ unsigned size = array_elems * reg->num_components;
+ nir_globals[reg->index] = fs_reg(GRF, virtual_grf_alloc(size));
+ }
/* get the main function and emit it */
nir_foreach_overload(nir, overload) {
reg = *emit_frontfacing_interpolation();
emit(MOV(retype(varying, BRW_REGISTER_TYPE_UD), reg));
} else {
- nir_emit_interpolation(var, &varying);
- }
- }
-}
-
-void
-fs_visitor::nir_emit_interpolation(nir_variable *var, fs_reg *varying)
-{
- brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
- brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
- fs_reg reg = *varying;
- reg.type = brw_type_for_base_type(var->type->get_scalar_type());
-
- unsigned int array_elements;
- const glsl_type *type;
-
- if (var->type->is_array()) {
- array_elements = var->type->length;
- if (array_elements == 0) {
- fail("dereferenced array '%s' has length 0\n", var->name);
- }
- type = var->type->fields.array;
- } else {
- array_elements = 1;
- type = var->type;
- }
-
- glsl_interp_qualifier interpolation_mode =
- determine_interpolation_mode(var, key->flat_shade);
-
- int location = var->data.location;
- for (unsigned int i = 0; i < array_elements; i++) {
- for (unsigned int j = 0; j < type->matrix_columns; j++) {
- if (prog_data->urb_setup[location] == -1) {
- /* If there's no incoming setup data for this slot, don't
- * emit interpolation for it.
- */
- reg.reg_offset += type->vector_elements;
- location++;
- continue;
- }
-
- if (interpolation_mode == INTERP_QUALIFIER_FLAT) {
- /* Constant interpolation (flat shading) case. The SF has
- * handed us defined values in only the constant offset
- * field of the setup reg.
- */
- for (unsigned int k = 0; k < type->vector_elements; k++) {
- struct brw_reg interp = interp_reg(location, k);
- interp = suboffset(interp, 3);
- interp.type = reg.type;
- emit(FS_OPCODE_CINTERP, reg, fs_reg(interp));
- reg.reg_offset++;
- }
- } else {
- /* Smooth/noperspective interpolation case. */
- for (unsigned int k = 0; k < type->vector_elements; k++) {
- struct brw_reg interp = interp_reg(location, k);
- if (brw->needs_unlit_centroid_workaround && var->data.centroid) {
- /* Get the pixel/sample mask into f0 so that we know
- * which pixels are lit. Then, for each channel that is
- * unlit, replace the centroid data with non-centroid
- * data.
- */
- emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
-
- fs_inst *inst;
- inst = emit_linterp(reg, fs_reg(interp), interpolation_mode,
- false, false);
- inst->predicate = BRW_PREDICATE_NORMAL;
- inst->predicate_inverse = true;
- if (brw->has_pln)
- inst->no_dd_clear = true;
-
- inst = emit_linterp(reg, fs_reg(interp), interpolation_mode,
- var->data.centroid && !key->persample_shading,
- var->data.sample || key->persample_shading);
- inst->predicate = BRW_PREDICATE_NORMAL;
- inst->predicate_inverse = false;
- if (brw->has_pln)
- inst->no_dd_check = true;
-
- } else {
- emit_linterp(reg, fs_reg(interp), interpolation_mode,
- var->data.centroid && !key->persample_shading,
- var->data.sample || key->persample_shading);
- }
- if (brw->gen < 6 && interpolation_mode == INTERP_QUALIFIER_SMOOTH) {
- emit(BRW_OPCODE_MUL, reg, reg, this->pixel_w);
- }
- reg.reg_offset++;
- }
-
- }
- location++;
+ emit_general_interpolation(varying, var->name, var->type,
+ (glsl_interp_qualifier) var->data.interpolation,
+ var->data.location, var->data.centroid,
+ var->data.sample);
}
}
}
}
void
-fs_visitor::nir_setup_registers(exec_list *list)
+fs_visitor::nir_emit_impl(nir_function_impl *impl)
{
- foreach_list_typed(nir_register, nir_reg, node, list) {
+ nir_locals = reralloc(mem_ctx, nir_locals, fs_reg, impl->reg_alloc);
+ foreach_list_typed(nir_register, reg, node, &impl->registers) {
unsigned array_elems =
- nir_reg->num_array_elems == 0 ? 1 : nir_reg->num_array_elems;
- unsigned size = array_elems * nir_reg->num_components;
- fs_reg *reg = new(mem_ctx) fs_reg(GRF, virtual_grf_alloc(size));
- _mesa_hash_table_insert(this->nir_reg_ht, nir_reg, reg);
+ reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
+ unsigned size = array_elems * reg->num_components;
+ nir_locals[reg->index] = fs_reg(GRF, virtual_grf_alloc(size));
}
-}
-void
-fs_visitor::nir_emit_impl(nir_function_impl *impl)
-{
- nir_setup_registers(&impl->registers);
nir_emit_cf_list(&impl->body);
}
nir_emit_intrinsic(nir_instr_as_intrinsic(instr));
break;
- case nir_instr_type_texture:
- nir_emit_texture(nir_instr_as_texture(instr));
+ case nir_instr_type_tex:
+ nir_emit_texture(nir_instr_as_tex(instr));
break;
case nir_instr_type_load_const:
- nir_emit_load_const(nir_instr_as_load_const(instr));
+ /* We can hit these, but we do nothing now and use them as
+ * immediates later.
+ */
break;
case nir_instr_type_jump:
struct brw_wm_prog_key *fs_key = (struct brw_wm_prog_key *) this->key;
fs_reg op[3];
- fs_reg dest = retype(get_nir_dest(instr->dest.dest),
- brw_type_for_nir_type(nir_op_infos[instr->op].output_type));
-
- fs_reg result;
- if (instr->has_predicate) {
- result = fs_reg(GRF, virtual_grf_alloc(4));
- result.type = dest.type;
- } else {
- result = dest;
- }
+ fs_reg result = get_nir_dest(instr->dest.dest);
+ result.type = brw_type_for_nir_type(nir_op_infos[instr->op].output_type);
-
- for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
- op[i] = retype(get_nir_alu_src(instr, i),
- brw_type_for_nir_type(nir_op_infos[instr->op].input_types[i]));
- }
+ for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
+ op[i] = get_nir_alu_src(instr, i);
switch (instr->op) {
case nir_op_fmov:
case nir_op_fmul: {
fs_inst *inst = MUL(result, op[0], op[1]);
inst->saturate = instr->dest.saturate;
- emit_percomp(MUL(result, op[0], op[1]), instr->dest.write_mask);
+ emit_percomp(inst, instr->dest.write_mask);
break;
}
emit_percomp(CBIT(result, op[0]), instr->dest.write_mask);
break;
- case nir_op_find_msb: {
- fs_reg temp = fs_reg(this, glsl_type::uvec4_type);
- emit_percomp(FBH(temp, op[0]), instr->dest.write_mask);
+ case nir_op_ufind_msb:
+ case nir_op_ifind_msb: {
+ emit_percomp(FBH(retype(result, BRW_REGISTER_TYPE_UD), op[0]),
+ instr->dest.write_mask);
/* FBH counts from the MSB side, while GLSL's findMSB() wants the count
* from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
* subtract the result from 31 to convert the MSB count into an LSB count.
*/
- emit_percomp(CMP(reg_null_d, temp, fs_reg(~0), BRW_CONDITIONAL_NZ),
+ emit_percomp(CMP(reg_null_d, result, fs_reg(-1), BRW_CONDITIONAL_NZ),
instr->dest.write_mask);
- temp.negate = true;
- fs_inst *inst = ADD(result, temp, fs_reg(31));
+ fs_reg neg_result(result);
+ neg_result.negate = true;
+ fs_inst *inst = ADD(result, neg_result, fs_reg(31));
inst->predicate = BRW_PREDICATE_NORMAL;
emit_percomp(inst, instr->dest.write_mask);
break;
break;
case nir_op_bcsel:
- emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
- emit_percomp(BRW_OPCODE_SEL, result, op[1], op[2],
- instr->dest.write_mask, false, BRW_PREDICATE_NORMAL);
+ for (unsigned i = 0; i < 4; i++) {
+ if (!((instr->dest.write_mask >> i) & 1))
+ continue;
+
+ emit(CMP(reg_null_d, offset(op[0], i), fs_reg(0), BRW_CONDITIONAL_NZ));
+ emit(SEL(offset(result, i), offset(op[1], i), offset(op[2], i)))
+ ->predicate = BRW_PREDICATE_NORMAL;
+ }
break;
default:
unreachable("unhandled instruction");
}
-
- /* emit a predicated move if there was predication */
- if (instr->has_predicate) {
- fs_inst *inst = emit(MOV(reg_null_d,
- retype(get_nir_src(instr->predicate),
- BRW_REGISTER_TYPE_UD)));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
- inst = MOV(dest, result);
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit_percomp(inst, instr->dest.write_mask);
- }
}
fs_reg
fs_visitor::get_nir_src(nir_src src)
{
- struct hash_entry *entry =
- _mesa_hash_table_search(this->nir_reg_ht, src.reg.reg);
- fs_reg reg = *((fs_reg *) entry->data);
- /* to avoid floating-point denorm flushing problems, set the type by
- * default to D - instructions that need floating point semantics will set
- * this to F if they need to
- */
- reg.type = BRW_REGISTER_TYPE_D;
- reg.reg_offset = src.reg.base_offset;
- if (src.reg.indirect) {
- reg.reladdr = new(mem_ctx) fs_reg();
- *reg.reladdr = retype(get_nir_src(*src.reg.indirect),
- BRW_REGISTER_TYPE_D);
- }
+ if (src.is_ssa) {
+ assert(src.ssa->parent_instr->type == nir_instr_type_load_const);
+ nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
+ fs_reg reg(GRF, virtual_grf_alloc(src.ssa->num_components),
+ BRW_REGISTER_TYPE_D);
- return reg;
+ for (unsigned i = 0; i < src.ssa->num_components; ++i)
+ emit(MOV(offset(reg, i), fs_reg(load->value.i[i])));
+
+ return reg;
+ } else {
+ fs_reg reg;
+ if (src.reg.reg->is_global)
+ reg = nir_globals[src.reg.reg->index];
+ else
+ reg = nir_locals[src.reg.reg->index];
+
+ /* to avoid floating-point denorm flushing problems, set the type by
+ * default to D - instructions that need floating point semantics will set
+ * this to F if they need to
+ */
+ reg.type = BRW_REGISTER_TYPE_D;
+ reg.reg_offset = src.reg.base_offset;
+ if (src.reg.indirect) {
+ reg.reladdr = new(mem_ctx) fs_reg();
+ *reg.reladdr = retype(get_nir_src(*src.reg.indirect),
+ BRW_REGISTER_TYPE_D);
+ }
+
+ return reg;
+ }
}
fs_reg
{
fs_reg reg = get_nir_src(instr->src[src].src);
+ reg.type = brw_type_for_nir_type(nir_op_infos[instr->op].input_types[src]);
reg.abs = instr->src[src].abs;
reg.negate = instr->src[src].negate;
if (needs_swizzle) {
/* resolve the swizzle through MOV's */
- fs_reg new_reg = fs_reg(GRF, virtual_grf_alloc(num_components));
+ fs_reg new_reg = fs_reg(GRF, virtual_grf_alloc(num_components), reg.type);
for (unsigned i = 0; i < 4; i++) {
if (!nir_alu_instr_channel_used(instr, src, i))
continue;
- fs_reg dest = new_reg;
- dest.type = reg.type;
- dest.reg_offset = i;
-
- fs_reg src0 = reg;
- src0.reg_offset += instr->src[src].swizzle[i];
-
- emit(MOV(dest, src0));
+ emit(MOV(offset(new_reg, i),
+ offset(reg, instr->src[src].swizzle[i])));
}
return new_reg;
fs_reg
fs_visitor::get_nir_dest(nir_dest dest)
{
- struct hash_entry *entry =
- _mesa_hash_table_search(this->nir_reg_ht, dest.reg.reg);
- fs_reg reg = *((fs_reg *) entry->data);
+ fs_reg reg;
+ if (dest.reg.reg->is_global)
+ reg = nir_globals[dest.reg.reg->index];
+ else
+ reg = nir_locals[dest.reg.reg->index];
+
reg.reg_offset = dest.reg.base_offset;
if (dest.reg.indirect) {
reg.reladdr = new(mem_ctx) fs_reg();
fs_reg dest;
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- if (instr->has_predicate) {
- fs_inst *inst = emit(MOV(reg_null_d,
- retype(get_nir_src(instr->predicate),
- BRW_REGISTER_TYPE_UD)));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
- }
+
+ bool has_indirect = false;
switch (instr->intrinsic) {
case nir_intrinsic_discard: {
fs_reg reg = fs_reg(retype(brw_vec8_grf(payload.sample_mask_in_reg, 0),
BRW_REGISTER_TYPE_D));
dest.type = reg.type;
- fs_inst *inst = MOV(dest, reg);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
+ emit(MOV(dest, reg));
break;
}
break;
}
- case nir_intrinsic_load_uniform_vec1:
- case nir_intrinsic_load_uniform_vec2:
- case nir_intrinsic_load_uniform_vec3:
- case nir_intrinsic_load_uniform_vec4: {
- unsigned index = 0;
- for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].dest_components; j++) {
- fs_reg src = nir_uniforms;
- src.reg_offset = instr->const_index[0] + index;
- src.type = dest.type;
- index++;
-
- fs_inst *inst = MOV(dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
- dest.reg_offset++;
- }
- }
- break;
- }
-
- case nir_intrinsic_load_uniform_vec1_indirect:
- case nir_intrinsic_load_uniform_vec2_indirect:
- case nir_intrinsic_load_uniform_vec3_indirect:
- case nir_intrinsic_load_uniform_vec4_indirect: {
+ case nir_intrinsic_load_uniform_indirect:
+ has_indirect = true;
+ case nir_intrinsic_load_uniform: {
unsigned index = 0;
for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].dest_components; j++) {
+ for (unsigned j = 0; j < instr->num_components; j++) {
fs_reg src = nir_uniforms;
src.reg_offset = instr->const_index[0] + index;
- src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
- src.reladdr->type = BRW_REGISTER_TYPE_D;
+ if (has_indirect)
+ src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
src.type = dest.type;
index++;
- fs_inst *inst = MOV(dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
+ emit(MOV(dest, src));
dest.reg_offset++;
}
}
break;
}
- case nir_intrinsic_load_ubo_vec1:
- case nir_intrinsic_load_ubo_vec2:
- case nir_intrinsic_load_ubo_vec3:
- case nir_intrinsic_load_ubo_vec4: {
- fs_reg surf_index = fs_reg(prog_data->binding_table.ubo_start +
- (unsigned) instr->const_index[0]);
- fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
- packed_consts.type = dest.type;
+ case nir_intrinsic_load_ubo_indirect:
+ has_indirect = true;
+ case nir_intrinsic_load_ubo: {
+ nir_const_value *const_index = nir_src_as_const_value(instr->src[0]);
+ fs_reg surf_index;
- fs_reg const_offset_reg = fs_reg((unsigned) instr->const_index[1] & ~15);
- emit(new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
- packed_consts, surf_index, const_offset_reg));
-
- for (unsigned i = 0;
- i < nir_intrinsic_infos[instr->intrinsic].dest_components; i++) {
- packed_consts.set_smear(instr->const_index[1] % 16 / 4 + i);
-
- /* The std140 packing rules don't allow vectors to cross 16-byte
- * boundaries, and a reg is 32 bytes.
+ if (const_index) {
+ surf_index = fs_reg(stage_prog_data->binding_table.ubo_start +
+ const_index->u[0]);
+ } else {
+ /* The block index is not a constant. Evaluate the index expression
+ * per-channel and add the base UBO index; the generator will select
+ * a value from any live channel.
*/
- assert(packed_consts.subreg_offset < 32);
+ surf_index = fs_reg(this, glsl_type::uint_type);
+ emit(ADD(surf_index, get_nir_src(instr->src[0]),
+ fs_reg(stage_prog_data->binding_table.ubo_start)))
+ ->force_writemask_all = true;
- fs_inst *inst = MOV(dest, packed_consts);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
-
- dest.reg_offset++;
+ /* Assume this may touch any UBO. It would be nice to provide
+ * a tighter bound, but the array information is already lowered away.
+ */
+ brw_mark_surface_used(prog_data,
+ stage_prog_data->binding_table.ubo_start +
+ shader_prog->NumUniformBlocks - 1);
}
- break;
- }
- case nir_intrinsic_load_ubo_vec1_indirect:
- case nir_intrinsic_load_ubo_vec2_indirect:
- case nir_intrinsic_load_ubo_vec3_indirect:
- case nir_intrinsic_load_ubo_vec4_indirect: {
- fs_reg surf_index = fs_reg(prog_data->binding_table.ubo_start +
- instr->const_index[0]);
- /* Turn the byte offset into a dword offset. */
- unsigned base_offset = instr->const_index[1] / 4;
- fs_reg offset = fs_reg(this, glsl_type::int_type);
- emit(SHR(offset, retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_D),
- fs_reg(2)));
-
- for (unsigned i = 0;
- i < nir_intrinsic_infos[instr->intrinsic].dest_components; i++) {
- exec_list list = VARYING_PULL_CONSTANT_LOAD(dest, surf_index,
- offset, base_offset + i);
- fs_inst *last_inst = (fs_inst *) list.get_tail();
- if (instr->has_predicate)
- last_inst->predicate = BRW_PREDICATE_NORMAL;
- emit(list);
+ if (has_indirect) {
+ /* Turn the byte offset into a dword offset. */
+ fs_reg base_offset = fs_reg(this, glsl_type::int_type);
+ emit(SHR(base_offset, retype(get_nir_src(instr->src[1]),
+ BRW_REGISTER_TYPE_D),
+ fs_reg(2)));
+
+ unsigned vec4_offset = instr->const_index[0] / 4;
+ for (int i = 0; i < instr->num_components; i++)
+ emit(VARYING_PULL_CONSTANT_LOAD(offset(dest, i), surf_index,
+ base_offset, vec4_offset + i));
+ } else {
+ fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
+ packed_consts.type = dest.type;
- dest.reg_offset++;
- }
- break;
- }
+ fs_reg const_offset_reg((unsigned) instr->const_index[0] & ~15);
+ emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, packed_consts,
+ surf_index, const_offset_reg);
- case nir_intrinsic_load_input_vec1:
- case nir_intrinsic_load_input_vec2:
- case nir_intrinsic_load_input_vec3:
- case nir_intrinsic_load_input_vec4: {
- unsigned index = 0;
- for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].dest_components; j++) {
- fs_reg src = nir_inputs;
- src.reg_offset = instr->const_index[0] + index;
- src.type = dest.type;
- index++;
+ for (unsigned i = 0; i < instr->num_components; i++) {
+ packed_consts.set_smear(instr->const_index[0] % 16 / 4 + i);
- fs_inst *inst = MOV(dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
+ /* The std140 packing rules don't allow vectors to cross 16-byte
+ * boundaries, and a reg is 32 bytes.
+ */
+ assert(packed_consts.subreg_offset < 32);
+
+ emit(MOV(dest, packed_consts));
dest.reg_offset++;
}
}
break;
}
- case nir_intrinsic_load_input_vec1_indirect:
- case nir_intrinsic_load_input_vec2_indirect:
- case nir_intrinsic_load_input_vec3_indirect:
- case nir_intrinsic_load_input_vec4_indirect: {
+ case nir_intrinsic_load_input_indirect:
+ has_indirect = true;
+ case nir_intrinsic_load_input: {
unsigned index = 0;
for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].dest_components; j++) {
+ for (unsigned j = 0; j < instr->num_components; j++) {
fs_reg src = nir_inputs;
src.reg_offset = instr->const_index[0] + index;
- src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
- src.reladdr->type = BRW_REGISTER_TYPE_D;
+ if (has_indirect)
+ src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
src.type = dest.type;
index++;
- fs_inst *inst = MOV(dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
+ emit(MOV(dest, src));
dest.reg_offset++;
}
}
break;
}
- case nir_intrinsic_store_output_vec1:
- case nir_intrinsic_store_output_vec2:
- case nir_intrinsic_store_output_vec3:
- case nir_intrinsic_store_output_vec4: {
- fs_reg src = get_nir_src(instr->src[0]);
- unsigned index = 0;
- for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].src_components[0]; j++) {
- fs_reg new_dest = nir_outputs;
- new_dest.reg_offset = instr->const_index[0] + index;
- new_dest.type = src.type;
- index++;
- fs_inst *inst = MOV(new_dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
- src.reg_offset++;
+ /* Handle ARB_gpu_shader5 interpolation intrinsics
+ *
+ * It's worth a quick word of explanation as to why we handle the full
+ * variable-based interpolation intrinsic rather than a lowered version
+ * with like we do for other inputs. We have to do that because the way
+ * we set up inputs doesn't allow us to use the already setup inputs for
+ * interpolation. At the beginning of the shader, we go through all of
+ * the input variables and do the initial interpolation and put it in
+ * the nir_inputs array based on its location as determined in
+ * nir_lower_io. If the input isn't used, dead code cleans up and
+ * everything works fine. However, when we get to the ARB_gpu_shader5
+ * interpolation intrinsics, we need to reinterpolate the input
+ * differently. If we used an intrinsic that just had an index it would
+ * only give us the offset into the nir_inputs array. However, this is
+ * useless because that value is post-interpolation and we need
+ * pre-interpolation. In order to get the actual location of the bits
+ * we get from the vertex fetching hardware, we need the variable.
+ */
+ case nir_intrinsic_interp_var_at_centroid:
+ case nir_intrinsic_interp_var_at_sample:
+ case nir_intrinsic_interp_var_at_offset: {
+ /* in SIMD16 mode, the pixel interpolator returns coords interleaved
+ * 8 channels at a time, same as the barycentric coords presented in
+ * the FS payload. this requires a bit of extra work to support.
+ */
+ no16("interpolate_at_* not yet supported in SIMD16 mode.");
+
+ fs_reg dst_x(GRF, virtual_grf_alloc(2), BRW_REGISTER_TYPE_F);
+ fs_reg dst_y = offset(dst_x, 1);
+
+ /* For most messages, we need one reg of ignored data; the hardware
+ * requires mlen==1 even when there is no payload. in the per-slot
+ * offset case, we'll replace this with the proper source data.
+ */
+ fs_reg src(this, glsl_type::float_type);
+ int mlen = 1; /* one reg unless overriden */
+ fs_inst *inst;
+
+ switch (instr->intrinsic) {
+ case nir_intrinsic_interp_var_at_centroid:
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_CENTROID, dst_x, src, fs_reg(0u));
+ break;
+
+ case nir_intrinsic_interp_var_at_sample: {
+ /* XXX: We should probably handle non-constant sample id's */
+ nir_const_value *const_sample = nir_src_as_const_value(instr->src[0]);
+ assert(const_sample);
+ unsigned msg_data = const_sample ? const_sample->i[0] << 4 : 0;
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_x, src,
+ fs_reg(msg_data));
+ break;
+ }
+
+ case nir_intrinsic_interp_var_at_offset: {
+ nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
+
+ if (const_offset) {
+ unsigned off_x = MIN2((int)(const_offset->f[0] * 16), 7) & 0xf;
+ unsigned off_y = MIN2((int)(const_offset->f[1] * 16), 7) & 0xf;
+
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_x, src,
+ fs_reg(off_x | (off_y << 4)));
+ } else {
+ src = fs_reg(this, glsl_type::ivec2_type);
+ fs_reg offset_src = retype(get_nir_src(instr->src[0]),
+ BRW_REGISTER_TYPE_F);
+ for (int i = 0; i < 2; i++) {
+ fs_reg temp(this, glsl_type::float_type);
+ emit(MUL(temp, offset(offset_src, i), fs_reg(16.0f)));
+ fs_reg itemp(this, glsl_type::int_type);
+ emit(MOV(itemp, temp)); /* float to int */
+
+ /* Clamp the upper end of the range to +7/16.
+ * ARB_gpu_shader5 requires that we support a maximum offset
+ * of +0.5, which isn't representable in a S0.4 value -- if
+ * we didn't clamp it, we'd end up with -8/16, which is the
+ * opposite of what the shader author wanted.
+ *
+ * This is legal due to ARB_gpu_shader5's quantization
+ * rules:
+ *
+ * "Not all values of <offset> may be supported; x and y
+ * offsets may be rounded to fixed-point values with the
+ * number of fraction bits given by the
+ * implementation-dependent constant
+ * FRAGMENT_INTERPOLATION_OFFSET_BITS"
+ */
+
+ emit(BRW_OPCODE_SEL, offset(src, i), itemp, fs_reg(7))
+ ->conditional_mod = BRW_CONDITIONAL_L; /* min(src2, 7) */
+ }
+
+ mlen = 2;
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, dst_x, src,
+ fs_reg(0u));
}
+ break;
+ }
+
+ default:
+ unreachable("Invalid intrinsic");
+ }
+
+ inst->mlen = mlen;
+ inst->regs_written = 2; /* 2 floats per slot returned */
+ inst->pi_noperspective = instr->variables[0]->var->data.interpolation ==
+ INTERP_QUALIFIER_NOPERSPECTIVE;
+
+ for (unsigned j = 0; j < instr->num_components; j++) {
+ fs_reg src = interp_reg(instr->variables[0]->var->data.location, j);
+ src.type = dest.type;
+
+ emit(FS_OPCODE_LINTERP, dest, dst_x, dst_y, src);
+ dest.reg_offset++;
}
break;
}
- case nir_intrinsic_store_output_vec1_indirect:
- case nir_intrinsic_store_output_vec2_indirect:
- case nir_intrinsic_store_output_vec3_indirect:
- case nir_intrinsic_store_output_vec4_indirect: {
+ case nir_intrinsic_store_output_indirect:
+ has_indirect = true;
+ case nir_intrinsic_store_output: {
fs_reg src = get_nir_src(instr->src[0]);
- fs_reg indirect = get_nir_src(instr->src[1]);
unsigned index = 0;
for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].src_components[0]; j++) {
+ for (unsigned j = 0; j < instr->num_components; j++) {
fs_reg new_dest = nir_outputs;
new_dest.reg_offset = instr->const_index[0] + index;
- new_dest.reladdr = new(mem_ctx) fs_reg(indirect);
+ if (has_indirect)
+ src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[1]));
new_dest.type = src.type;
index++;
- fs_inst *inst = MOV(new_dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
emit(MOV(new_dest, src));
src.reg_offset++;
}
{
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
unsigned sampler = instr->sampler_index;
+ fs_reg sampler_reg(sampler);
/* FINISHME: We're failing to recompile our programs when the sampler is
* updated. This only matters for the texture rectangle scale parameters
break;
case nir_tex_src_projector:
unreachable("should be lowered");
- case nir_tex_src_sampler_index:
- unreachable("not yet supported");
+
+ case nir_tex_src_sampler_offset: {
+ /* Figure out the highest possible sampler index and mark it as used */
+ uint32_t max_used = sampler + instr->sampler_array_size - 1;
+ if (instr->op == nir_texop_tg4 && brw->gen < 8) {
+ max_used += stage_prog_data->binding_table.gather_texture_start;
+ } else {
+ max_used += stage_prog_data->binding_table.texture_start;
+ }
+ brw_mark_surface_used(prog_data, max_used);
+
+ /* Emit code to evaluate the actual indexing expression */
+ sampler_reg = fs_reg(this, glsl_type::uint_type);
+ emit(ADD(sampler_reg, src, fs_reg(sampler)))
+ ->force_writemask_all = true;
+ break;
+ }
+
default:
unreachable("unknown texture source");
}
if (instr->op == nir_texop_txf_ms) {
if (brw->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
- mcs = emit_mcs_fetch(coordinate, instr->coord_components, fs_reg(sampler));
+ mcs = emit_mcs_fetch(coordinate, instr->coord_components, sampler_reg);
else
mcs = fs_reg(0u);
}
emit_texture(op, dest_type, coordinate, instr->coord_components,
shadow_comparitor, lod, lod2, lod_components, sample_index,
offset, offset_components, mcs, gather_component,
- is_cube_array, is_rect, sampler, fs_reg(sampler), texunit);
+ is_cube_array, is_rect, sampler, sampler_reg, texunit);
fs_reg dest = get_nir_dest(instr->dest);
dest.type = this->result.type;
emit_percomp(MOV(dest, this->result), (1 << num_components) - 1);
}
-void
-fs_visitor::nir_emit_load_const(nir_load_const_instr *instr)
-{
- fs_reg dest = get_nir_dest(instr->dest);
- dest.type = BRW_REGISTER_TYPE_UD;
- if (instr->array_elems == 0) {
- for (unsigned i = 0; i < instr->num_components; i++) {
- emit(MOV(dest, fs_reg(instr->value.u[i])));
- dest.reg_offset++;
- }
- } else {
- for (unsigned i = 0; i < instr->array_elems; i++) {
- for (unsigned j = 0; j < instr->num_components; j++) {
- emit(MOV(dest, fs_reg(instr->array[i].u[j])));
- dest.reg_offset++;
- }
- }
- }
-}
-
void
fs_visitor::nir_emit_jump(nir_jump_instr *instr)
{
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