#include "glsl/ir.h"
#include "glsl/ir_optimization.h"
#include "glsl/nir/glsl_to_nir.h"
+#include "main/shaderimage.h"
#include "program/prog_to_nir.h"
#include "brw_fs.h"
+#include "brw_fs_surface_builder.h"
#include "brw_nir.h"
using namespace brw;
/* emit the arrays used for inputs and outputs - load/store intrinsics will
* be converted to reads/writes of these arrays
*/
-
- if (nir->num_inputs > 0) {
- nir_inputs = bld.vgrf(BRW_REGISTER_TYPE_F, nir->num_inputs);
- nir_setup_inputs(nir);
- }
-
- if (nir->num_outputs > 0) {
- nir_outputs = bld.vgrf(BRW_REGISTER_TYPE_F, nir->num_outputs);
- nir_setup_outputs(nir);
- }
-
- if (nir->num_uniforms > 0) {
- nir_setup_uniforms(nir);
- }
-
+ nir_setup_inputs(nir);
+ nir_setup_outputs(nir);
+ nir_setup_uniforms(nir);
nir_emit_system_values(nir);
- nir_globals = ralloc_array(mem_ctx, fs_reg, nir->reg_alloc);
- foreach_list_typed(nir_register, reg, node, &nir->registers) {
- unsigned array_elems =
- reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
- unsigned size = array_elems * reg->num_components;
- nir_globals[reg->index] = bld.vgrf(BRW_REGISTER_TYPE_F, size);
- }
-
/* get the main function and emit it */
nir_foreach_overload(nir, overload) {
assert(strcmp(overload->function->name, "main") == 0);
void
fs_visitor::nir_setup_inputs(nir_shader *shader)
{
+ nir_inputs = bld.vgrf(BRW_REGISTER_TYPE_F, shader->num_inputs);
+
foreach_list_typed(nir_variable, var, node, &shader->inputs) {
enum brw_reg_type type = brw_type_for_base_type(var->type);
fs_reg input = offset(nir_inputs, bld, var->data.driver_location);
* So, we need to copy from fs_reg(ATTR, var->location) to
* offset(nir_inputs, var->data.driver_location).
*/
- unsigned components = var->type->without_array()->components();
+ const glsl_type *const t = var->type->without_array();
+ const unsigned components = t->components();
+ const unsigned cols = t->matrix_columns;
+ const unsigned elts = t->vector_elements;
unsigned array_length = var->type->is_array() ? var->type->length : 1;
for (unsigned i = 0; i < array_length; i++) {
- for (unsigned j = 0; j < components; j++) {
- bld.MOV(retype(offset(input, bld, components * i + j), type),
- offset(fs_reg(ATTR, var->data.location + i, type), bld, j));
+ for (unsigned j = 0; j < cols; j++) {
+ for (unsigned k = 0; k < elts; k++) {
+ bld.MOV(offset(retype(input, type), bld,
+ components * i + elts * j + k),
+ offset(fs_reg(ATTR, var->data.location + i, type),
+ bld, 4 * j + k));
+ }
}
}
break;
}
case MESA_SHADER_GEOMETRY:
case MESA_SHADER_COMPUTE:
+ case MESA_SHADER_TESS_CTRL:
+ case MESA_SHADER_TESS_EVAL:
unreachable("fs_visitor not used for these stages yet.");
break;
case MESA_SHADER_FRAGMENT:
{
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+ nir_outputs = bld.vgrf(BRW_REGISTER_TYPE_F, shader->num_outputs);
+
foreach_list_typed(nir_variable, var, node, &shader->outputs) {
fs_reg reg = offset(nir_outputs, bld, var->data.driver_location);
var->type->is_array() ? var->type->fields.array->vector_elements
: var->type->vector_elements;
- if (stage == MESA_SHADER_VERTEX) {
+ switch (stage) {
+ case MESA_SHADER_VERTEX:
for (int i = 0; i < ALIGN(type_size(var->type), 4) / 4; i++) {
int output = var->data.location + i;
this->outputs[output] = offset(reg, bld, 4 * i);
this->output_components[output] = vector_elements;
}
- } else if (var->data.index > 0) {
- assert(var->data.location == FRAG_RESULT_DATA0);
- assert(var->data.index == 1);
- this->dual_src_output = reg;
- this->do_dual_src = true;
- } else if (var->data.location == FRAG_RESULT_COLOR) {
- /* Writing gl_FragColor outputs to all color regions. */
- for (unsigned int i = 0; i < MAX2(key->nr_color_regions, 1); i++) {
- this->outputs[i] = reg;
- this->output_components[i] = 4;
- }
- } else if (var->data.location == FRAG_RESULT_DEPTH) {
- this->frag_depth = reg;
- } else if (var->data.location == FRAG_RESULT_SAMPLE_MASK) {
- this->sample_mask = reg;
- } else {
- /* gl_FragData or a user-defined FS output */
- assert(var->data.location >= FRAG_RESULT_DATA0 &&
- var->data.location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);
-
- /* General color output. */
- for (unsigned int i = 0; i < MAX2(1, var->type->length); i++) {
- int output = var->data.location - FRAG_RESULT_DATA0 + i;
- this->outputs[output] = offset(reg, bld, vector_elements * i);
- this->output_components[output] = vector_elements;
+ break;
+ case MESA_SHADER_FRAGMENT:
+ if (var->data.index > 0) {
+ assert(var->data.location == FRAG_RESULT_DATA0);
+ assert(var->data.index == 1);
+ this->dual_src_output = reg;
+ this->do_dual_src = true;
+ } else if (var->data.location == FRAG_RESULT_COLOR) {
+ /* Writing gl_FragColor outputs to all color regions. */
+ for (unsigned int i = 0; i < MAX2(key->nr_color_regions, 1); i++) {
+ this->outputs[i] = reg;
+ this->output_components[i] = 4;
+ }
+ } else if (var->data.location == FRAG_RESULT_DEPTH) {
+ this->frag_depth = reg;
+ } else if (var->data.location == FRAG_RESULT_SAMPLE_MASK) {
+ this->sample_mask = reg;
+ } else {
+ /* gl_FragData or a user-defined FS output */
+ assert(var->data.location >= FRAG_RESULT_DATA0 &&
+ var->data.location < FRAG_RESULT_DATA0+BRW_MAX_DRAW_BUFFERS);
+
+ /* General color output. */
+ for (unsigned int i = 0; i < MAX2(1, var->type->length); i++) {
+ int output = var->data.location - FRAG_RESULT_DATA0 + i;
+ this->outputs[output] = offset(reg, bld, vector_elements * i);
+ this->output_components[output] = vector_elements;
+ }
}
+ break;
+ default:
+ unreachable("unhandled shader stage");
}
}
}
void
fs_visitor::nir_setup_uniforms(nir_shader *shader)
{
- uniforms = shader->num_uniforms;
num_direct_uniforms = shader->num_direct_uniforms;
+ if (dispatch_width != 8)
+ return;
+
/* We split the uniform register file in half. The first half is
* entirely direct uniforms. The second half is indirect.
*/
- param_size[0] = num_direct_uniforms;
+ if (num_direct_uniforms > 0)
+ param_size[0] = num_direct_uniforms;
if (shader->num_uniforms > num_direct_uniforms)
param_size[num_direct_uniforms] = shader->num_uniforms - num_direct_uniforms;
- if (dispatch_width != 8)
- return;
+ uniforms = shader->num_uniforms;
if (shader_prog) {
foreach_list_typed(nir_variable, var, node, &shader->uniforms) {
continue;
}
- unsigned slots = storage->type->component_slots();
- if (storage->array_elements)
- slots *= storage->array_elements;
+ if (storage->type->is_image()) {
+ /* Images don't get a valid location assigned by nir_lower_io()
+ * because their size is driver-specific, so we need to allocate
+ * space for them here at the end of the parameter array.
+ */
+ var->data.driver_location = uniforms;
+ param_size[uniforms] =
+ BRW_IMAGE_PARAM_SIZE * MAX2(storage->array_elements, 1);
+
+ setup_image_uniform_values(storage);
+ } else {
+ unsigned slots = storage->type->component_slots();
+ if (storage->array_elements)
+ slots *= storage->array_elements;
- for (unsigned i = 0; i < slots; i++) {
- stage_prog_data->param[index++] = &storage->storage[i];
+ for (unsigned i = 0; i < slots; i++) {
+ stage_prog_data->param[index++] = &storage->storage[i];
+ }
}
}
-
- /* Make sure we actually initialized the right amount of stuff here. */
- assert(var->data.driver_location + var->type->component_slots() == index);
}
void
bld.emit(BRW_OPCODE_ENDIF);
- if (!try_replace_with_sel() && devinfo->gen < 6) {
- no16("Can't support (non-uniform) control flow on SIMD16\n");
- }
+ try_replace_with_sel();
}
void
fs_visitor::nir_emit_loop(nir_loop *loop)
{
- if (devinfo->gen < 6) {
- no16("Can't support (non-uniform) control flow on SIMD16\n");
- }
-
bld.emit(BRW_OPCODE_DO);
nir_emit_cf_list(&loop->body);
}
}
-static brw_reg_type
-brw_type_for_nir_type(nir_alu_type type)
-{
- switch (type) {
- case nir_type_unsigned:
- return BRW_REGISTER_TYPE_UD;
- case nir_type_bool:
- case nir_type_int:
- return BRW_REGISTER_TYPE_D;
- case nir_type_float:
- return BRW_REGISTER_TYPE_F;
- default:
- unreachable("unknown type");
- }
-
- return BRW_REGISTER_TYPE_F;
-}
-
bool
fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
const fs_reg &result)
break;
case nir_op_imul_high:
- case nir_op_umul_high: {
- if (devinfo->gen >= 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width), result.type);
-
- fs_inst *mul = bld.MUL(acc, op[0], op[1]);
- bld.MACH(result, op[0], op[1]);
-
- /* Until Gen8, integer multiplies read 32-bits from one source, and
- * 16-bits from the other, and relying on the MACH instruction to
- * generate the high bits of the result.
- *
- * On Gen8, the multiply instruction does a full 32x32-bit multiply,
- * but in order to do a 64x64-bit multiply we have to simulate the
- * previous behavior and then use a MACH instruction.
- *
- * FINISHME: Don't use source modifiers on src1.
- */
- if (devinfo->gen >= 8) {
- assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
- mul->src[1].type == BRW_REGISTER_TYPE_UD);
- if (mul->src[1].type == BRW_REGISTER_TYPE_D) {
- mul->src[1].type = BRW_REGISTER_TYPE_W;
- mul->src[1].stride = 2;
- } else {
- mul->src[1].type = BRW_REGISTER_TYPE_UW;
- mul->src[1].stride = 2;
- }
- }
+ case nir_op_umul_high:
+ bld.emit(SHADER_OPCODE_MULH, result, op[0], op[1]);
break;
- }
case nir_op_idiv:
case nir_op_udiv:
bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
break;
- case nir_op_uadd_carry: {
- if (devinfo->gen >= 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- bld.ADDC(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
- break;
- }
-
- case nir_op_usub_borrow: {
- if (devinfo->gen >= 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
+ case nir_op_uadd_carry:
+ unreachable("Should have been lowered by carry_to_arith().");
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- bld.SUBB(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
- break;
- }
+ case nir_op_usub_borrow:
+ unreachable("Should have been lowered by borrow_to_arith().");
case nir_op_umod:
bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
case nir_op_inot:
if (devinfo->gen >= 8) {
- resolve_source_modifiers(&op[0]);
+ op[0] = resolve_source_modifiers(op[0]);
}
bld.NOT(result, op[0]);
break;
case nir_op_ixor:
if (devinfo->gen >= 8) {
- resolve_source_modifiers(&op[0]);
- resolve_source_modifiers(&op[1]);
+ op[0] = resolve_source_modifiers(op[0]);
+ op[1] = resolve_source_modifiers(op[1]);
}
bld.XOR(result, op[0], op[1]);
break;
case nir_op_ior:
if (devinfo->gen >= 8) {
- resolve_source_modifiers(&op[0]);
- resolve_source_modifiers(&op[1]);
+ op[0] = resolve_source_modifiers(op[0]);
+ op[1] = resolve_source_modifiers(op[1]);
}
bld.OR(result, op[0], op[1]);
break;
case nir_op_iand:
if (devinfo->gen >= 8) {
- resolve_source_modifiers(&op[0]);
- resolve_source_modifiers(&op[1]);
+ op[0] = resolve_source_modifiers(op[0]);
+ op[1] = resolve_source_modifiers(op[1]);
}
bld.AND(result, op[0], op[1]);
break;
break;
case nir_op_b2i:
- bld.AND(result, op[0], fs_reg(1));
- break;
case nir_op_b2f:
- bld.AND(retype(result, BRW_REGISTER_TYPE_UD), op[0], fs_reg(0x3f800000u));
+ bld.MOV(result, negate(op[0]));
break;
case nir_op_f2b:
unsigned base_offset, nir_src *indirect)
{
fs_reg reg;
- if (nir_reg->is_global)
- reg = v->nir_globals[nir_reg->index];
- else
- reg = v->nir_locals[nir_reg->index];
+
+ assert(!nir_reg->is_global);
+
+ reg = v->nir_locals[nir_reg->index];
reg = offset(reg, v->bld, base_offset * nir_reg->num_components);
if (indirect) {
dest.reg.indirect);
}
+fs_reg
+fs_visitor::get_nir_image_deref(const nir_deref_var *deref)
+{
+ fs_reg image(UNIFORM, deref->var->data.driver_location,
+ BRW_REGISTER_TYPE_UD);
+
+ if (deref->deref.child) {
+ const nir_deref_array *deref_array =
+ nir_deref_as_array(deref->deref.child);
+ assert(deref->deref.child->deref_type == nir_deref_type_array &&
+ deref_array->deref.child == NULL);
+ const unsigned size = glsl_get_length(deref->var->type);
+ const unsigned base = MIN2(deref_array->base_offset, size - 1);
+
+ image = offset(image, bld, base * BRW_IMAGE_PARAM_SIZE);
+
+ if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
+ fs_reg *tmp = new(mem_ctx) fs_reg(vgrf(glsl_type::int_type));
+
+ if (devinfo->gen == 7 && !devinfo->is_haswell) {
+ /* IVB hangs when trying to access an invalid surface index with
+ * the dataport. According to the spec "if the index used to
+ * select an individual element is negative or greater than or
+ * equal to the size of the array, the results of the operation
+ * are undefined but may not lead to termination" -- which is one
+ * of the possible outcomes of the hang. Clamp the index to
+ * prevent access outside of the array bounds.
+ */
+ bld.emit_minmax(*tmp, retype(get_nir_src(deref_array->indirect),
+ BRW_REGISTER_TYPE_UD),
+ fs_reg(size - base - 1), BRW_CONDITIONAL_L);
+ } else {
+ bld.MOV(*tmp, get_nir_src(deref_array->indirect));
+ }
+
+ bld.MUL(*tmp, *tmp, fs_reg(BRW_IMAGE_PARAM_SIZE));
+ image.reladdr = tmp;
+ }
+ }
+
+ return image;
+}
+
void
fs_visitor::emit_percomp(const fs_builder &bld, const fs_inst &inst,
unsigned wr_mask)
}
}
+/**
+ * Get the matching channel register datatype for an image intrinsic of the
+ * specified GLSL image type.
+ */
+static brw_reg_type
+get_image_base_type(const glsl_type *type)
+{
+ switch ((glsl_base_type)type->sampler_type) {
+ case GLSL_TYPE_UINT:
+ return BRW_REGISTER_TYPE_UD;
+ case GLSL_TYPE_INT:
+ return BRW_REGISTER_TYPE_D;
+ case GLSL_TYPE_FLOAT:
+ return BRW_REGISTER_TYPE_F;
+ default:
+ unreachable("Not reached.");
+ }
+}
+
+/**
+ * Get the appropriate atomic op for an image atomic intrinsic.
+ */
+static unsigned
+get_image_atomic_op(nir_intrinsic_op op, const glsl_type *type)
+{
+ switch (op) {
+ case nir_intrinsic_image_atomic_add:
+ return BRW_AOP_ADD;
+ case nir_intrinsic_image_atomic_min:
+ return (get_image_base_type(type) == BRW_REGISTER_TYPE_D ?
+ BRW_AOP_IMIN : BRW_AOP_UMIN);
+ case nir_intrinsic_image_atomic_max:
+ return (get_image_base_type(type) == BRW_REGISTER_TYPE_D ?
+ BRW_AOP_IMAX : BRW_AOP_UMAX);
+ case nir_intrinsic_image_atomic_and:
+ return BRW_AOP_AND;
+ case nir_intrinsic_image_atomic_or:
+ return BRW_AOP_OR;
+ case nir_intrinsic_image_atomic_xor:
+ return BRW_AOP_XOR;
+ case nir_intrinsic_image_atomic_exchange:
+ return BRW_AOP_MOV;
+ case nir_intrinsic_image_atomic_comp_swap:
+ return BRW_AOP_CMPWR;
+ default:
+ unreachable("Not reachable.");
+ }
+}
+
void
fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr)
{
case nir_intrinsic_atomic_counter_inc:
case nir_intrinsic_atomic_counter_dec:
case nir_intrinsic_atomic_counter_read: {
- unsigned surf_index = prog_data->binding_table.abo_start +
- (unsigned) instr->const_index[0];
- fs_reg offset = fs_reg(get_nir_src(instr->src[0]));
+ using namespace surface_access;
+ /* Get the arguments of the atomic intrinsic. */
+ const fs_reg offset = get_nir_src(instr->src[0]);
+ const unsigned surface = (stage_prog_data->binding_table.abo_start +
+ instr->const_index[0]);
+ fs_reg tmp;
+
+ /* Emit a surface read or atomic op. */
switch (instr->intrinsic) {
- case nir_intrinsic_atomic_counter_inc:
- emit_untyped_atomic(BRW_AOP_INC, surf_index, dest, offset,
- fs_reg(), fs_reg());
- break;
- case nir_intrinsic_atomic_counter_dec:
- emit_untyped_atomic(BRW_AOP_PREDEC, surf_index, dest, offset,
- fs_reg(), fs_reg());
- break;
- case nir_intrinsic_atomic_counter_read:
- emit_untyped_surface_read(surf_index, dest, offset);
- break;
- default:
- unreachable("Unreachable");
+ case nir_intrinsic_atomic_counter_read:
+ tmp = emit_untyped_read(bld, fs_reg(surface), offset, 1, 1);
+ break;
+
+ case nir_intrinsic_atomic_counter_inc:
+ tmp = emit_untyped_atomic(bld, fs_reg(surface), offset, fs_reg(),
+ fs_reg(), 1, 1, BRW_AOP_INC);
+ break;
+
+ case nir_intrinsic_atomic_counter_dec:
+ tmp = emit_untyped_atomic(bld, fs_reg(surface), offset, fs_reg(),
+ fs_reg(), 1, 1, BRW_AOP_PREDEC);
+ break;
+
+ default:
+ unreachable("Unreachable");
}
+
+ /* Assign the result. */
+ bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), tmp);
+
+ /* Mark the surface as used. */
+ brw_mark_surface_used(stage_prog_data, surface);
+ break;
+ }
+
+ case nir_intrinsic_image_load:
+ case nir_intrinsic_image_store:
+ case nir_intrinsic_image_atomic_add:
+ case nir_intrinsic_image_atomic_min:
+ case nir_intrinsic_image_atomic_max:
+ case nir_intrinsic_image_atomic_and:
+ case nir_intrinsic_image_atomic_or:
+ case nir_intrinsic_image_atomic_xor:
+ case nir_intrinsic_image_atomic_exchange:
+ case nir_intrinsic_image_atomic_comp_swap: {
+ using namespace image_access;
+
+ /* Get the referenced image variable and type. */
+ const nir_variable *var = instr->variables[0]->var;
+ const glsl_type *type = var->type->without_array();
+ const brw_reg_type base_type = get_image_base_type(type);
+
+ /* Get some metadata from the image intrinsic. */
+ const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
+ const unsigned arr_dims = type->sampler_array ? 1 : 0;
+ const unsigned surf_dims = type->coordinate_components() - arr_dims;
+ const mesa_format format =
+ (var->data.image.write_only ? MESA_FORMAT_NONE :
+ _mesa_get_shader_image_format(var->data.image.format));
+
+ /* Get the arguments of the image intrinsic. */
+ const fs_reg image = get_nir_image_deref(instr->variables[0]);
+ const fs_reg addr = retype(get_nir_src(instr->src[0]),
+ BRW_REGISTER_TYPE_UD);
+ const fs_reg src0 = (info->num_srcs >= 3 ?
+ retype(get_nir_src(instr->src[2]), base_type) :
+ fs_reg());
+ const fs_reg src1 = (info->num_srcs >= 4 ?
+ retype(get_nir_src(instr->src[3]), base_type) :
+ fs_reg());
+ fs_reg tmp;
+
+ /* Emit an image load, store or atomic op. */
+ if (instr->intrinsic == nir_intrinsic_image_load)
+ tmp = emit_image_load(bld, image, addr, surf_dims, arr_dims, format);
+
+ else if (instr->intrinsic == nir_intrinsic_image_store)
+ emit_image_store(bld, image, addr, src0, surf_dims, arr_dims, format);
+
+ else
+ tmp = emit_image_atomic(bld, image, addr, src0, src1,
+ surf_dims, arr_dims, info->dest_components,
+ get_image_atomic_op(instr->intrinsic, type));
+
+ /* Assign the result. */
+ for (unsigned c = 0; c < info->dest_components; ++c)
+ bld.MOV(offset(retype(dest, base_type), bld, c),
+ offset(tmp, bld, c));
+ break;
+ }
+
+ case nir_intrinsic_memory_barrier: {
+ const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 16 / dispatch_width);
+ bld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp)
+ ->regs_written = 2;
break;
}
has_indirect = true;
/* fallthrough */
case nir_intrinsic_load_ubo: {
+ uint32_t set = instr->const_index[0];
nir_const_value *const_index = nir_src_as_const_value(instr->src[0]);
fs_reg surf_index;
if (const_index) {
- surf_index = fs_reg(stage_prog_data->binding_table.ubo_start +
- const_index->u[0]);
+ uint32_t binding = const_index->u[0];
+
+ /* FIXME: We should probably assert here, but dota2 seems to hit
+ * it and we'd like to keep going.
+ */
+ if (binding >= stage_prog_data->bind_map[set].index_count)
+ binding = 0;
+
+ surf_index = fs_reg(stage_prog_data->bind_map[set].index[binding]);
} else {
+ assert(0 && "need more info from the ir for this.");
/* The block index is not a constant. Evaluate the index expression
* per-channel and add the base UBO index; we have to select a value
* from any live channel.
surf_index = vgrf(glsl_type::uint_type);
bld.ADD(surf_index, get_nir_src(instr->src[0]),
fs_reg(stage_prog_data->binding_table.ubo_start));
- bld.emit_uniformize(surf_index, surf_index);
+ surf_index = bld.emit_uniformize(surf_index);
/* Assume this may touch any UBO. It would be nice to provide
* a tighter bound, but the array information is already lowered away.
BRW_REGISTER_TYPE_D),
fs_reg(2));
- unsigned vec4_offset = instr->const_index[0] / 4;
+ unsigned vec4_offset = instr->const_index[1] / 4;
for (int i = 0; i < instr->num_components; i++)
VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
base_offset, vec4_offset + i);
fs_reg packed_consts = vgrf(glsl_type::float_type);
packed_consts.type = dest.type;
- fs_reg const_offset_reg((unsigned) instr->const_index[0] & ~15);
+ fs_reg const_offset_reg((unsigned) instr->const_index[1] & ~15);
bld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, packed_consts,
surf_index, const_offset_reg);
void
fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
{
- unsigned sampler = instr->sampler_index;
+ uint32_t set = instr->sampler_set;
+ uint32_t binding = instr->sampler_index;
+
+ assert(binding < stage_prog_data->bind_map[set].index_count);
+ assert(stage_prog_data->bind_map[set].index[binding] < 1000);
+
+ unsigned sampler = stage_prog_data->bind_map[set].index[binding];
fs_reg sampler_reg(sampler);
/* FINISHME: We're failing to recompile our programs when the sampler is
/* Emit code to evaluate the actual indexing expression */
sampler_reg = vgrf(glsl_type::uint_type);
bld.ADD(sampler_reg, src, fs_reg(sampler));
- bld.emit_uniformize(sampler_reg, sampler_reg);
+ sampler_reg = bld.emit_uniformize(sampler_reg);
break;
}
}
}
- enum glsl_base_type dest_base_type;
- switch (instr->dest_type) {
- case nir_type_float:
- dest_base_type = GLSL_TYPE_FLOAT;
- break;
- case nir_type_int:
- dest_base_type = GLSL_TYPE_INT;
- break;
- case nir_type_unsigned:
- dest_base_type = GLSL_TYPE_UINT;
- break;
- default:
- unreachable("bad type");
- }
+ enum glsl_base_type dest_base_type =
+ brw_glsl_base_type_for_nir_type (instr->dest_type);
const glsl_type *dest_type =
glsl_type::get_instance(dest_base_type, nir_tex_instr_dest_size(instr),
bld.emit(BRW_OPCODE_CONTINUE);
break;
case nir_jump_return:
+ /* This has to be the last block in the shader. We don't handle
+ * early returns.
+ */
+ assert(nir_cf_node_next(&instr->instr.block->cf_node) == NULL &&
+ instr->instr.block->cf_node.parent->type == nir_cf_node_function);
+ break;
default:
unreachable("unknown jump");
}
projects / mesa.git / blobdiff