#include "glsl/ir.h"
#include "glsl/ir_optimization.h"
#include "glsl/nir/glsl_to_nir.h"
+#include "main/shaderimage.h"
#include "program/prog_to_nir.h"
#include "brw_fs.h"
+#include "brw_fs_surface_builder.h"
#include "brw_nir.h"
using namespace brw;
/* emit the arrays used for inputs and outputs - load/store intrinsics will
* be converted to reads/writes of these arrays
*/
-
- if (nir->num_inputs > 0) {
- nir_inputs = bld.vgrf(BRW_REGISTER_TYPE_F, nir->num_inputs);
- nir_setup_inputs(nir);
- }
-
- if (nir->num_outputs > 0) {
- nir_outputs = bld.vgrf(BRW_REGISTER_TYPE_F, nir->num_outputs);
- nir_setup_outputs(nir);
- }
-
- if (nir->num_uniforms > 0) {
- nir_setup_uniforms(nir);
- }
-
+ nir_setup_inputs(nir);
+ nir_setup_outputs(nir);
+ nir_setup_uniforms(nir);
nir_emit_system_values(nir);
- nir_globals = ralloc_array(mem_ctx, fs_reg, nir->reg_alloc);
- foreach_list_typed(nir_register, reg, node, &nir->registers) {
- unsigned array_elems =
- reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
- unsigned size = array_elems * reg->num_components;
- nir_globals[reg->index] = bld.vgrf(BRW_REGISTER_TYPE_F, size);
- }
-
/* get the main function and emit it */
nir_foreach_overload(nir, overload) {
assert(strcmp(overload->function->name, "main") == 0);
void
fs_visitor::nir_setup_inputs(nir_shader *shader)
{
+ nir_inputs = bld.vgrf(BRW_REGISTER_TYPE_F, shader->num_inputs);
+
foreach_list_typed(nir_variable, var, node, &shader->inputs) {
enum brw_reg_type type = brw_type_for_base_type(var->type);
- fs_reg input = offset(nir_inputs, var->data.driver_location);
+ fs_reg input = offset(nir_inputs, bld, var->data.driver_location);
fs_reg reg;
switch (stage) {
* So, we need to copy from fs_reg(ATTR, var->location) to
* offset(nir_inputs, var->data.driver_location).
*/
- unsigned components = var->type->without_array()->components();
+ const glsl_type *const t = var->type->without_array();
+ const unsigned components = t->components();
+ const unsigned cols = t->matrix_columns;
+ const unsigned elts = t->vector_elements;
unsigned array_length = var->type->is_array() ? var->type->length : 1;
for (unsigned i = 0; i < array_length; i++) {
- for (unsigned j = 0; j < components; j++) {
- bld.MOV(retype(offset(input, components * i + j), type),
- offset(fs_reg(ATTR, var->data.location + i, type), j));
+ for (unsigned j = 0; j < cols; j++) {
+ for (unsigned k = 0; k < elts; k++) {
+ bld.MOV(offset(retype(input, type), bld,
+ components * i + elts * j + k),
+ offset(fs_reg(ATTR, var->data.location + i, type),
+ bld, 4 * j + k));
+ }
}
}
break;
}
case MESA_SHADER_GEOMETRY:
case MESA_SHADER_COMPUTE:
+ case MESA_SHADER_TESS_CTRL:
+ case MESA_SHADER_TESS_EVAL:
unreachable("fs_visitor not used for these stages yet.");
break;
case MESA_SHADER_FRAGMENT:
if (var->data.location == VARYING_SLOT_POS) {
reg = *emit_fragcoord_interpolation(var->data.pixel_center_integer,
var->data.origin_upper_left);
- emit_percomp(bld, fs_inst(BRW_OPCODE_MOV, input, reg), 0xF);
+ emit_percomp(bld, fs_inst(BRW_OPCODE_MOV, bld.dispatch_width(),
+ input, reg), 0xF);
} else {
emit_general_interpolation(input, var->name, var->type,
(glsl_interp_qualifier) var->data.interpolation,
{
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+ nir_outputs = bld.vgrf(BRW_REGISTER_TYPE_F, shader->num_outputs);
+
foreach_list_typed(nir_variable, var, node, &shader->outputs) {
- fs_reg reg = offset(nir_outputs, var->data.driver_location);
+ fs_reg reg = offset(nir_outputs, bld, var->data.driver_location);
int vector_elements =
var->type->is_array() ? var->type->fields.array->vector_elements
: var->type->vector_elements;
- if (stage == MESA_SHADER_VERTEX) {
+ switch (stage) {
+ case MESA_SHADER_VERTEX:
for (int i = 0; i < ALIGN(type_size(var->type), 4) / 4; i++) {
int output = var->data.location + i;
- this->outputs[output] = offset(reg, 4 * i);
+ this->outputs[output] = offset(reg, bld, 4 * i);
this->output_components[output] = vector_elements;
}
- } else if (var->data.index > 0) {
- assert(var->data.location == FRAG_RESULT_DATA0);
- assert(var->data.index == 1);
- this->dual_src_output = reg;
- this->do_dual_src = true;
- } else if (var->data.location == FRAG_RESULT_COLOR) {
- /* Writing gl_FragColor outputs to all color regions. */
- for (unsigned int i = 0; i < MAX2(key->nr_color_regions, 1); i++) {
- this->outputs[i] = reg;
- this->output_components[i] = 4;
- }
- } else if (var->data.location == FRAG_RESULT_DEPTH) {
- this->frag_depth = reg;
- } else if (var->data.location == FRAG_RESULT_SAMPLE_MASK) {
- this->sample_mask = reg;
- } else {
- /* gl_FragData or a user-defined FS output */
- assert(var->data.location >= FRAG_RESULT_DATA0 &&
- var->data.location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);
-
- /* General color output. */
- for (unsigned int i = 0; i < MAX2(1, var->type->length); i++) {
- int output = var->data.location - FRAG_RESULT_DATA0 + i;
- this->outputs[output] = offset(reg, vector_elements * i);
- this->output_components[output] = vector_elements;
+ break;
+ case MESA_SHADER_FRAGMENT:
+ if (var->data.index > 0) {
+ assert(var->data.location == FRAG_RESULT_DATA0);
+ assert(var->data.index == 1);
+ this->dual_src_output = reg;
+ this->do_dual_src = true;
+ } else if (var->data.location == FRAG_RESULT_COLOR) {
+ /* Writing gl_FragColor outputs to all color regions. */
+ for (unsigned int i = 0; i < MAX2(key->nr_color_regions, 1); i++) {
+ this->outputs[i] = reg;
+ this->output_components[i] = 4;
+ }
+ } else if (var->data.location == FRAG_RESULT_DEPTH) {
+ this->frag_depth = reg;
+ } else if (var->data.location == FRAG_RESULT_SAMPLE_MASK) {
+ this->sample_mask = reg;
+ } else {
+ /* gl_FragData or a user-defined FS output */
+ assert(var->data.location >= FRAG_RESULT_DATA0 &&
+ var->data.location < FRAG_RESULT_DATA0+BRW_MAX_DRAW_BUFFERS);
+
+ /* General color output. */
+ for (unsigned int i = 0; i < MAX2(1, var->type->length); i++) {
+ int output = var->data.location - FRAG_RESULT_DATA0 + i;
+ this->outputs[output] = offset(reg, bld, vector_elements * i);
+ this->output_components[output] = vector_elements;
+ }
}
+ break;
+ default:
+ unreachable("unhandled shader stage");
}
}
}
void
fs_visitor::nir_setup_uniforms(nir_shader *shader)
{
- uniforms = shader->num_uniforms;
num_direct_uniforms = shader->num_direct_uniforms;
+ if (dispatch_width != 8)
+ return;
+
/* We split the uniform register file in half. The first half is
* entirely direct uniforms. The second half is indirect.
*/
- param_size[0] = num_direct_uniforms;
+ if (num_direct_uniforms > 0)
+ param_size[0] = num_direct_uniforms;
if (shader->num_uniforms > num_direct_uniforms)
param_size[num_direct_uniforms] = shader->num_uniforms - num_direct_uniforms;
- if (dispatch_width != 8)
- return;
+ uniforms = shader->num_uniforms;
if (shader_prog) {
foreach_list_typed(nir_variable, var, node, &shader->uniforms) {
continue;
}
- unsigned slots = storage->type->component_slots();
- if (storage->array_elements)
- slots *= storage->array_elements;
+ if (storage->type->is_image()) {
+ /* Images don't get a valid location assigned by nir_lower_io()
+ * because their size is driver-specific, so we need to allocate
+ * space for them here at the end of the parameter array.
+ */
+ var->data.driver_location = uniforms;
+ param_size[uniforms] =
+ BRW_IMAGE_PARAM_SIZE * MAX2(storage->array_elements, 1);
- for (unsigned i = 0; i < slots; i++) {
- stage_prog_data->param[index++] = &storage->storage[i];
+ setup_image_uniform_values(storage);
+ } else {
+ unsigned slots = storage->type->component_slots();
+ if (storage->array_elements)
+ slots *= storage->array_elements;
+
+ for (unsigned i = 0; i < slots; i++) {
+ stage_prog_data->param[index++] = &storage->storage[i];
+ }
}
}
-
- /* Make sure we actually initialized the right amount of stuff here. */
- assert(var->data.driver_location + var->type->component_slots() == index);
}
void
nir_locals[reg->index] = bld.vgrf(BRW_REGISTER_TYPE_F, size);
}
+ nir_ssa_values = reralloc(mem_ctx, nir_ssa_values, fs_reg,
+ impl->ssa_alloc);
+
nir_emit_cf_list(&impl->body);
}
bld.emit(BRW_OPCODE_ENDIF);
- if (!try_replace_with_sel() && devinfo->gen < 6) {
- no16("Can't support (non-uniform) control flow on SIMD16\n");
- }
+ try_replace_with_sel();
}
void
fs_visitor::nir_emit_loop(nir_loop *loop)
{
- if (devinfo->gen < 6) {
- no16("Can't support (non-uniform) control flow on SIMD16\n");
- }
-
bld.emit(BRW_OPCODE_DO);
nir_emit_cf_list(&loop->body);
fs_visitor::nir_emit_instr(nir_instr *instr)
{
const fs_builder abld = bld.annotate(NULL, instr);
- this->base_ir = instr;
switch (instr->type) {
case nir_instr_type_alu:
break;
case nir_instr_type_intrinsic:
- nir_emit_intrinsic(nir_instr_as_intrinsic(instr));
+ nir_emit_intrinsic(abld, nir_instr_as_intrinsic(instr));
break;
case nir_instr_type_tex:
- nir_emit_texture(nir_instr_as_tex(instr));
+ nir_emit_texture(abld, nir_instr_as_tex(instr));
break;
case nir_instr_type_load_const:
- /* We can hit these, but we do nothing now and use them as
- * immediates later.
- */
+ nir_emit_load_const(abld, nir_instr_as_load_const(instr));
+ break;
+
+ case nir_instr_type_ssa_undef:
+ nir_emit_undef(abld, nir_instr_as_ssa_undef(instr));
break;
case nir_instr_type_jump:
default:
unreachable("unknown instruction type");
}
-
- this->base_ir = NULL;
-}
-
-static brw_reg_type
-brw_type_for_nir_type(nir_alu_type type)
-{
- switch (type) {
- case nir_type_unsigned:
- return BRW_REGISTER_TYPE_UD;
- case nir_type_bool:
- case nir_type_int:
- return BRW_REGISTER_TYPE_D;
- case nir_type_float:
- return BRW_REGISTER_TYPE_F;
- default:
- unreachable("unknown type");
- }
-
- return BRW_REGISTER_TYPE_F;
}
bool
fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
const fs_reg &result)
{
- if (instr->src[0].src.is_ssa ||
- !instr->src[0].src.reg.reg ||
- !instr->src[0].src.reg.reg->parent_instr)
- return false;
-
- if (instr->src[0].src.reg.reg->parent_instr->type !=
- nir_instr_type_intrinsic)
+ if (!instr->src[0].src.is_ssa ||
+ instr->src[0].src.ssa->parent_instr->type != nir_instr_type_intrinsic)
return false;
nir_intrinsic_instr *src0 =
- nir_instr_as_intrinsic(instr->src[0].src.reg.reg->parent_instr);
+ nir_instr_as_intrinsic(instr->src[0].src.ssa->parent_instr);
if (src0->intrinsic != nir_intrinsic_load_front_face)
return false;
continue;
if (instr->op == nir_op_imov || instr->op == nir_op_fmov) {
- inst = bld.MOV(offset(temp, i),
- offset(op[0], instr->src[0].swizzle[i]));
+ inst = bld.MOV(offset(temp, bld, i),
+ offset(op[0], bld, instr->src[0].swizzle[i]));
} else {
- inst = bld.MOV(offset(temp, i),
- offset(op[i], instr->src[i].swizzle[0]));
+ inst = bld.MOV(offset(temp, bld, i),
+ offset(op[i], bld, instr->src[i].swizzle[0]));
}
inst->saturate = instr->dest.saturate;
}
if (!(instr->dest.write_mask & (1 << i)))
continue;
- bld.MOV(offset(result, i), offset(temp, i));
+ bld.MOV(offset(result, bld, i), offset(temp, bld, i));
}
}
return;
assert(_mesa_bitcount(instr->dest.write_mask) == 1);
channel = ffs(instr->dest.write_mask) - 1;
- result = offset(result, channel);
+ result = offset(result, bld, channel);
}
for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
assert(nir_op_infos[instr->op].input_sizes[i] < 2);
- op[i] = offset(op[i], instr->src[i].swizzle[channel]);
+ op[i] = offset(op[i], bld, instr->src[i].swizzle[channel]);
}
switch (instr->op) {
break;
case nir_op_imul_high:
- case nir_op_umul_high: {
- if (devinfo->gen >= 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width), result.type);
-
- fs_inst *mul = bld.MUL(acc, op[0], op[1]);
- bld.MACH(result, op[0], op[1]);
-
- /* Until Gen8, integer multiplies read 32-bits from one source, and
- * 16-bits from the other, and relying on the MACH instruction to
- * generate the high bits of the result.
- *
- * On Gen8, the multiply instruction does a full 32x32-bit multiply,
- * but in order to do a 64x64-bit multiply we have to simulate the
- * previous behavior and then use a MACH instruction.
- *
- * FINISHME: Don't use source modifiers on src1.
- */
- if (devinfo->gen >= 8) {
- assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
- mul->src[1].type == BRW_REGISTER_TYPE_UD);
- if (mul->src[1].type == BRW_REGISTER_TYPE_D) {
- mul->src[1].type = BRW_REGISTER_TYPE_W;
- mul->src[1].stride = 2;
- } else {
- mul->src[1].type = BRW_REGISTER_TYPE_UW;
- mul->src[1].stride = 2;
- }
- }
+ case nir_op_umul_high:
+ bld.emit(SHADER_OPCODE_MULH, result, op[0], op[1]);
break;
- }
case nir_op_idiv:
case nir_op_udiv:
bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
break;
- case nir_op_uadd_carry: {
- if (devinfo->gen >= 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- bld.ADDC(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
- break;
- }
-
- case nir_op_usub_borrow: {
- if (devinfo->gen >= 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
+ case nir_op_uadd_carry:
+ unreachable("Should have been lowered by carry_to_arith().");
- bld.SUBB(bld.null_reg_ud(), op[0], op[1]);
- bld.MOV(result, fs_reg(acc));
- break;
- }
+ case nir_op_usub_borrow:
+ unreachable("Should have been lowered by borrow_to_arith().");
case nir_op_umod:
bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
case nir_op_inot:
if (devinfo->gen >= 8) {
- resolve_source_modifiers(&op[0]);
+ op[0] = resolve_source_modifiers(op[0]);
}
bld.NOT(result, op[0]);
break;
case nir_op_ixor:
if (devinfo->gen >= 8) {
- resolve_source_modifiers(&op[0]);
- resolve_source_modifiers(&op[1]);
+ op[0] = resolve_source_modifiers(op[0]);
+ op[1] = resolve_source_modifiers(op[1]);
}
bld.XOR(result, op[0], op[1]);
break;
case nir_op_ior:
if (devinfo->gen >= 8) {
- resolve_source_modifiers(&op[0]);
- resolve_source_modifiers(&op[1]);
+ op[0] = resolve_source_modifiers(op[0]);
+ op[1] = resolve_source_modifiers(op[1]);
}
bld.OR(result, op[0], op[1]);
break;
case nir_op_iand:
if (devinfo->gen >= 8) {
- resolve_source_modifiers(&op[0]);
- resolve_source_modifiers(&op[1]);
+ op[0] = resolve_source_modifiers(op[0]);
+ op[1] = resolve_source_modifiers(op[1]);
}
bld.AND(result, op[0], op[1]);
break;
break;
case nir_op_b2i:
- bld.AND(result, op[0], fs_reg(1));
- break;
case nir_op_b2f:
- bld.AND(retype(result, BRW_REGISTER_TYPE_UD), op[0], fs_reg(0x3f800000u));
+ bld.MOV(result, negate(op[0]));
break;
case nir_op_f2b:
}
}
+void
+fs_visitor::nir_emit_load_const(const fs_builder &bld,
+ nir_load_const_instr *instr)
+{
+ fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_D, instr->def.num_components);
+
+ for (unsigned i = 0; i < instr->def.num_components; i++)
+ bld.MOV(offset(reg, bld, i), fs_reg(instr->value.i[i]));
+
+ nir_ssa_values[instr->def.index] = reg;
+}
+
+void
+fs_visitor::nir_emit_undef(const fs_builder &bld, nir_ssa_undef_instr *instr)
+{
+ nir_ssa_values[instr->def.index] = bld.vgrf(BRW_REGISTER_TYPE_D,
+ instr->def.num_components);
+}
+
static fs_reg
fs_reg_for_nir_reg(fs_visitor *v, nir_register *nir_reg,
unsigned base_offset, nir_src *indirect)
{
fs_reg reg;
- if (nir_reg->is_global)
- reg = v->nir_globals[nir_reg->index];
- else
- reg = v->nir_locals[nir_reg->index];
- reg = offset(reg, base_offset * nir_reg->num_components);
+ assert(!nir_reg->is_global);
+
+ reg = v->nir_locals[nir_reg->index];
+
+ reg = offset(reg, v->bld, base_offset * nir_reg->num_components);
if (indirect) {
int multiplier = nir_reg->num_components * (v->dispatch_width / 8);
fs_reg
fs_visitor::get_nir_src(nir_src src)
{
+ fs_reg reg;
if (src.is_ssa) {
- assert(src.ssa->parent_instr->type == nir_instr_type_load_const);
- nir_load_const_instr *load = nir_instr_as_load_const(src.ssa->parent_instr);
- fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_D, src.ssa->num_components);
-
- for (unsigned i = 0; i < src.ssa->num_components; ++i)
- bld.MOV(offset(reg, i), fs_reg(load->value.i[i]));
-
- return reg;
+ reg = nir_ssa_values[src.ssa->index];
} else {
- fs_reg reg = fs_reg_for_nir_reg(this, src.reg.reg, src.reg.base_offset,
- src.reg.indirect);
-
- /* to avoid floating-point denorm flushing problems, set the type by
- * default to D - instructions that need floating point semantics will set
- * this to F if they need to
- */
- return retype(reg, BRW_REGISTER_TYPE_D);
+ reg = fs_reg_for_nir_reg(this, src.reg.reg, src.reg.base_offset,
+ src.reg.indirect);
}
+
+ /* to avoid floating-point denorm flushing problems, set the type by
+ * default to D - instructions that need floating point semantics will set
+ * this to F if they need to
+ */
+ return retype(reg, BRW_REGISTER_TYPE_D);
}
fs_reg
fs_visitor::get_nir_dest(nir_dest dest)
{
+ if (dest.is_ssa) {
+ nir_ssa_values[dest.ssa.index] = bld.vgrf(BRW_REGISTER_TYPE_F,
+ dest.ssa.num_components);
+ return nir_ssa_values[dest.ssa.index];
+ }
+
return fs_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
dest.reg.indirect);
}
+fs_reg
+fs_visitor::get_nir_image_deref(const nir_deref_var *deref)
+{
+ fs_reg image(UNIFORM, deref->var->data.driver_location,
+ BRW_REGISTER_TYPE_UD);
+
+ if (deref->deref.child) {
+ const nir_deref_array *deref_array =
+ nir_deref_as_array(deref->deref.child);
+ assert(deref->deref.child->deref_type == nir_deref_type_array &&
+ deref_array->deref.child == NULL);
+ const unsigned size = glsl_get_length(deref->var->type);
+ const unsigned base = MIN2(deref_array->base_offset, size - 1);
+
+ image = offset(image, bld, base * BRW_IMAGE_PARAM_SIZE);
+
+ if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
+ fs_reg *tmp = new(mem_ctx) fs_reg(vgrf(glsl_type::int_type));
+
+ if (devinfo->gen == 7 && !devinfo->is_haswell) {
+ /* IVB hangs when trying to access an invalid surface index with
+ * the dataport. According to the spec "if the index used to
+ * select an individual element is negative or greater than or
+ * equal to the size of the array, the results of the operation
+ * are undefined but may not lead to termination" -- which is one
+ * of the possible outcomes of the hang. Clamp the index to
+ * prevent access outside of the array bounds.
+ */
+ bld.emit_minmax(*tmp, retype(get_nir_src(deref_array->indirect),
+ BRW_REGISTER_TYPE_UD),
+ fs_reg(size - base - 1), BRW_CONDITIONAL_L);
+ } else {
+ bld.MOV(*tmp, get_nir_src(deref_array->indirect));
+ }
+
+ bld.MUL(*tmp, *tmp, fs_reg(BRW_IMAGE_PARAM_SIZE));
+ image.reladdr = tmp;
+ }
+ }
+
+ return image;
+}
+
void
fs_visitor::emit_percomp(const fs_builder &bld, const fs_inst &inst,
unsigned wr_mask)
continue;
fs_inst *new_inst = new(mem_ctx) fs_inst(inst);
- new_inst->dst = offset(new_inst->dst, i);
+ new_inst->dst = offset(new_inst->dst, bld, i);
for (unsigned j = 0; j < new_inst->sources; j++)
if (new_inst->src[j].file == GRF)
- new_inst->src[j] = offset(new_inst->src[j], i);
+ new_inst->src[j] = offset(new_inst->src[j], bld, i);
bld.emit(new_inst);
}
}
+/**
+ * Get the matching channel register datatype for an image intrinsic of the
+ * specified GLSL image type.
+ */
+static brw_reg_type
+get_image_base_type(const glsl_type *type)
+{
+ switch ((glsl_base_type)type->sampler_type) {
+ case GLSL_TYPE_UINT:
+ return BRW_REGISTER_TYPE_UD;
+ case GLSL_TYPE_INT:
+ return BRW_REGISTER_TYPE_D;
+ case GLSL_TYPE_FLOAT:
+ return BRW_REGISTER_TYPE_F;
+ default:
+ unreachable("Not reached.");
+ }
+}
+
+/**
+ * Get the appropriate atomic op for an image atomic intrinsic.
+ */
+static unsigned
+get_image_atomic_op(nir_intrinsic_op op, const glsl_type *type)
+{
+ switch (op) {
+ case nir_intrinsic_image_atomic_add:
+ return BRW_AOP_ADD;
+ case nir_intrinsic_image_atomic_min:
+ return (get_image_base_type(type) == BRW_REGISTER_TYPE_D ?
+ BRW_AOP_IMIN : BRW_AOP_UMIN);
+ case nir_intrinsic_image_atomic_max:
+ return (get_image_base_type(type) == BRW_REGISTER_TYPE_D ?
+ BRW_AOP_IMAX : BRW_AOP_UMAX);
+ case nir_intrinsic_image_atomic_and:
+ return BRW_AOP_AND;
+ case nir_intrinsic_image_atomic_or:
+ return BRW_AOP_OR;
+ case nir_intrinsic_image_atomic_xor:
+ return BRW_AOP_XOR;
+ case nir_intrinsic_image_atomic_exchange:
+ return BRW_AOP_MOV;
+ case nir_intrinsic_image_atomic_comp_swap:
+ return BRW_AOP_CMPWR;
+ default:
+ unreachable("Not reachable.");
+ }
+}
+
void
-fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
+fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr)
{
fs_reg dest;
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
*/
fs_inst *cmp;
if (instr->intrinsic == nir_intrinsic_discard_if) {
- cmp = emit(CMP(reg_null_f, get_nir_src(instr->src[0]),
- fs_reg(0), BRW_CONDITIONAL_Z));
+ cmp = bld.CMP(bld.null_reg_f(), get_nir_src(instr->src[0]),
+ fs_reg(0), BRW_CONDITIONAL_Z);
} else {
fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
BRW_REGISTER_TYPE_UW));
- cmp = emit(CMP(reg_null_f, some_reg, some_reg, BRW_CONDITIONAL_NZ));
+ cmp = bld.CMP(bld.null_reg_f(), some_reg, some_reg, BRW_CONDITIONAL_NZ);
}
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
case nir_intrinsic_atomic_counter_inc:
case nir_intrinsic_atomic_counter_dec:
case nir_intrinsic_atomic_counter_read: {
- unsigned surf_index = prog_data->binding_table.abo_start +
- (unsigned) instr->const_index[0];
- fs_reg offset = fs_reg(get_nir_src(instr->src[0]));
+ using namespace surface_access;
+ /* Get the arguments of the atomic intrinsic. */
+ const fs_reg offset = get_nir_src(instr->src[0]);
+ const unsigned surface = (stage_prog_data->binding_table.abo_start +
+ instr->const_index[0]);
+ fs_reg tmp;
+
+ /* Emit a surface read or atomic op. */
switch (instr->intrinsic) {
- case nir_intrinsic_atomic_counter_inc:
- emit_untyped_atomic(BRW_AOP_INC, surf_index, dest, offset,
- fs_reg(), fs_reg());
- break;
- case nir_intrinsic_atomic_counter_dec:
- emit_untyped_atomic(BRW_AOP_PREDEC, surf_index, dest, offset,
- fs_reg(), fs_reg());
- break;
- case nir_intrinsic_atomic_counter_read:
- emit_untyped_surface_read(surf_index, dest, offset);
- break;
- default:
- unreachable("Unreachable");
+ case nir_intrinsic_atomic_counter_read:
+ tmp = emit_untyped_read(bld, fs_reg(surface), offset, 1, 1);
+ break;
+
+ case nir_intrinsic_atomic_counter_inc:
+ tmp = emit_untyped_atomic(bld, fs_reg(surface), offset, fs_reg(),
+ fs_reg(), 1, 1, BRW_AOP_INC);
+ break;
+
+ case nir_intrinsic_atomic_counter_dec:
+ tmp = emit_untyped_atomic(bld, fs_reg(surface), offset, fs_reg(),
+ fs_reg(), 1, 1, BRW_AOP_PREDEC);
+ break;
+
+ default:
+ unreachable("Unreachable");
}
+
+ /* Assign the result. */
+ bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), tmp);
+
+ /* Mark the surface as used. */
+ brw_mark_surface_used(stage_prog_data, surface);
+ break;
+ }
+
+ case nir_intrinsic_image_load:
+ case nir_intrinsic_image_store:
+ case nir_intrinsic_image_atomic_add:
+ case nir_intrinsic_image_atomic_min:
+ case nir_intrinsic_image_atomic_max:
+ case nir_intrinsic_image_atomic_and:
+ case nir_intrinsic_image_atomic_or:
+ case nir_intrinsic_image_atomic_xor:
+ case nir_intrinsic_image_atomic_exchange:
+ case nir_intrinsic_image_atomic_comp_swap: {
+ using namespace image_access;
+
+ /* Get the referenced image variable and type. */
+ const nir_variable *var = instr->variables[0]->var;
+ const glsl_type *type = var->type->without_array();
+ const brw_reg_type base_type = get_image_base_type(type);
+
+ /* Get some metadata from the image intrinsic. */
+ const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];
+ const unsigned arr_dims = type->sampler_array ? 1 : 0;
+ const unsigned surf_dims = type->coordinate_components() - arr_dims;
+ const mesa_format format =
+ (var->data.image.write_only ? MESA_FORMAT_NONE :
+ _mesa_get_shader_image_format(var->data.image.format));
+
+ /* Get the arguments of the image intrinsic. */
+ const fs_reg image = get_nir_image_deref(instr->variables[0]);
+ const fs_reg addr = retype(get_nir_src(instr->src[0]),
+ BRW_REGISTER_TYPE_UD);
+ const fs_reg src0 = (info->num_srcs >= 3 ?
+ retype(get_nir_src(instr->src[2]), base_type) :
+ fs_reg());
+ const fs_reg src1 = (info->num_srcs >= 4 ?
+ retype(get_nir_src(instr->src[3]), base_type) :
+ fs_reg());
+ fs_reg tmp;
+
+ /* Emit an image load, store or atomic op. */
+ if (instr->intrinsic == nir_intrinsic_image_load)
+ tmp = emit_image_load(bld, image, addr, surf_dims, arr_dims, format);
+
+ else if (instr->intrinsic == nir_intrinsic_image_store)
+ emit_image_store(bld, image, addr, src0, surf_dims, arr_dims, format);
+
+ else
+ tmp = emit_image_atomic(bld, image, addr, src0, src1,
+ surf_dims, arr_dims, info->dest_components,
+ get_image_atomic_op(instr->intrinsic, type));
+
+ /* Assign the result. */
+ for (unsigned c = 0; c < info->dest_components; ++c)
+ bld.MOV(offset(retype(dest, base_type), bld, c),
+ offset(tmp, bld, c));
+ break;
+ }
+
+ case nir_intrinsic_memory_barrier: {
+ const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 16 / dispatch_width);
+ bld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp)
+ ->regs_written = 2;
break;
}
case nir_intrinsic_load_front_face:
- emit(MOV(retype(dest, BRW_REGISTER_TYPE_D),
- *emit_frontfacing_interpolation()));
+ bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
+ *emit_frontfacing_interpolation());
break;
case nir_intrinsic_load_vertex_id:
fs_reg vertex_id = nir_system_values[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE];
assert(vertex_id.file != BAD_FILE);
dest.type = vertex_id.type;
- emit(MOV(dest, vertex_id));
+ bld.MOV(dest, vertex_id);
break;
}
fs_reg base_vertex = nir_system_values[SYSTEM_VALUE_BASE_VERTEX];
assert(base_vertex.file != BAD_FILE);
dest.type = base_vertex.type;
- emit(MOV(dest, base_vertex));
+ bld.MOV(dest, base_vertex);
break;
}
fs_reg instance_id = nir_system_values[SYSTEM_VALUE_INSTANCE_ID];
assert(instance_id.file != BAD_FILE);
dest.type = instance_id.type;
- emit(MOV(dest, instance_id));
+ bld.MOV(dest, instance_id);
break;
}
fs_reg sample_mask_in = nir_system_values[SYSTEM_VALUE_SAMPLE_MASK_IN];
assert(sample_mask_in.file != BAD_FILE);
dest.type = sample_mask_in.type;
- emit(MOV(dest, sample_mask_in));
+ bld.MOV(dest, sample_mask_in);
break;
}
fs_reg sample_pos = nir_system_values[SYSTEM_VALUE_SAMPLE_POS];
assert(sample_pos.file != BAD_FILE);
dest.type = sample_pos.type;
- emit(MOV(dest, sample_pos));
- emit(MOV(offset(dest, 1), offset(sample_pos, 1)));
+ bld.MOV(dest, sample_pos);
+ bld.MOV(offset(dest, bld, 1), offset(sample_pos, bld, 1));
break;
}
fs_reg sample_id = nir_system_values[SYSTEM_VALUE_SAMPLE_ID];
assert(sample_id.file != BAD_FILE);
dest.type = sample_id.type;
- emit(MOV(dest, sample_id));
+ bld.MOV(dest, sample_id);
break;
}
}
for (unsigned j = 0; j < instr->num_components; j++) {
- fs_reg src = offset(retype(uniform_reg, dest.type), index);
+ fs_reg src = offset(retype(uniform_reg, dest.type), bld, index);
if (has_indirect)
src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
index++;
- emit(MOV(dest, src));
- dest = offset(dest, 1);
+ bld.MOV(dest, src);
+ dest = offset(dest, bld, 1);
}
break;
}
has_indirect = true;
/* fallthrough */
case nir_intrinsic_load_ubo: {
+ uint32_t set = instr->const_index[0];
nir_const_value *const_index = nir_src_as_const_value(instr->src[0]);
fs_reg surf_index;
if (const_index) {
- surf_index = fs_reg(stage_prog_data->binding_table.ubo_start +
- const_index->u[0]);
+ uint32_t binding = const_index->u[0];
+
+ /* FIXME: We should probably assert here, but dota2 seems to hit
+ * it and we'd like to keep going.
+ */
+ if (binding >= stage_prog_data->bind_map[set].index_count)
+ binding = 0;
+
+ surf_index = fs_reg(stage_prog_data->bind_map[set].index[binding]);
} else {
+ assert(0 && "need more info from the ir for this.");
/* The block index is not a constant. Evaluate the index expression
* per-channel and add the base UBO index; we have to select a value
* from any live channel.
*/
surf_index = vgrf(glsl_type::uint_type);
- emit(ADD(surf_index, get_nir_src(instr->src[0]),
- fs_reg(stage_prog_data->binding_table.ubo_start)));
- emit_uniformize(surf_index, surf_index);
+ bld.ADD(surf_index, get_nir_src(instr->src[0]),
+ fs_reg(stage_prog_data->binding_table.ubo_start));
+ surf_index = bld.emit_uniformize(surf_index);
/* Assume this may touch any UBO. It would be nice to provide
* a tighter bound, but the array information is already lowered away.
if (has_indirect) {
/* Turn the byte offset into a dword offset. */
fs_reg base_offset = vgrf(glsl_type::int_type);
- emit(SHR(base_offset, retype(get_nir_src(instr->src[1]),
- BRW_REGISTER_TYPE_D),
- fs_reg(2)));
+ bld.SHR(base_offset, retype(get_nir_src(instr->src[1]),
+ BRW_REGISTER_TYPE_D),
+ fs_reg(2));
- unsigned vec4_offset = instr->const_index[0] / 4;
+ unsigned vec4_offset = instr->const_index[1] / 4;
for (int i = 0; i < instr->num_components; i++)
- VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, i), surf_index,
+ VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
base_offset, vec4_offset + i);
} else {
fs_reg packed_consts = vgrf(glsl_type::float_type);
packed_consts.type = dest.type;
- fs_reg const_offset_reg((unsigned) instr->const_index[0] & ~15);
- emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, packed_consts,
- surf_index, const_offset_reg);
+ fs_reg const_offset_reg((unsigned) instr->const_index[1] & ~15);
+ bld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, packed_consts,
+ surf_index, const_offset_reg);
for (unsigned i = 0; i < instr->num_components; i++) {
packed_consts.set_smear(instr->const_index[0] % 16 / 4 + i);
*/
assert(packed_consts.subreg_offset < 32);
- emit(MOV(dest, packed_consts));
- dest = offset(dest, 1);
+ bld.MOV(dest, packed_consts);
+ dest = offset(dest, bld, 1);
}
}
break;
case nir_intrinsic_load_input: {
unsigned index = 0;
for (unsigned j = 0; j < instr->num_components; j++) {
- fs_reg src = offset(retype(nir_inputs, dest.type),
+ fs_reg src = offset(retype(nir_inputs, dest.type), bld,
instr->const_index[0] + index);
if (has_indirect)
src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
index++;
- emit(MOV(dest, src));
- dest = offset(dest, 1);
+ bld.MOV(dest, src);
+ dest = offset(dest, bld, 1);
}
break;
}
case nir_intrinsic_interp_var_at_centroid:
case nir_intrinsic_interp_var_at_sample:
case nir_intrinsic_interp_var_at_offset: {
- /* in SIMD16 mode, the pixel interpolator returns coords interleaved
- * 8 channels at a time, same as the barycentric coords presented in
- * the FS payload. this requires a bit of extra work to support.
- */
- no16("interpolate_at_* not yet supported in SIMD16 mode.");
+ assert(stage == MESA_SHADER_FRAGMENT);
+
+ ((struct brw_wm_prog_data *) prog_data)->pulls_bary = true;
- fs_reg dst_xy = vgrf(2);
+ fs_reg dst_xy = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
/* For most messages, we need one reg of ignored data; the hardware
* requires mlen==1 even when there is no payload. in the per-slot
switch (instr->intrinsic) {
case nir_intrinsic_interp_var_at_centroid:
- inst = emit(FS_OPCODE_INTERPOLATE_AT_CENTROID, dst_xy, src, fs_reg(0u));
+ inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID,
+ dst_xy, src, fs_reg(0u));
break;
case nir_intrinsic_interp_var_at_sample: {
nir_const_value *const_sample = nir_src_as_const_value(instr->src[0]);
assert(const_sample);
unsigned msg_data = const_sample ? const_sample->i[0] << 4 : 0;
- inst = emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_xy, src,
- fs_reg(msg_data));
+ inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_xy, src,
+ fs_reg(msg_data));
break;
}
unsigned off_x = MIN2((int)(const_offset->f[0] * 16), 7) & 0xf;
unsigned off_y = MIN2((int)(const_offset->f[1] * 16), 7) & 0xf;
- inst = emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_xy, src,
- fs_reg(off_x | (off_y << 4)));
+ inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_xy, src,
+ fs_reg(off_x | (off_y << 4)));
} else {
src = vgrf(glsl_type::ivec2_type);
fs_reg offset_src = retype(get_nir_src(instr->src[0]),
BRW_REGISTER_TYPE_F);
for (int i = 0; i < 2; i++) {
fs_reg temp = vgrf(glsl_type::float_type);
- emit(MUL(temp, offset(offset_src, i), fs_reg(16.0f)));
+ bld.MUL(temp, offset(offset_src, bld, i), fs_reg(16.0f));
fs_reg itemp = vgrf(glsl_type::int_type);
- emit(MOV(itemp, temp)); /* float to int */
+ bld.MOV(itemp, temp); /* float to int */
/* Clamp the upper end of the range to +7/16.
* ARB_gpu_shader5 requires that we support a maximum offset
* implementation-dependent constant
* FRAGMENT_INTERPOLATION_OFFSET_BITS"
*/
-
- emit(BRW_OPCODE_SEL, offset(src, i), itemp, fs_reg(7))
- ->conditional_mod = BRW_CONDITIONAL_L; /* min(src2, 7) */
+ set_condmod(BRW_CONDITIONAL_L,
+ bld.SEL(offset(src, bld, i), itemp, fs_reg(7)));
}
- mlen = 2;
- inst = emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, dst_xy, src,
- fs_reg(0u));
+ mlen = 2 * dispatch_width / 8;
+ inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, dst_xy, src,
+ fs_reg(0u));
}
break;
}
}
inst->mlen = mlen;
- inst->regs_written = 2; /* 2 floats per slot returned */
+ /* 2 floats per slot returned */
+ inst->regs_written = 2 * dispatch_width / 8;
inst->pi_noperspective = instr->variables[0]->var->data.interpolation ==
INTERP_QUALIFIER_NOPERSPECTIVE;
fs_reg src = interp_reg(instr->variables[0]->var->data.location, j);
src.type = dest.type;
- emit(FS_OPCODE_LINTERP, dest, dst_xy, src);
- dest = offset(dest, 1);
+ bld.emit(FS_OPCODE_LINTERP, dest, dst_xy, src);
+ dest = offset(dest, bld, 1);
}
break;
}
fs_reg src = get_nir_src(instr->src[0]);
unsigned index = 0;
for (unsigned j = 0; j < instr->num_components; j++) {
- fs_reg new_dest = offset(retype(nir_outputs, src.type),
+ fs_reg new_dest = offset(retype(nir_outputs, src.type), bld,
instr->const_index[0] + index);
if (has_indirect)
src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[1]));
index++;
- emit(MOV(new_dest, src));
- src = offset(src, 1);
+ bld.MOV(new_dest, src);
+ src = offset(src, bld, 1);
}
break;
}
+ case nir_intrinsic_barrier:
+ emit_barrier();
+ break;
+
default:
unreachable("unknown intrinsic");
}
}
void
-fs_visitor::nir_emit_texture(nir_tex_instr *instr)
+fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
{
- unsigned sampler = instr->sampler_index;
+ uint32_t set = instr->sampler_set;
+ uint32_t binding = instr->sampler_index;
+
+ assert(binding < stage_prog_data->bind_map[set].index_count);
+ assert(stage_prog_data->bind_map[set].index[binding] < 1000);
+
+ unsigned sampler = stage_prog_data->bind_map[set].index[binding];
fs_reg sampler_reg(sampler);
/* FINISHME: We're failing to recompile our programs when the sampler is
bool is_cube_array = instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
instr->is_array;
- int lod_components = 0, offset_components = 0;
+ int lod_components = 0;
+ int UNUSED offset_components = 0;
fs_reg coordinate, shadow_comparitor, lod, lod2, sample_index, mcs, tex_offset;
/* Emit code to evaluate the actual indexing expression */
sampler_reg = vgrf(glsl_type::uint_type);
- emit(ADD(sampler_reg, src, fs_reg(sampler)));
- emit_uniformize(sampler_reg, sampler_reg);
+ bld.ADD(sampler_reg, src, fs_reg(sampler));
+ sampler_reg = bld.emit_uniformize(sampler_reg);
break;
}
}
}
- enum glsl_base_type dest_base_type;
- switch (instr->dest_type) {
- case nir_type_float:
- dest_base_type = GLSL_TYPE_FLOAT;
- break;
- case nir_type_int:
- dest_base_type = GLSL_TYPE_INT;
- break;
- case nir_type_unsigned:
- dest_base_type = GLSL_TYPE_UINT;
- break;
- default:
- unreachable("bad type");
- }
+ enum glsl_base_type dest_base_type =
+ brw_glsl_base_type_for_nir_type (instr->dest_type);
const glsl_type *dest_type =
glsl_type::get_instance(dest_base_type, nir_tex_instr_dest_size(instr),
fs_reg dest = get_nir_dest(instr->dest);
dest.type = this->result.type;
unsigned num_components = nir_tex_instr_dest_size(instr);
- emit_percomp(bld, fs_inst(BRW_OPCODE_MOV, dest, this->result),
+ emit_percomp(bld, fs_inst(BRW_OPCODE_MOV, bld.dispatch_width(),
+ dest, this->result),
(1 << num_components) - 1);
}
bld.emit(BRW_OPCODE_CONTINUE);
break;
case nir_jump_return:
+ /* This has to be the last block in the shader. We don't handle
+ * early returns.
+ */
+ assert(nir_cf_node_next(&instr->instr.block->cf_node) == NULL &&
+ instr->instr.block->cf_node.parent->type == nir_cf_node_function);
+ break;
default:
unreachable("unknown jump");
}
projects / mesa.git / blobdiff