/* Get rid of split copies */
nir_optimize(nir);
+ nir_assign_var_locations_scalar_direct_first(nir, &nir->uniforms,
+ &num_direct_uniforms,
+ &nir->num_uniforms);
+ nir_assign_var_locations_scalar(&nir->inputs, &nir->num_inputs);
+ nir_assign_var_locations_scalar(&nir->outputs, &nir->num_outputs);
+
nir_lower_io(nir);
nir_validate_shader(nir);
}
if (nir->num_uniforms > 0) {
- nir_uniforms = fs_reg(UNIFORM, 0);
nir_setup_uniforms(nir);
}
void
fs_visitor::nir_setup_inputs(nir_shader *shader)
{
- struct hash_entry *entry;
- hash_table_foreach(shader->inputs, entry) {
- nir_variable *var = (nir_variable *) entry->data;
+ foreach_list_typed(nir_variable, var, node, &shader->inputs) {
enum brw_reg_type type = brw_type_for_base_type(var->type);
fs_reg input = offset(nir_inputs, var->data.driver_location);
{
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
- struct hash_entry *entry;
- hash_table_foreach(shader->outputs, entry) {
- nir_variable *var = (nir_variable *) entry->data;
+ foreach_list_typed(nir_variable, var, node, &shader->outputs) {
fs_reg reg = offset(nir_outputs, var->data.driver_location);
int vector_elements =
fs_visitor::nir_setup_uniforms(nir_shader *shader)
{
uniforms = shader->num_uniforms;
- param_size[0] = shader->num_uniforms;
+
+ /* We split the uniform register file in half. The first half is
+ * entirely direct uniforms. The second half is indirect.
+ */
+ param_size[0] = num_direct_uniforms;
+ if (shader->num_uniforms > num_direct_uniforms)
+ param_size[num_direct_uniforms] = shader->num_uniforms - num_direct_uniforms;
if (dispatch_width != 8)
return;
- struct hash_entry *entry;
- hash_table_foreach(shader->uniforms, entry) {
- nir_variable *var = (nir_variable *) entry->data;
-
+ foreach_list_typed(nir_variable, var, node, &shader->uniforms) {
/* UBO's and atomics don't take up space in the uniform file */
if (var->interface_type != NULL || var->type->contains_atomic())
break;
case nir_op_flrp:
- /* TODO emulate for gen < 6 */
- inst = emit(LRP(result, op[2], op[1], op[0]));
+ inst = emit_lrp(result, op[0], op[1], op[2]);
inst->saturate = instr->dest.saturate;
break;
cmp->flag_subreg = 1;
if (brw->gen >= 6) {
- /* For performance, after a discard, jump to the end of the shader.
- * Only jump if all relevant channels have been discarded.
- */
- fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
- discard_jump->flag_subreg = 1;
-
- discard_jump->predicate = (dispatch_width == 8)
- ? BRW_PREDICATE_ALIGN1_ANY8H
- : BRW_PREDICATE_ALIGN1_ANY16H;
- discard_jump->predicate_inverse = true;
+ emit_discard_jump();
}
-
break;
}
case nir_intrinsic_load_uniform_indirect:
has_indirect = true;
case nir_intrinsic_load_uniform: {
- unsigned index = 0;
+ unsigned index = instr->const_index[0];
+
+ fs_reg uniform_reg;
+ if (index < num_direct_uniforms) {
+ uniform_reg = fs_reg(UNIFORM, 0);
+ } else {
+ uniform_reg = fs_reg(UNIFORM, num_direct_uniforms);
+ index -= num_direct_uniforms;
+ }
+
for (int i = 0; i < instr->const_index[1]; i++) {
for (unsigned j = 0; j < instr->num_components; j++) {
- fs_reg src = offset(retype(nir_uniforms, dest.type),
- instr->const_index[0] + index);
+ fs_reg src = offset(retype(uniform_reg, dest.type), index);
if (has_indirect)
src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
index++;