* IN THE SOFTWARE.
*/
+#include "glsl/ir.h"
+#include "glsl/ir_optimization.h"
#include "glsl/nir/glsl_to_nir.h"
+#include "program/prog_to_nir.h"
#include "brw_fs.h"
+#include "brw_fs_surface_builder.h"
+#include "brw_nir.h"
-static glsl_interp_qualifier
-determine_interpolation_mode(nir_variable *var, bool flat_shade)
-{
- if (var->data.interpolation != INTERP_QUALIFIER_NONE)
- return (glsl_interp_qualifier) var->data.interpolation;
- int location = var->data.location;
- bool is_gl_Color =
- location == VARYING_SLOT_COL0 || location == VARYING_SLOT_COL1;
- if (flat_shade && is_gl_Color)
- return INTERP_QUALIFIER_FLAT;
- else
- return INTERP_QUALIFIER_SMOOTH;
-}
+using namespace brw;
void
fs_visitor::emit_nir_code()
{
- /* first, lower the GLSL IR shader to NIR */
- nir_shader *nir = glsl_to_nir(shader->base.ir, NULL, true);
- nir_validate_shader(nir);
-
- /* lower some of the GLSL-isms into NIR-isms - after this point, we no
- * longer have to deal with variables inside the shader
- */
-
- nir_lower_variables_scalar(nir, true, true, true, true);
- nir_validate_shader(nir);
-
- nir_lower_samplers(nir, shader_prog, shader->base.Program);
- nir_validate_shader(nir);
-
- nir_lower_system_values(nir);
- nir_validate_shader(nir);
-
- nir_lower_atomics(nir);
- nir_validate_shader(nir);
-
- nir_remove_dead_variables(nir);
- nir_opt_global_to_local(nir);
- nir_validate_shader(nir);
-
- if (1)
- nir_print_shader(nir, stderr);
+ nir_shader *nir = prog->nir;
/* emit the arrays used for inputs and outputs - load/store intrinsics will
* be converted to reads/writes of these arrays
*/
-
- if (nir->num_inputs > 0) {
- nir_inputs = fs_reg(GRF, virtual_grf_alloc(nir->num_inputs));
- nir_setup_inputs(nir);
- }
-
- if (nir->num_outputs > 0) {
- nir_outputs = fs_reg(GRF, virtual_grf_alloc(nir->num_outputs));
- nir_setup_outputs(nir);
- }
-
- if (nir->num_uniforms > 0) {
- nir_uniforms = fs_reg(UNIFORM, 0);
- nir_setup_uniforms(nir);
- }
-
- nir_setup_registers(&nir->registers);
+ nir_setup_inputs(nir);
+ nir_setup_outputs(nir);
+ nir_setup_uniforms(nir);
+ nir_emit_system_values(nir);
/* get the main function and emit it */
nir_foreach_overload(nir, overload) {
assert(overload->impl);
nir_emit_impl(overload->impl);
}
-
- ralloc_free(nir);
}
void
fs_visitor::nir_setup_inputs(nir_shader *shader)
{
- fs_reg varying = nir_inputs;
+ nir_inputs = bld.vgrf(BRW_REGISTER_TYPE_F, shader->num_inputs);
- struct hash_entry *entry;
- hash_table_foreach(shader->inputs, entry) {
- nir_variable *var = (nir_variable *) entry->data;
- varying.reg_offset = var->data.driver_location;
+ foreach_list_typed(nir_variable, var, node, &shader->inputs) {
+ enum brw_reg_type type = brw_type_for_base_type(var->type);
+ fs_reg input = offset(nir_inputs, bld, var->data.driver_location);
fs_reg reg;
- if (!strcmp(var->name, "gl_FragCoord")) {
- reg = *emit_fragcoord_interpolation(var->data.pixel_center_integer,
- var->data.origin_upper_left);
- emit_percomp(MOV(varying, reg), 0xF);
- } else if (!strcmp(var->name, "gl_FrontFacing")) {
- reg = *emit_frontfacing_interpolation();
- emit(MOV(retype(varying, BRW_REGISTER_TYPE_UD), reg));
- } else {
- nir_emit_interpolation(var, &varying);
+ switch (stage) {
+ case MESA_SHADER_VERTEX: {
+ /* Our ATTR file is indexed by VERT_ATTRIB_*, which is the value
+ * stored in nir_variable::location.
+ *
+ * However, NIR's load_input intrinsics use a different index - an
+ * offset into a single contiguous array containing all inputs.
+ * This index corresponds to the nir_variable::driver_location field.
+ *
+ * So, we need to copy from fs_reg(ATTR, var->location) to
+ * offset(nir_inputs, var->data.driver_location).
+ */
+ const glsl_type *const t = var->type->without_array();
+ const unsigned components = t->components();
+ const unsigned cols = t->matrix_columns;
+ const unsigned elts = t->vector_elements;
+ unsigned array_length = var->type->is_array() ? var->type->length : 1;
+ for (unsigned i = 0; i < array_length; i++) {
+ for (unsigned j = 0; j < cols; j++) {
+ for (unsigned k = 0; k < elts; k++) {
+ bld.MOV(offset(retype(input, type), bld,
+ components * i + elts * j + k),
+ offset(fs_reg(ATTR, var->data.location + i, type),
+ bld, 4 * j + k));
+ }
+ }
+ }
+ break;
+ }
+ case MESA_SHADER_GEOMETRY:
+ case MESA_SHADER_COMPUTE:
+ case MESA_SHADER_TESS_CTRL:
+ case MESA_SHADER_TESS_EVAL:
+ unreachable("fs_visitor not used for these stages yet.");
+ break;
+ case MESA_SHADER_FRAGMENT:
+ if (var->data.location == VARYING_SLOT_POS) {
+ reg = *emit_fragcoord_interpolation(var->data.pixel_center_integer,
+ var->data.origin_upper_left);
+ emit_percomp(bld, fs_inst(BRW_OPCODE_MOV, bld.dispatch_width(),
+ input, reg), 0xF);
+ } else {
+ emit_general_interpolation(input, var->name, var->type,
+ (glsl_interp_qualifier) var->data.interpolation,
+ var->data.location, var->data.centroid,
+ var->data.sample);
+ }
+ break;
}
}
}
void
-fs_visitor::nir_emit_interpolation(nir_variable *var, fs_reg *varying)
+fs_visitor::nir_setup_outputs(nir_shader *shader)
{
- brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
- fs_reg reg = *varying;
- reg.type = brw_type_for_base_type(var->type->get_scalar_type());
- unsigned int array_elements;
- const glsl_type *type;
+ nir_outputs = bld.vgrf(BRW_REGISTER_TYPE_F, shader->num_outputs);
- if (var->type->is_array()) {
- array_elements = var->type->length;
- if (array_elements == 0) {
- fail("dereferenced array '%s' has length 0\n", var->name);
- }
- type = var->type->fields.array;
- } else {
- array_elements = 1;
- type = var->type;
- }
+ foreach_list_typed(nir_variable, var, node, &shader->outputs) {
+ fs_reg reg = offset(nir_outputs, bld, var->data.driver_location);
- glsl_interp_qualifier interpolation_mode =
- determine_interpolation_mode(var, key->flat_shade);
+ int vector_elements =
+ var->type->is_array() ? var->type->fields.array->vector_elements
+ : var->type->vector_elements;
- int location = var->data.location;
- for (unsigned int i = 0; i < array_elements; i++) {
- for (unsigned int j = 0; j < type->matrix_columns; j++) {
- if (prog_data->urb_setup[location] == -1) {
- /* If there's no incoming setup data for this slot, don't
- * emit interpolation for it.
- */
- reg.reg_offset += type->vector_elements;
- location++;
- continue;
+ switch (stage) {
+ case MESA_SHADER_VERTEX:
+ for (int i = 0; i < ALIGN(type_size(var->type), 4) / 4; i++) {
+ int output = var->data.location + i;
+ this->outputs[output] = offset(reg, bld, 4 * i);
+ this->output_components[output] = vector_elements;
}
-
- if (interpolation_mode == INTERP_QUALIFIER_FLAT) {
- /* Constant interpolation (flat shading) case. The SF has
- * handed us defined values in only the constant offset
- * field of the setup reg.
- */
- for (unsigned int k = 0; k < type->vector_elements; k++) {
- struct brw_reg interp = interp_reg(location, k);
- interp = suboffset(interp, 3);
- interp.type = reg.type;
- emit(FS_OPCODE_CINTERP, reg, fs_reg(interp));
- reg.reg_offset++;
+ break;
+ case MESA_SHADER_FRAGMENT:
+ if (var->data.index > 0) {
+ assert(var->data.location == FRAG_RESULT_DATA0);
+ assert(var->data.index == 1);
+ this->dual_src_output = reg;
+ this->do_dual_src = true;
+ } else if (var->data.location == FRAG_RESULT_COLOR) {
+ /* Writing gl_FragColor outputs to all color regions. */
+ for (unsigned int i = 0; i < MAX2(key->nr_color_regions, 1); i++) {
+ this->outputs[i] = reg;
+ this->output_components[i] = 4;
}
+ } else if (var->data.location == FRAG_RESULT_DEPTH) {
+ this->frag_depth = reg;
+ } else if (var->data.location == FRAG_RESULT_SAMPLE_MASK) {
+ this->sample_mask = reg;
} else {
- /* Smooth/noperspective interpolation case. */
- for (unsigned int k = 0; k < type->vector_elements; k++) {
- struct brw_reg interp = interp_reg(location, k);
- if (brw->needs_unlit_centroid_workaround && var->data.centroid) {
- /* Get the pixel/sample mask into f0 so that we know
- * which pixels are lit. Then, for each channel that is
- * unlit, replace the centroid data with non-centroid
- * data.
- */
- emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS);
-
- fs_inst *inst;
- inst = emit_linterp(reg, fs_reg(interp), interpolation_mode,
- false, false);
- inst->predicate = BRW_PREDICATE_NORMAL;
- inst->predicate_inverse = true;
- if (brw->has_pln)
- inst->no_dd_clear = true;
-
- inst = emit_linterp(reg, fs_reg(interp), interpolation_mode,
- var->data.centroid && !key->persample_shading,
- var->data.sample || key->persample_shading);
- inst->predicate = BRW_PREDICATE_NORMAL;
- inst->predicate_inverse = false;
- if (brw->has_pln)
- inst->no_dd_check = true;
-
- } else {
- emit_linterp(reg, fs_reg(interp), interpolation_mode,
- var->data.centroid && !key->persample_shading,
- var->data.sample || key->persample_shading);
- }
- if (brw->gen < 6 && interpolation_mode == INTERP_QUALIFIER_SMOOTH) {
- emit(BRW_OPCODE_MUL, reg, reg, this->pixel_w);
- }
- reg.reg_offset++;
+ /* gl_FragData or a user-defined FS output */
+ assert(var->data.location >= FRAG_RESULT_DATA0 &&
+ var->data.location < FRAG_RESULT_DATA0+BRW_MAX_DRAW_BUFFERS);
+
+ /* General color output. */
+ for (unsigned int i = 0; i < MAX2(1, var->type->length); i++) {
+ int output = var->data.location - FRAG_RESULT_DATA0 + i;
+ this->outputs[output] = offset(reg, bld, vector_elements * i);
+ this->output_components[output] = vector_elements;
}
-
- }
- location++;
- }
- }
-}
-
-void
-fs_visitor::nir_setup_outputs(nir_shader *shader)
-{
- brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
- fs_reg reg = nir_outputs;
-
- struct hash_entry *entry;
- hash_table_foreach(shader->outputs, entry) {
- nir_variable *var = (nir_variable *) entry->data;
- reg.reg_offset = var->data.driver_location;
-
- if (var->data.index > 0) {
- assert(var->data.location == FRAG_RESULT_DATA0);
- assert(var->data.index == 1);
- this->dual_src_output = reg;
- this->do_dual_src = true;
- } else if (var->data.location == FRAG_RESULT_COLOR) {
- /* Writing gl_FragColor outputs to all color regions. */
- for (unsigned int i = 0; i < MAX2(key->nr_color_regions, 1); i++) {
- this->outputs[i] = reg;
- this->output_components[i] = 4;
- }
- } else if (var->data.location == FRAG_RESULT_DEPTH) {
- this->frag_depth = reg;
- } else if (var->data.location == FRAG_RESULT_SAMPLE_MASK) {
- this->sample_mask = reg;
- } else {
- /* gl_FragData or a user-defined FS output */
- assert(var->data.location >= FRAG_RESULT_DATA0 &&
- var->data.location < FRAG_RESULT_DATA0 + BRW_MAX_DRAW_BUFFERS);
-
- int vector_elements =
- var->type->is_array() ? var->type->fields.array->vector_elements
- : var->type->vector_elements;
-
- /* General color output. */
- for (unsigned int i = 0; i < MAX2(1, var->type->length); i++) {
- int output = var->data.location - FRAG_RESULT_DATA0 + i;
- this->outputs[output] = reg;
- this->outputs[output].reg_offset += vector_elements * i;
- this->output_components[output] = vector_elements;
}
+ break;
+ default:
+ unreachable("unhandled shader stage");
}
}
}
void
fs_visitor::nir_setup_uniforms(nir_shader *shader)
{
- uniforms = shader->num_uniforms;
- param_size[0] = shader->num_uniforms;
+ num_direct_uniforms = shader->num_direct_uniforms;
if (dispatch_width != 8)
return;
- struct hash_entry *entry;
- hash_table_foreach(shader->uniforms, entry) {
- nir_variable *var = (nir_variable *) entry->data;
+ /* We split the uniform register file in half. The first half is
+ * entirely direct uniforms. The second half is indirect.
+ */
+ if (num_direct_uniforms > 0)
+ param_size[0] = num_direct_uniforms;
+ if (shader->num_uniforms > num_direct_uniforms)
+ param_size[num_direct_uniforms] = shader->num_uniforms - num_direct_uniforms;
- /* UBO's and atomics don't take up space in the uniform file */
+ uniforms = shader->num_uniforms;
- if (var->interface_type != NULL || var->type->contains_atomic())
- continue;
+ if (shader_prog) {
+ foreach_list_typed(nir_variable, var, node, &shader->uniforms) {
+ /* UBO's and atomics don't take up space in the uniform file */
+ if (var->interface_type != NULL || var->type->contains_atomic())
+ continue;
- if (strncmp(var->name, "gl_", 3) == 0)
- nir_setup_builtin_uniform(var);
- else
- nir_setup_uniform(var);
+ if (strncmp(var->name, "gl_", 3) == 0)
+ nir_setup_builtin_uniform(var);
+ else
+ nir_setup_uniform(var);
+ }
+ } else {
+ /* prog_to_nir doesn't create uniform variables; set param up directly. */
+ for (unsigned p = 0; p < prog->Parameters->NumParameters; p++) {
+ for (unsigned int i = 0; i < 4; i++) {
+ stage_prog_data->param[4 * p + i] =
+ &prog->Parameters->ParameterValues[p][i];
+ }
+ }
}
}
* our name.
*/
unsigned index = var->data.driver_location;
- for (unsigned u = 0; u < shader_prog->NumUserUniformStorage; u++) {
+ for (unsigned u = 0; u < shader_prog->NumUniformStorage; u++) {
struct gl_uniform_storage *storage = &shader_prog->UniformStorage[u];
+ if (storage->builtin)
+ continue;
+
if (strncmp(var->name, storage->name, namelen) != 0 ||
(storage->name[namelen] != 0 &&
storage->name[namelen] != '.' &&
}
}
+static bool
+emit_system_values_block(nir_block *block, void *void_visitor)
+{
+ fs_visitor *v = (fs_visitor *)void_visitor;
+ fs_reg *reg;
+
+ nir_foreach_instr(block, instr) {
+ if (instr->type != nir_instr_type_intrinsic)
+ continue;
+
+ nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+ switch (intrin->intrinsic) {
+ case nir_intrinsic_load_vertex_id:
+ unreachable("should be lowered by lower_vertex_id().");
+
+ case nir_intrinsic_load_vertex_id_zero_base:
+ assert(v->stage == MESA_SHADER_VERTEX);
+ reg = &v->nir_system_values[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE];
+ if (reg->file == BAD_FILE)
+ *reg = *v->emit_vs_system_value(SYSTEM_VALUE_VERTEX_ID_ZERO_BASE);
+ break;
+
+ case nir_intrinsic_load_base_vertex:
+ assert(v->stage == MESA_SHADER_VERTEX);
+ reg = &v->nir_system_values[SYSTEM_VALUE_BASE_VERTEX];
+ if (reg->file == BAD_FILE)
+ *reg = *v->emit_vs_system_value(SYSTEM_VALUE_BASE_VERTEX);
+ break;
+
+ case nir_intrinsic_load_instance_id:
+ assert(v->stage == MESA_SHADER_VERTEX);
+ reg = &v->nir_system_values[SYSTEM_VALUE_INSTANCE_ID];
+ if (reg->file == BAD_FILE)
+ *reg = *v->emit_vs_system_value(SYSTEM_VALUE_INSTANCE_ID);
+ break;
+
+ case nir_intrinsic_load_sample_pos:
+ assert(v->stage == MESA_SHADER_FRAGMENT);
+ reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_POS];
+ if (reg->file == BAD_FILE)
+ *reg = *v->emit_samplepos_setup();
+ break;
+
+ case nir_intrinsic_load_sample_id:
+ assert(v->stage == MESA_SHADER_FRAGMENT);
+ reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_ID];
+ if (reg->file == BAD_FILE)
+ *reg = *v->emit_sampleid_setup();
+ break;
+
+ case nir_intrinsic_load_sample_mask_in:
+ assert(v->stage == MESA_SHADER_FRAGMENT);
+ assert(v->devinfo->gen >= 7);
+ reg = &v->nir_system_values[SYSTEM_VALUE_SAMPLE_MASK_IN];
+ if (reg->file == BAD_FILE)
+ *reg = fs_reg(retype(brw_vec8_grf(v->payload.sample_mask_in_reg, 0),
+ BRW_REGISTER_TYPE_D));
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ return true;
+}
+
void
-fs_visitor::nir_setup_registers(exec_list *list)
+fs_visitor::nir_emit_system_values(nir_shader *shader)
{
- foreach_list_typed(nir_register, nir_reg, node, list) {
- unsigned array_elems =
- nir_reg->num_array_elems == 0 ? 1 : nir_reg->num_array_elems;
- unsigned size = array_elems * nir_reg->num_components;
- fs_reg *reg = new(mem_ctx) fs_reg(GRF, virtual_grf_alloc(size));
- _mesa_hash_table_insert(this->nir_reg_ht, nir_reg, reg);
+ nir_system_values = ralloc_array(mem_ctx, fs_reg, SYSTEM_VALUE_MAX);
+ nir_foreach_overload(shader, overload) {
+ assert(strcmp(overload->function->name, "main") == 0);
+ assert(overload->impl);
+ nir_foreach_block(overload->impl, emit_system_values_block, this);
}
}
void
fs_visitor::nir_emit_impl(nir_function_impl *impl)
{
- nir_setup_registers(&impl->registers);
+ nir_locals = reralloc(mem_ctx, nir_locals, fs_reg, impl->reg_alloc);
+ foreach_list_typed(nir_register, reg, node, &impl->registers) {
+ unsigned array_elems =
+ reg->num_array_elems == 0 ? 1 : reg->num_array_elems;
+ unsigned size = array_elems * reg->num_components;
+ nir_locals[reg->index] = bld.vgrf(BRW_REGISTER_TYPE_F, size);
+ }
+
+ nir_ssa_values = reralloc(mem_ctx, nir_ssa_values, fs_reg,
+ impl->ssa_alloc);
+
nir_emit_cf_list(&impl->body);
}
void
fs_visitor::nir_emit_cf_list(exec_list *list)
{
+ exec_list_validate(list);
foreach_list_typed(nir_cf_node, node, node, list) {
switch (node->type) {
case nir_cf_node_if:
void
fs_visitor::nir_emit_if(nir_if *if_stmt)
{
- if (brw->gen < 6) {
- no16("Can't support (non-uniform) control flow on SIMD16\n");
- }
-
/* first, put the condition into f0 */
- fs_inst *inst = emit(MOV(reg_null_d,
+ fs_inst *inst = bld.MOV(bld.null_reg_d(),
retype(get_nir_src(if_stmt->condition),
- BRW_REGISTER_TYPE_UD)));
+ BRW_REGISTER_TYPE_D));
inst->conditional_mod = BRW_CONDITIONAL_NZ;
- emit(IF(BRW_PREDICATE_NORMAL));
+ bld.IF(BRW_PREDICATE_NORMAL);
nir_emit_cf_list(&if_stmt->then_list);
/* note: if the else is empty, dead CF elimination will remove it */
- emit(BRW_OPCODE_ELSE);
+ bld.emit(BRW_OPCODE_ELSE);
nir_emit_cf_list(&if_stmt->else_list);
- emit(BRW_OPCODE_ENDIF);
+ bld.emit(BRW_OPCODE_ENDIF);
try_replace_with_sel();
}
void
fs_visitor::nir_emit_loop(nir_loop *loop)
{
- if (brw->gen < 6) {
- no16("Can't support (non-uniform) control flow on SIMD16\n");
- }
-
- emit(BRW_OPCODE_DO);
+ bld.emit(BRW_OPCODE_DO);
nir_emit_cf_list(&loop->body);
- emit(BRW_OPCODE_WHILE);
+ bld.emit(BRW_OPCODE_WHILE);
}
void
void
fs_visitor::nir_emit_instr(nir_instr *instr)
{
+ const fs_builder abld = bld.annotate(NULL, instr);
+
switch (instr->type) {
case nir_instr_type_alu:
- nir_emit_alu(nir_instr_as_alu(instr));
+ nir_emit_alu(abld, nir_instr_as_alu(instr));
break;
case nir_instr_type_intrinsic:
- nir_emit_intrinsic(nir_instr_as_intrinsic(instr));
+ nir_emit_intrinsic(abld, nir_instr_as_intrinsic(instr));
break;
- case nir_instr_type_texture:
- nir_emit_texture(nir_instr_as_texture(instr));
+ case nir_instr_type_tex:
+ nir_emit_texture(abld, nir_instr_as_tex(instr));
break;
case nir_instr_type_load_const:
- nir_emit_load_const(nir_instr_as_load_const(instr));
+ nir_emit_load_const(abld, nir_instr_as_load_const(instr));
+ break;
+
+ case nir_instr_type_ssa_undef:
+ nir_emit_undef(abld, nir_instr_as_ssa_undef(instr));
break;
case nir_instr_type_jump:
- nir_emit_jump(nir_instr_as_jump(instr));
+ nir_emit_jump(abld, nir_instr_as_jump(instr));
break;
default:
}
}
-static brw_reg_type
-brw_type_for_nir_type(nir_alu_type type)
+bool
+fs_visitor::optimize_frontfacing_ternary(nir_alu_instr *instr,
+ const fs_reg &result)
{
- switch (type) {
- case nir_type_bool:
- case nir_type_unsigned:
- return BRW_REGISTER_TYPE_UD;
- case nir_type_int:
- return BRW_REGISTER_TYPE_D;
- case nir_type_float:
- return BRW_REGISTER_TYPE_F;
- default:
- unreachable("unknown type");
+ if (!instr->src[0].src.is_ssa ||
+ instr->src[0].src.ssa->parent_instr->type != nir_instr_type_intrinsic)
+ return false;
+
+ nir_intrinsic_instr *src0 =
+ nir_instr_as_intrinsic(instr->src[0].src.ssa->parent_instr);
+
+ if (src0->intrinsic != nir_intrinsic_load_front_face)
+ return false;
+
+ nir_const_value *value1 = nir_src_as_const_value(instr->src[1].src);
+ if (!value1 || fabsf(value1->f[0]) != 1.0f)
+ return false;
+
+ nir_const_value *value2 = nir_src_as_const_value(instr->src[2].src);
+ if (!value2 || fabsf(value2->f[0]) != 1.0f)
+ return false;
+
+ fs_reg tmp = vgrf(glsl_type::int_type);
+
+ if (devinfo->gen >= 6) {
+ /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
+ fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
+ *
+ * This negation looks like it's safe in practice, because bits 0:4 will
+ * surely be TRIANGLES
+ */
+
+ if (value1->f[0] == -1.0f) {
+ g0.negate = true;
+ }
+
+ tmp.type = BRW_REGISTER_TYPE_W;
+ tmp.subreg_offset = 2;
+ tmp.stride = 2;
+
+ fs_inst *or_inst = bld.OR(tmp, g0, fs_reg(0x3f80));
+ or_inst->src[1].type = BRW_REGISTER_TYPE_UW;
+
+ tmp.type = BRW_REGISTER_TYPE_D;
+ tmp.subreg_offset = 0;
+ tmp.stride = 1;
+ } else {
+ /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
+ fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
+ *
+ * This negation looks like it's safe in practice, because bits 0:4 will
+ * surely be TRIANGLES
+ */
+
+ if (value1->f[0] == -1.0f) {
+ g1_6.negate = true;
+ }
+
+ bld.OR(tmp, g1_6, fs_reg(0x3f800000));
}
+ bld.AND(retype(result, BRW_REGISTER_TYPE_D), tmp, fs_reg(0xbf800000));
- return BRW_REGISTER_TYPE_F;
+ return true;
}
void
-fs_visitor::nir_emit_alu(nir_alu_instr *instr)
+fs_visitor::nir_emit_alu(const fs_builder &bld, nir_alu_instr *instr)
{
struct brw_wm_prog_key *fs_key = (struct brw_wm_prog_key *) this->key;
+ fs_inst *inst;
- fs_reg op[3];
- fs_reg dest = retype(get_nir_dest(instr->dest.dest),
- brw_type_for_nir_type(nir_op_infos[instr->op].output_type));
+ fs_reg result = get_nir_dest(instr->dest.dest);
+ result.type = brw_type_for_nir_type(nir_op_infos[instr->op].output_type);
- fs_reg result;
- if (instr->has_predicate) {
- result = fs_reg(GRF, virtual_grf_alloc(4));
- result.type = dest.type;
- } else {
- result = dest;
+ fs_reg op[4];
+ for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
+ op[i] = get_nir_src(instr->src[i].src);
+ op[i].type = brw_type_for_nir_type(nir_op_infos[instr->op].input_types[i]);
+ op[i].abs = instr->src[i].abs;
+ op[i].negate = instr->src[i].negate;
}
+ /* We get a bunch of mov's out of the from_ssa pass and they may still
+ * be vectorized. We'll handle them as a special-case. We'll also
+ * handle vecN here because it's basically the same thing.
+ */
+ switch (instr->op) {
+ case nir_op_imov:
+ case nir_op_fmov:
+ case nir_op_vec2:
+ case nir_op_vec3:
+ case nir_op_vec4: {
+ fs_reg temp = result;
+ bool need_extra_copy = false;
+ for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
+ if (!instr->src[i].src.is_ssa &&
+ instr->dest.dest.reg.reg == instr->src[i].src.reg.reg) {
+ need_extra_copy = true;
+ temp = bld.vgrf(result.type, 4);
+ break;
+ }
+ }
+
+ for (unsigned i = 0; i < 4; i++) {
+ if (!(instr->dest.write_mask & (1 << i)))
+ continue;
+
+ if (instr->op == nir_op_imov || instr->op == nir_op_fmov) {
+ inst = bld.MOV(offset(temp, bld, i),
+ offset(op[0], bld, instr->src[0].swizzle[i]));
+ } else {
+ inst = bld.MOV(offset(temp, bld, i),
+ offset(op[i], bld, instr->src[i].swizzle[0]));
+ }
+ inst->saturate = instr->dest.saturate;
+ }
+
+ /* In this case the source and destination registers were the same,
+ * so we need to insert an extra set of moves in order to deal with
+ * any swizzling.
+ */
+ if (need_extra_copy) {
+ for (unsigned i = 0; i < 4; i++) {
+ if (!(instr->dest.write_mask & (1 << i)))
+ continue;
+
+ bld.MOV(offset(result, bld, i), offset(temp, bld, i));
+ }
+ }
+ return;
+ }
+ default:
+ break;
+ }
+
+ /* At this point, we have dealt with any instruction that operates on
+ * more than a single channel. Therefore, we can just adjust the source
+ * and destination registers for that channel and emit the instruction.
+ */
+ unsigned channel = 0;
+ if (nir_op_infos[instr->op].output_size == 0) {
+ /* Since NIR is doing the scalarizing for us, we should only ever see
+ * vectorized operations with a single channel.
+ */
+ assert(_mesa_bitcount(instr->dest.write_mask) == 1);
+ channel = ffs(instr->dest.write_mask) - 1;
+
+ result = offset(result, bld, channel);
+ }
for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
- op[i] = retype(get_nir_alu_src(instr, i),
- brw_type_for_nir_type(nir_op_infos[instr->op].input_types[i]));
+ assert(nir_op_infos[instr->op].input_sizes[i] < 2);
+ op[i] = offset(op[i], bld, instr->src[i].swizzle[channel]);
}
switch (instr->op) {
- case nir_op_fmov:
case nir_op_i2f:
- case nir_op_u2f: {
- fs_inst *inst = MOV(result, op[0]);
+ case nir_op_u2f:
+ inst = bld.MOV(result, op[0]);
inst->saturate = instr->dest.saturate;
- emit_percomp(inst, instr->dest.write_mask);
- }
break;
- case nir_op_imov:
case nir_op_f2i:
case nir_op_f2u:
- emit_percomp(MOV(result, op[0]), instr->dest.write_mask);
+ bld.MOV(result, op[0]);
break;
case nir_op_fsign: {
* Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
* zero.
*/
- emit_percomp(CMP(reg_null_f, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ),
- instr->dest.write_mask);
+ bld.CMP(bld.null_reg_f(), op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ);
fs_reg result_int = retype(result, BRW_REGISTER_TYPE_UD);
op[0].type = BRW_REGISTER_TYPE_UD;
result.type = BRW_REGISTER_TYPE_UD;
- emit_percomp(AND(result_int, op[0], fs_reg(0x80000000u)),
- instr->dest.write_mask);
+ bld.AND(result_int, op[0], fs_reg(0x80000000u));
- fs_inst *inst = OR(result_int, result_int, fs_reg(0x3f800000u));
+ inst = bld.OR(result_int, result_int, fs_reg(0x3f800000u));
inst->predicate = BRW_PREDICATE_NORMAL;
- emit_percomp(inst, instr->dest.write_mask);
if (instr->dest.saturate) {
- fs_inst *inst = MOV(result, result);
+ inst = bld.MOV(result, result);
inst->saturate = true;
- emit_percomp(inst, instr->dest.write_mask);
}
break;
}
- case nir_op_isign: {
+ case nir_op_isign:
/* ASR(val, 31) -> negative val generates 0xffffffff (signed -1).
- * -> non-negative val generates 0x00000000.
- * Predicated OR sets 1 if val is positive.
- */
- emit_percomp(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_G),
- instr->dest.write_mask);
-
- emit_percomp(ASR(result, op[0], fs_reg(31)), instr->dest.write_mask);
-
- fs_inst *inst = OR(result, result, fs_reg(1));
+ * -> non-negative val generates 0x00000000.
+ * Predicated OR sets 1 if val is positive.
+ */
+ bld.CMP(bld.null_reg_d(), op[0], fs_reg(0), BRW_CONDITIONAL_G);
+ bld.ASR(result, op[0], fs_reg(31));
+ inst = bld.OR(result, result, fs_reg(1));
inst->predicate = BRW_PREDICATE_NORMAL;
- emit_percomp(inst, instr->dest.write_mask);
break;
- }
case nir_op_frcp:
- emit_math_percomp(SHADER_OPCODE_RCP, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(SHADER_OPCODE_RCP, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_fexp2:
- emit_math_percomp(SHADER_OPCODE_EXP2, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(SHADER_OPCODE_EXP2, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_flog2:
- emit_math_percomp(SHADER_OPCODE_LOG2, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(SHADER_OPCODE_LOG2, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
- case nir_op_fexp:
- case nir_op_flog:
- unreachable("not reached: should be handled by ir_explog_to_explog2");
-
case nir_op_fsin:
- case nir_op_fsin_reduced:
- emit_math_percomp(SHADER_OPCODE_SIN, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(SHADER_OPCODE_SIN, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_fcos:
- case nir_op_fcos_reduced:
- emit_math_percomp(SHADER_OPCODE_COS, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(SHADER_OPCODE_COS, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_fddx:
- if (fs_key->high_quality_derivatives)
- emit_percomp(FS_OPCODE_DDX_FINE, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
- else
- emit_percomp(FS_OPCODE_DDX_COARSE, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ if (fs_key->high_quality_derivatives) {
+ inst = bld.emit(FS_OPCODE_DDX_FINE, result, op[0]);
+ } else {
+ inst = bld.emit(FS_OPCODE_DDX_COARSE, result, op[0]);
+ }
+ inst->saturate = instr->dest.saturate;
+ break;
+ case nir_op_fddx_fine:
+ inst = bld.emit(FS_OPCODE_DDX_FINE, result, op[0]);
+ inst->saturate = instr->dest.saturate;
+ break;
+ case nir_op_fddx_coarse:
+ inst = bld.emit(FS_OPCODE_DDX_COARSE, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_fddy:
- if (fs_key->high_quality_derivatives)
- emit_percomp(FS_OPCODE_DDY_FINE, result, op[0],
- fs_reg(fs_key->render_to_fbo),
- instr->dest.write_mask, instr->dest.saturate);
- else
- emit_percomp(FS_OPCODE_DDY_COARSE, result, op[0],
- fs_reg(fs_key->render_to_fbo),
- instr->dest.write_mask, instr->dest.saturate);
+ if (fs_key->high_quality_derivatives) {
+ inst = bld.emit(FS_OPCODE_DDY_FINE, result, op[0],
+ fs_reg(fs_key->render_to_fbo));
+ } else {
+ inst = bld.emit(FS_OPCODE_DDY_COARSE, result, op[0],
+ fs_reg(fs_key->render_to_fbo));
+ }
+ inst->saturate = instr->dest.saturate;
+ break;
+ case nir_op_fddy_fine:
+ inst = bld.emit(FS_OPCODE_DDY_FINE, result, op[0],
+ fs_reg(fs_key->render_to_fbo));
+ inst->saturate = instr->dest.saturate;
+ break;
+ case nir_op_fddy_coarse:
+ inst = bld.emit(FS_OPCODE_DDY_COARSE, result, op[0],
+ fs_reg(fs_key->render_to_fbo));
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_fadd:
- case nir_op_iadd: {
- fs_inst *inst = ADD(result, op[0], op[1]);
+ case nir_op_iadd:
+ inst = bld.ADD(result, op[0], op[1]);
inst->saturate = instr->dest.saturate;
- emit_percomp(inst, instr->dest.write_mask);
break;
- }
- case nir_op_fmul: {
- fs_inst *inst = MUL(result, op[0], op[1]);
+ case nir_op_fmul:
+ inst = bld.MUL(result, op[0], op[1]);
inst->saturate = instr->dest.saturate;
- emit_percomp(MUL(result, op[0], op[1]), instr->dest.write_mask);
break;
- }
- case nir_op_imul: {
- /* TODO put in the 16-bit constant optimization once we have SSA */
-
- if (brw->gen >= 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width), result.type);
-
- emit_percomp(MUL(acc, op[0], op[1]), instr->dest.write_mask);
- emit_percomp(MACH(reg_null_d, op[0], op[1]), instr->dest.write_mask);
- emit_percomp(MOV(result, fs_reg(acc)), instr->dest.write_mask);
+ case nir_op_imul:
+ bld.MUL(result, op[0], op[1]);
break;
- }
case nir_op_imul_high:
case nir_op_umul_high: {
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width), result.type);
- emit_percomp(MUL(acc, op[0], op[1]), instr->dest.write_mask);
- emit_percomp(MACH(result, op[0], op[1]), instr->dest.write_mask);
+ fs_inst *mul = bld.MUL(acc, op[0], op[1]);
+ bld.MACH(result, op[0], op[1]);
+
+ /* Until Gen8, integer multiplies read 32-bits from one source, and
+ * 16-bits from the other, and relying on the MACH instruction to
+ * generate the high bits of the result.
+ *
+ * On Gen8, the multiply instruction does a full 32x32-bit multiply,
+ * but in order to do a 64x64-bit multiply we have to simulate the
+ * previous behavior and then use a MACH instruction.
+ *
+ * FINISHME: Don't use source modifiers on src1.
+ */
+ if (devinfo->gen >= 8) {
+ assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
+ mul->src[1].type == BRW_REGISTER_TYPE_UD);
+ if (mul->src[1].type == BRW_REGISTER_TYPE_D) {
+ mul->src[1].type = BRW_REGISTER_TYPE_W;
+ mul->src[1].stride = 2;
+ } else {
+ mul->src[1].type = BRW_REGISTER_TYPE_UW;
+ mul->src[1].stride = 2;
+ }
+ }
break;
}
case nir_op_idiv:
case nir_op_udiv:
- emit_math_percomp(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1],
- instr->dest.write_mask);
- break;
-
- case nir_op_uadd_carry: {
- if (brw->gen >= 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
-
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- emit_percomp(ADDC(reg_null_ud, op[0], op[1]), instr->dest.write_mask);
- emit_percomp(MOV(result, fs_reg(acc)), instr->dest.write_mask);
+ bld.emit(SHADER_OPCODE_INT_QUOTIENT, result, op[0], op[1]);
break;
- }
- case nir_op_usub_borrow: {
- if (brw->gen >= 7)
- no16("SIMD16 explicit accumulator operands unsupported\n");
+ case nir_op_uadd_carry:
+ unreachable("Should have been lowered by carry_to_arith().");
- struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
- BRW_REGISTER_TYPE_UD);
-
- emit_percomp(SUBB(reg_null_ud, op[0], op[1]), instr->dest.write_mask);
- emit_percomp(MOV(result, fs_reg(acc)), instr->dest.write_mask);
- break;
- }
+ case nir_op_usub_borrow:
+ unreachable("Should have been lowered by borrow_to_arith().");
case nir_op_umod:
- emit_math_percomp(SHADER_OPCODE_INT_REMAINDER, result, op[0],
- op[1], instr->dest.write_mask);
+ bld.emit(SHADER_OPCODE_INT_REMAINDER, result, op[0], op[1]);
break;
case nir_op_flt:
case nir_op_ilt:
case nir_op_ult:
- emit_percomp(CMP(result, op[0], op[1], BRW_CONDITIONAL_L),
- instr->dest.write_mask);
+ bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_L);
break;
case nir_op_fge:
case nir_op_ige:
case nir_op_uge:
- emit_percomp(CMP(result, op[0], op[1], BRW_CONDITIONAL_GE),
- instr->dest.write_mask);
+ bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_GE);
break;
case nir_op_feq:
case nir_op_ieq:
- emit_percomp(CMP(result, op[0], op[1], BRW_CONDITIONAL_Z),
- instr->dest.write_mask);
+ bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_Z);
break;
case nir_op_fne:
case nir_op_ine:
- emit_percomp(CMP(result, op[0], op[1], BRW_CONDITIONAL_NZ),
- instr->dest.write_mask);
- break;
-
- case nir_op_ball_fequal2:
- case nir_op_ball_iequal2:
- case nir_op_ball_fequal3:
- case nir_op_ball_iequal3:
- case nir_op_ball_fequal4:
- case nir_op_ball_iequal4: {
- unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
- fs_reg temp = fs_reg(GRF, virtual_grf_alloc(num_components));
- emit_percomp(CMP(temp, op[0], op[1], BRW_CONDITIONAL_Z),
- (1 << num_components) - 1);
- emit_reduction(BRW_OPCODE_AND, result, temp, num_components);
+ bld.CMP(result, op[0], op[1], BRW_CONDITIONAL_NZ);
break;
- }
-
- case nir_op_bany_fnequal2:
- case nir_op_bany_inequal2:
- case nir_op_bany_fnequal3:
- case nir_op_bany_inequal3:
- case nir_op_bany_fnequal4:
- case nir_op_bany_inequal4: {
- unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
- fs_reg temp = fs_reg(GRF, virtual_grf_alloc(num_components));
- temp.type = BRW_REGISTER_TYPE_UD;
- emit_percomp(CMP(temp, op[0], op[1], BRW_CONDITIONAL_NZ),
- (1 << num_components) - 1);
- emit_reduction(BRW_OPCODE_OR, result, temp, num_components);
- break;
- }
case nir_op_inot:
- emit_percomp(NOT(result, op[0]), instr->dest.write_mask);
+ if (devinfo->gen >= 8) {
+ resolve_source_modifiers(&op[0]);
+ }
+ bld.NOT(result, op[0]);
break;
case nir_op_ixor:
- emit_percomp(XOR(result, op[0], op[1]), instr->dest.write_mask);
+ if (devinfo->gen >= 8) {
+ resolve_source_modifiers(&op[0]);
+ resolve_source_modifiers(&op[1]);
+ }
+ bld.XOR(result, op[0], op[1]);
break;
case nir_op_ior:
- emit_percomp(OR(result, op[0], op[1]), instr->dest.write_mask);
+ if (devinfo->gen >= 8) {
+ resolve_source_modifiers(&op[0]);
+ resolve_source_modifiers(&op[1]);
+ }
+ bld.OR(result, op[0], op[1]);
break;
case nir_op_iand:
- emit_percomp(AND(result, op[0], op[1]), instr->dest.write_mask);
+ if (devinfo->gen >= 8) {
+ resolve_source_modifiers(&op[0]);
+ resolve_source_modifiers(&op[1]);
+ }
+ bld.AND(result, op[0], op[1]);
break;
case nir_op_fdot2:
case nir_op_fdot3:
- case nir_op_fdot4: {
- unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
- fs_reg temp = fs_reg(GRF, virtual_grf_alloc(num_components));
- emit_percomp(MUL(temp, op[0], op[1]), (1 << num_components) - 1);
- emit_reduction(BRW_OPCODE_ADD, result, temp, num_components);
- if (instr->dest.saturate) {
- fs_inst *inst = emit(MOV(result, result));
- inst->saturate = true;
- }
- break;
- }
-
+ case nir_op_fdot4:
case nir_op_bany2:
case nir_op_bany3:
- case nir_op_bany4: {
- unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
- emit_reduction(BRW_OPCODE_OR, result, op[0], num_components);
- break;
- }
-
+ case nir_op_bany4:
case nir_op_ball2:
case nir_op_ball3:
- case nir_op_ball4: {
- unsigned num_components = nir_op_infos[instr->op].input_sizes[0];
- emit_reduction(BRW_OPCODE_AND, result, op[0], num_components);
- break;
- }
+ case nir_op_ball4:
+ case nir_op_ball_fequal2:
+ case nir_op_ball_iequal2:
+ case nir_op_ball_fequal3:
+ case nir_op_ball_iequal3:
+ case nir_op_ball_fequal4:
+ case nir_op_ball_iequal4:
+ case nir_op_bany_fnequal2:
+ case nir_op_bany_inequal2:
+ case nir_op_bany_fnequal3:
+ case nir_op_bany_inequal3:
+ case nir_op_bany_fnequal4:
+ case nir_op_bany_inequal4:
+ unreachable("Lowered by nir_lower_alu_reductions");
case nir_op_fnoise1_1:
case nir_op_fnoise1_2:
case nir_op_fnoise4_4:
unreachable("not reached: should be handled by lower_noise");
- case nir_op_vec2:
- case nir_op_vec3:
- case nir_op_vec4:
- unreachable("not reached: should be handled by lower_quadop_vector");
-
case nir_op_ldexp:
unreachable("not reached: should be handled by ldexp_to_arith()");
case nir_op_fsqrt:
- emit_math_percomp(SHADER_OPCODE_SQRT, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(SHADER_OPCODE_SQRT, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_frsq:
- emit_math_percomp(SHADER_OPCODE_RSQ, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(SHADER_OPCODE_RSQ, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_b2i:
- emit_percomp(AND(result, op[0], fs_reg(1)), instr->dest.write_mask);
- break;
- case nir_op_b2f: {
- emit_percomp(AND(retype(result, BRW_REGISTER_TYPE_UD), op[0],
- fs_reg(0x3f800000u)),
- instr->dest.write_mask);
+ case nir_op_b2f:
+ bld.MOV(result, negate(op[0]));
break;
- }
case nir_op_f2b:
- emit_percomp(CMP(result, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ),
- instr->dest.write_mask);
+ bld.CMP(result, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ);
break;
case nir_op_i2b:
- emit_percomp(CMP(result, op[0], fs_reg(0), BRW_CONDITIONAL_NZ),
- instr->dest.write_mask);
+ bld.CMP(result, op[0], fs_reg(0), BRW_CONDITIONAL_NZ);
break;
- case nir_op_ftrunc: {
- fs_inst *inst = RNDZ(result, op[0]);
+ case nir_op_ftrunc:
+ inst = bld.RNDZ(result, op[0]);
inst->saturate = instr->dest.saturate;
- emit_percomp(inst, instr->dest.write_mask);
break;
- }
+
case nir_op_fceil: {
op[0].negate = !op[0].negate;
- fs_reg temp = fs_reg(this, glsl_type::vec4_type);
- emit_percomp(RNDD(temp, op[0]), instr->dest.write_mask);
+ fs_reg temp = vgrf(glsl_type::float_type);
+ bld.RNDD(temp, op[0]);
temp.negate = true;
- fs_inst *inst = MOV(result, temp);
+ inst = bld.MOV(result, temp);
inst->saturate = instr->dest.saturate;
- emit_percomp(inst, instr->dest.write_mask);
break;
}
- case nir_op_ffloor: {
- fs_inst *inst = RNDD(result, op[0]);
+ case nir_op_ffloor:
+ inst = bld.RNDD(result, op[0]);
inst->saturate = instr->dest.saturate;
- emit_percomp(inst, instr->dest.write_mask);
break;
- }
- case nir_op_ffract: {
- fs_inst *inst = FRC(result, op[0]);
+ case nir_op_ffract:
+ inst = bld.FRC(result, op[0]);
inst->saturate = instr->dest.saturate;
- emit_percomp(inst, instr->dest.write_mask);
break;
- }
- case nir_op_fround_even: {
- fs_inst *inst = RNDE(result, op[0]);
+ case nir_op_fround_even:
+ inst = bld.RNDE(result, op[0]);
inst->saturate = instr->dest.saturate;
- emit_percomp(inst, instr->dest.write_mask);
break;
- }
case nir_op_fmin:
case nir_op_imin:
case nir_op_umin:
- if (brw->gen >= 6) {
- emit_percomp(BRW_OPCODE_SEL, result, op[0], op[1],
- instr->dest.write_mask, instr->dest.saturate,
- BRW_PREDICATE_NONE, BRW_CONDITIONAL_L);
+ if (devinfo->gen >= 6) {
+ inst = bld.emit(BRW_OPCODE_SEL, result, op[0], op[1]);
+ inst->conditional_mod = BRW_CONDITIONAL_L;
} else {
- emit_percomp(CMP(reg_null_d, op[0], op[1], BRW_CONDITIONAL_L),
- instr->dest.write_mask);
-
- emit_percomp(BRW_OPCODE_SEL, result, op[0], op[1],
- instr->dest.write_mask, instr->dest.saturate,
- BRW_PREDICATE_NORMAL);
+ bld.CMP(bld.null_reg_d(), op[0], op[1], BRW_CONDITIONAL_L);
+ inst = bld.SEL(result, op[0], op[1]);
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_fmax:
case nir_op_imax:
case nir_op_umax:
- if (brw->gen >= 6) {
- emit_percomp(BRW_OPCODE_SEL, result, op[0], op[1],
- instr->dest.write_mask, instr->dest.saturate,
- BRW_PREDICATE_NONE, BRW_CONDITIONAL_GE);
+ if (devinfo->gen >= 6) {
+ inst = bld.emit(BRW_OPCODE_SEL, result, op[0], op[1]);
+ inst->conditional_mod = BRW_CONDITIONAL_GE;
} else {
- emit_percomp(CMP(reg_null_d, op[0], op[1], BRW_CONDITIONAL_GE),
- instr->dest.write_mask);
-
- emit_percomp(BRW_OPCODE_SEL, result, op[0], op[1],
- instr->dest.write_mask, instr->dest.saturate,
- BRW_PREDICATE_NORMAL);
+ bld.CMP(bld.null_reg_d(), op[0], op[1], BRW_CONDITIONAL_GE);
+ inst = bld.SEL(result, op[0], op[1]);
+ inst->predicate = BRW_PREDICATE_NORMAL;
}
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_pack_snorm_2x16:
unreachable("not reached: should be handled by lower_packing_builtins");
case nir_op_unpack_half_2x16_split_x:
- emit_percomp(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_unpack_half_2x16_split_y:
- emit_percomp(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, result, op[0],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, result, op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_fpow:
- emit_percomp(SHADER_OPCODE_POW, result, op[0], op[1],
- instr->dest.write_mask, instr->dest.saturate);
+ inst = bld.emit(SHADER_OPCODE_POW, result, op[0], op[1]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_bitfield_reverse:
- emit_percomp(BFREV(result, op[0]), instr->dest.write_mask);
+ bld.BFREV(result, op[0]);
break;
case nir_op_bit_count:
- emit_percomp(CBIT(result, op[0]), instr->dest.write_mask);
+ bld.CBIT(result, op[0]);
break;
- case nir_op_find_msb: {
- fs_reg temp = fs_reg(this, glsl_type::uvec4_type);
- emit_percomp(FBH(temp, op[0]), instr->dest.write_mask);
+ case nir_op_ufind_msb:
+ case nir_op_ifind_msb: {
+ bld.FBH(retype(result, BRW_REGISTER_TYPE_UD), op[0]);
/* FBH counts from the MSB side, while GLSL's findMSB() wants the count
* from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
* subtract the result from 31 to convert the MSB count into an LSB count.
*/
- emit_percomp(CMP(reg_null_d, temp, fs_reg(~0), BRW_CONDITIONAL_NZ),
- instr->dest.write_mask);
- temp.negate = true;
- fs_inst *inst = ADD(result, temp, fs_reg(31));
+ bld.CMP(bld.null_reg_d(), result, fs_reg(-1), BRW_CONDITIONAL_NZ);
+ fs_reg neg_result(result);
+ neg_result.negate = true;
+ inst = bld.ADD(result, neg_result, fs_reg(31));
inst->predicate = BRW_PREDICATE_NORMAL;
- emit_percomp(inst, instr->dest.write_mask);
break;
}
case nir_op_find_lsb:
- emit_percomp(FBL(result, op[0]), instr->dest.write_mask);
+ bld.FBL(result, op[0]);
break;
case nir_op_ubitfield_extract:
case nir_op_ibitfield_extract:
- emit_percomp(BFE(result, op[2], op[1], op[0]), instr->dest.write_mask);
+ bld.BFE(result, op[2], op[1], op[0]);
break;
case nir_op_bfm:
- emit_percomp(BFI1(result, op[0], op[1]), instr->dest.write_mask);
+ bld.BFI1(result, op[0], op[1]);
break;
case nir_op_bfi:
- emit_percomp(BFI2(result, op[0], op[1], op[2]), instr->dest.write_mask);
+ bld.BFI2(result, op[0], op[1], op[2]);
break;
case nir_op_bitfield_insert:
"lower_instructions::bitfield_insert_to_bfm_bfi");
case nir_op_ishl:
- emit_percomp(SHL(result, op[0], op[1]), instr->dest.write_mask);
+ bld.SHL(result, op[0], op[1]);
break;
case nir_op_ishr:
- emit_percomp(ASR(result, op[0], op[1]), instr->dest.write_mask);
+ bld.ASR(result, op[0], op[1]);
break;
case nir_op_ushr:
- emit_percomp(SHR(result, op[0], op[1]), instr->dest.write_mask);
+ bld.SHR(result, op[0], op[1]);
break;
case nir_op_pack_half_2x16_split:
- emit_percomp(FS_OPCODE_PACK_HALF_2x16_SPLIT, result, op[0], op[1],
- instr->dest.write_mask);
+ bld.emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, result, op[0], op[1]);
break;
case nir_op_ffma:
- emit_percomp(MAD(result, op[2], op[1], op[0]), instr->dest.write_mask);
+ inst = bld.MAD(result, op[2], op[1], op[0]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_flrp:
- /* TODO emulate for gen < 6 */
- emit_percomp(LRP(result, op[2], op[1], op[0]), instr->dest.write_mask);
+ inst = bld.LRP(result, op[0], op[1], op[2]);
+ inst->saturate = instr->dest.saturate;
break;
case nir_op_bcsel:
- emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
- emit_percomp(BRW_OPCODE_SEL, result, op[1], op[2],
- instr->dest.write_mask, false, BRW_PREDICATE_NORMAL);
+ if (optimize_frontfacing_ternary(instr, result))
+ return;
+
+ bld.CMP(bld.null_reg_d(), op[0], fs_reg(0), BRW_CONDITIONAL_NZ);
+ inst = bld.SEL(result, op[1], op[2]);
+ inst->predicate = BRW_PREDICATE_NORMAL;
break;
default:
unreachable("unhandled instruction");
}
- /* emit a predicated move if there was predication */
- if (instr->has_predicate) {
- fs_inst *inst = emit(MOV(reg_null_d,
- retype(get_nir_src(instr->predicate),
- BRW_REGISTER_TYPE_UD)));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
- inst = MOV(dest, result);
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit_percomp(inst, instr->dest.write_mask);
- }
-}
-
-fs_reg
-fs_visitor::get_nir_src(nir_src src)
-{
- struct hash_entry *entry =
- _mesa_hash_table_search(this->nir_reg_ht, src.reg.reg);
- fs_reg reg = *((fs_reg *) entry->data);
- /* to avoid floating-point denorm flushing problems, set the type by
- * default to D - instructions that need floating point semantics will set
- * this to F if they need to
+ /* If we need to do a boolean resolve, replace the result with -(x & 1)
+ * to sign extend the low bit to 0/~0
*/
- reg.type = BRW_REGISTER_TYPE_D;
- reg.reg_offset = src.reg.base_offset;
- if (src.reg.indirect) {
- reg.reladdr = new(mem_ctx) fs_reg();
- *reg.reladdr = retype(get_nir_src(*src.reg.indirect),
- BRW_REGISTER_TYPE_D);
+ if (devinfo->gen <= 5 &&
+ (instr->instr.pass_flags & BRW_NIR_BOOLEAN_MASK) == BRW_NIR_BOOLEAN_NEEDS_RESOLVE) {
+ fs_reg masked = vgrf(glsl_type::int_type);
+ bld.AND(masked, result, fs_reg(1));
+ masked.negate = true;
+ bld.MOV(retype(result, BRW_REGISTER_TYPE_D), masked);
}
-
- return reg;
}
-fs_reg
-fs_visitor::get_nir_alu_src(nir_alu_instr *instr, unsigned src)
+void
+fs_visitor::nir_emit_load_const(const fs_builder &bld,
+ nir_load_const_instr *instr)
{
- fs_reg reg = get_nir_src(instr->src[src].src);
-
- reg.abs = instr->src[src].abs;
- reg.negate = instr->src[src].negate;
+ fs_reg reg = bld.vgrf(BRW_REGISTER_TYPE_D, instr->def.num_components);
- bool needs_swizzle = false;
- unsigned num_components = 0;
- for (unsigned i = 0; i < 4; i++) {
- if (!nir_alu_instr_channel_used(instr, src, i))
- continue;
+ for (unsigned i = 0; i < instr->def.num_components; i++)
+ bld.MOV(offset(reg, bld, i), fs_reg(instr->value.i[i]));
- if (instr->src[src].swizzle[i] != i)
- needs_swizzle = true;
-
- num_components = i + 1;
- }
+ nir_ssa_values[instr->def.index] = reg;
+}
- if (needs_swizzle) {
- /* resolve the swizzle through MOV's */
- fs_reg new_reg = fs_reg(GRF, virtual_grf_alloc(num_components));
+void
+fs_visitor::nir_emit_undef(const fs_builder &bld, nir_ssa_undef_instr *instr)
+{
+ nir_ssa_values[instr->def.index] = bld.vgrf(BRW_REGISTER_TYPE_D,
+ instr->def.num_components);
+}
- for (unsigned i = 0; i < 4; i++) {
- if (!nir_alu_instr_channel_used(instr, src, i))
- continue;
+static fs_reg
+fs_reg_for_nir_reg(fs_visitor *v, nir_register *nir_reg,
+ unsigned base_offset, nir_src *indirect)
+{
+ fs_reg reg;
- fs_reg dest = new_reg;
- dest.type = reg.type;
- dest.reg_offset = i;
+ assert(!nir_reg->is_global);
- fs_reg src0 = reg;
- src0.reg_offset += instr->src[src].swizzle[i];
+ reg = v->nir_locals[nir_reg->index];
- emit(MOV(dest, src0));
- }
+ reg = offset(reg, v->bld, base_offset * nir_reg->num_components);
+ if (indirect) {
+ int multiplier = nir_reg->num_components * (v->dispatch_width / 8);
- return new_reg;
+ reg.reladdr = new(v->mem_ctx) fs_reg(v->vgrf(glsl_type::int_type));
+ v->bld.MUL(*reg.reladdr, v->get_nir_src(*indirect),
+ fs_reg(multiplier));
}
return reg;
}
fs_reg
-fs_visitor::get_nir_dest(nir_dest dest)
+fs_visitor::get_nir_src(nir_src src)
{
- struct hash_entry *entry =
- _mesa_hash_table_search(this->nir_reg_ht, dest.reg.reg);
- fs_reg reg = *((fs_reg *) entry->data);
- reg.reg_offset = dest.reg.base_offset;
- if (dest.reg.indirect) {
- reg.reladdr = new(mem_ctx) fs_reg();
- *reg.reladdr = retype(get_nir_src(*dest.reg.indirect),
- BRW_REGISTER_TYPE_D);
+ fs_reg reg;
+ if (src.is_ssa) {
+ reg = nir_ssa_values[src.ssa->index];
+ } else {
+ reg = fs_reg_for_nir_reg(this, src.reg.reg, src.reg.base_offset,
+ src.reg.indirect);
}
- return reg;
+ /* to avoid floating-point denorm flushing problems, set the type by
+ * default to D - instructions that need floating point semantics will set
+ * this to F if they need to
+ */
+ return retype(reg, BRW_REGISTER_TYPE_D);
}
-void
-fs_visitor::emit_percomp(fs_inst *inst, unsigned wr_mask)
+fs_reg
+fs_visitor::get_nir_dest(nir_dest dest)
{
- for (unsigned i = 0; i < 4; i++) {
- if (!((wr_mask >> i) & 1))
- continue;
-
- fs_inst *new_inst = new(mem_ctx) fs_inst(*inst);
- new_inst->dst.reg_offset += i;
- for (unsigned j = 0; j < new_inst->sources; j++)
- if (inst->src[j].file == GRF)
- new_inst->src[j].reg_offset += i;
-
- emit(new_inst);
+ if (dest.is_ssa) {
+ nir_ssa_values[dest.ssa.index] = bld.vgrf(BRW_REGISTER_TYPE_F,
+ dest.ssa.num_components);
+ return nir_ssa_values[dest.ssa.index];
}
-}
-
-void
-fs_visitor::emit_percomp(enum opcode op, fs_reg dest, fs_reg src0,
- unsigned wr_mask, bool saturate,
- enum brw_predicate predicate,
- enum brw_conditional_mod mod)
-{
- for (unsigned i = 0; i < 4; i++) {
- if (!((wr_mask >> i) & 1))
- continue;
- fs_inst *new_inst = new(mem_ctx) fs_inst(op, dest, src0);
- new_inst->dst.reg_offset += i;
- for (unsigned j = 0; j < new_inst->sources; j++)
- if (new_inst->src[j].file == GRF)
- new_inst->src[j].reg_offset += i;
-
- new_inst->predicate = predicate;
- new_inst->conditional_mod = mod;
- new_inst->saturate = saturate;
- emit(new_inst);
- }
+ return fs_reg_for_nir_reg(this, dest.reg.reg, dest.reg.base_offset,
+ dest.reg.indirect);
}
void
-fs_visitor::emit_percomp(enum opcode op, fs_reg dest, fs_reg src0, fs_reg src1,
- unsigned wr_mask, bool saturate,
- enum brw_predicate predicate,
- enum brw_conditional_mod mod)
+fs_visitor::emit_percomp(const fs_builder &bld, const fs_inst &inst,
+ unsigned wr_mask)
{
for (unsigned i = 0; i < 4; i++) {
if (!((wr_mask >> i) & 1))
continue;
- fs_inst *new_inst = new(mem_ctx) fs_inst(op, dest, src0, src1);
- new_inst->dst.reg_offset += i;
+ fs_inst *new_inst = new(mem_ctx) fs_inst(inst);
+ new_inst->dst = offset(new_inst->dst, bld, i);
for (unsigned j = 0; j < new_inst->sources; j++)
if (new_inst->src[j].file == GRF)
- new_inst->src[j].reg_offset += i;
+ new_inst->src[j] = offset(new_inst->src[j], bld, i);
- new_inst->predicate = predicate;
- new_inst->conditional_mod = mod;
- new_inst->saturate = saturate;
- emit(new_inst);
+ bld.emit(new_inst);
}
}
void
-fs_visitor::emit_math_percomp(enum opcode op, fs_reg dest, fs_reg src0,
- unsigned wr_mask, bool saturate)
-{
- for (unsigned i = 0; i < 4; i++) {
- if (!((wr_mask >> i) & 1))
- continue;
-
- fs_reg new_dest = dest;
- new_dest.reg_offset += i;
- fs_reg new_src0 = src0;
- if (src0.file == GRF)
- new_src0.reg_offset += i;
-
- fs_inst *new_inst = emit_math(op, new_dest, new_src0);
- new_inst->saturate = saturate;
- }
-}
-
-void
-fs_visitor::emit_math_percomp(enum opcode op, fs_reg dest, fs_reg src0,
- fs_reg src1, unsigned wr_mask,
- bool saturate)
-{
- for (unsigned i = 0; i < 4; i++) {
- if (!((wr_mask >> i) & 1))
- continue;
-
- fs_reg new_dest = dest;
- new_dest.reg_offset += i;
- fs_reg new_src0 = src0;
- if (src0.file == GRF)
- new_src0.reg_offset += i;
- fs_reg new_src1 = src1;
- if (src1.file == GRF)
- new_src1.reg_offset += i;
-
- fs_inst *new_inst = emit_math(op, new_dest, new_src0, new_src1);
- new_inst->saturate = saturate;
- }
-}
-
-void
-fs_visitor::emit_reduction(enum opcode op, fs_reg dest, fs_reg src,
- unsigned num_components)
-{
- fs_reg src0 = src;
- fs_reg src1 = src;
- src1.reg_offset++;
-
- if (num_components == 2) {
- emit(op, dest, src0, src1);
- return;
- }
-
- fs_reg temp1 = fs_reg(GRF, virtual_grf_alloc(1));
- temp1.type = src.type;
- emit(op, temp1, src0, src1);
-
- fs_reg src2 = src;
- src2.reg_offset += 2;
-
- if (num_components == 3) {
- emit(op, dest, temp1, src2);
- return;
- }
-
- assert(num_components == 4);
-
- fs_reg src3 = src;
- src3.reg_offset += 3;
- fs_reg temp2 = fs_reg(GRF, virtual_grf_alloc(1));
- temp2.type = src.type;
-
- emit(op, temp2, src2, src3);
- emit(op, dest, temp1, temp2);
-}
-
-void
-fs_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
+fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr *instr)
{
fs_reg dest;
if (nir_intrinsic_infos[instr->intrinsic].has_dest)
dest = get_nir_dest(instr->dest);
- if (instr->has_predicate) {
- fs_inst *inst = emit(MOV(reg_null_d,
- retype(get_nir_src(instr->predicate),
- BRW_REGISTER_TYPE_UD)));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
- }
+
+ bool has_indirect = false;
switch (instr->intrinsic) {
- case nir_intrinsic_discard: {
+ case nir_intrinsic_discard:
+ case nir_intrinsic_discard_if: {
/* We track our discarded pixels in f0.1. By predicating on it, we can
- * update just the flag bits that aren't yet discarded. By emitting a
- * CMP of g0 != g0, all our currently executing channels will get turned
- * off.
+ * update just the flag bits that aren't yet discarded. If there's no
+ * condition, we emit a CMP of g0 != g0, so all currently executing
+ * channels will get turned off.
*/
- fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
- BRW_REGISTER_TYPE_UW));
- fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
- BRW_CONDITIONAL_NZ));
+ fs_inst *cmp;
+ if (instr->intrinsic == nir_intrinsic_discard_if) {
+ cmp = bld.CMP(bld.null_reg_f(), get_nir_src(instr->src[0]),
+ fs_reg(0), BRW_CONDITIONAL_Z);
+ } else {
+ fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
+ BRW_REGISTER_TYPE_UW));
+ cmp = bld.CMP(bld.null_reg_f(), some_reg, some_reg, BRW_CONDITIONAL_NZ);
+ }
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
- if (brw->gen >= 6) {
- /* For performance, after a discard, jump to the end of the shader.
- * Only jump if all relevant channels have been discarded.
- */
- fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
- discard_jump->flag_subreg = 1;
-
- discard_jump->predicate = (dispatch_width == 8)
- ? BRW_PREDICATE_ALIGN1_ANY8H
- : BRW_PREDICATE_ALIGN1_ANY16H;
- discard_jump->predicate_inverse = true;
+ if (devinfo->gen >= 6) {
+ emit_discard_jump();
}
-
break;
}
case nir_intrinsic_atomic_counter_inc:
case nir_intrinsic_atomic_counter_dec:
- case nir_intrinsic_atomic_counter_read:
- assert(!"TODO");
+ case nir_intrinsic_atomic_counter_read: {
+ using namespace surface_access;
+
+ /* Get the arguments of the atomic intrinsic. */
+ const fs_reg offset = get_nir_src(instr->src[0]);
+ const unsigned surface = (stage_prog_data->binding_table.abo_start +
+ instr->const_index[0]);
+ fs_reg tmp;
+
+ /* Emit a surface read or atomic op. */
+ switch (instr->intrinsic) {
+ case nir_intrinsic_atomic_counter_read:
+ tmp = emit_untyped_read(bld, fs_reg(surface), offset, 1, 1);
+ break;
+
+ case nir_intrinsic_atomic_counter_inc:
+ tmp = emit_untyped_atomic(bld, fs_reg(surface), offset, fs_reg(),
+ fs_reg(), 1, 1, BRW_AOP_INC);
+ break;
+
+ case nir_intrinsic_atomic_counter_dec:
+ tmp = emit_untyped_atomic(bld, fs_reg(surface), offset, fs_reg(),
+ fs_reg(), 1, 1, BRW_AOP_PREDEC);
+ break;
+
+ default:
+ unreachable("Unreachable");
+ }
+ /* Assign the result. */
+ bld.MOV(retype(dest, BRW_REGISTER_TYPE_UD), tmp);
+
+ /* Mark the surface as used. */
+ brw_mark_surface_used(stage_prog_data, surface);
+ break;
+ }
+
+ case nir_intrinsic_memory_barrier: {
+ const fs_reg tmp = bld.vgrf(BRW_REGISTER_TYPE_UD, 16 / dispatch_width);
+ bld.emit(SHADER_OPCODE_MEMORY_FENCE, tmp)
+ ->regs_written = 2;
+ break;
+ }
case nir_intrinsic_load_front_face:
- assert(!"TODO");
+ bld.MOV(retype(dest, BRW_REGISTER_TYPE_D),
+ *emit_frontfacing_interpolation());
+ break;
+
+ case nir_intrinsic_load_vertex_id:
+ unreachable("should be lowered by lower_vertex_id()");
+
+ case nir_intrinsic_load_vertex_id_zero_base: {
+ fs_reg vertex_id = nir_system_values[SYSTEM_VALUE_VERTEX_ID_ZERO_BASE];
+ assert(vertex_id.file != BAD_FILE);
+ dest.type = vertex_id.type;
+ bld.MOV(dest, vertex_id);
+ break;
+ }
+
+ case nir_intrinsic_load_base_vertex: {
+ fs_reg base_vertex = nir_system_values[SYSTEM_VALUE_BASE_VERTEX];
+ assert(base_vertex.file != BAD_FILE);
+ dest.type = base_vertex.type;
+ bld.MOV(dest, base_vertex);
+ break;
+ }
+
+ case nir_intrinsic_load_instance_id: {
+ fs_reg instance_id = nir_system_values[SYSTEM_VALUE_INSTANCE_ID];
+ assert(instance_id.file != BAD_FILE);
+ dest.type = instance_id.type;
+ bld.MOV(dest, instance_id);
+ break;
+ }
case nir_intrinsic_load_sample_mask_in: {
- assert(brw->gen >= 7);
- fs_reg reg = fs_reg(retype(brw_vec8_grf(payload.sample_mask_in_reg, 0),
- BRW_REGISTER_TYPE_D));
- dest.type = reg.type;
- fs_inst *inst = MOV(dest, reg);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
+ fs_reg sample_mask_in = nir_system_values[SYSTEM_VALUE_SAMPLE_MASK_IN];
+ assert(sample_mask_in.file != BAD_FILE);
+ dest.type = sample_mask_in.type;
+ bld.MOV(dest, sample_mask_in);
break;
}
case nir_intrinsic_load_sample_pos: {
- fs_reg *reg = emit_samplepos_setup();
- dest.type = reg->type;
- emit(MOV(dest, *reg));
- emit(MOV(offset(dest, 1), offset(*reg, 1)));
+ fs_reg sample_pos = nir_system_values[SYSTEM_VALUE_SAMPLE_POS];
+ assert(sample_pos.file != BAD_FILE);
+ dest.type = sample_pos.type;
+ bld.MOV(dest, sample_pos);
+ bld.MOV(offset(dest, bld, 1), offset(sample_pos, bld, 1));
break;
}
case nir_intrinsic_load_sample_id: {
- fs_reg *reg = emit_sampleid_setup();
- dest.type = reg->type;
- emit(MOV(dest, *reg));
+ fs_reg sample_id = nir_system_values[SYSTEM_VALUE_SAMPLE_ID];
+ assert(sample_id.file != BAD_FILE);
+ dest.type = sample_id.type;
+ bld.MOV(dest, sample_id);
break;
}
- case nir_intrinsic_load_uniform_vec1:
- case nir_intrinsic_load_uniform_vec2:
- case nir_intrinsic_load_uniform_vec3:
- case nir_intrinsic_load_uniform_vec4: {
- unsigned index = 0;
- for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].dest_components; j++) {
- fs_reg src = nir_uniforms;
- src.reg_offset = instr->const_index[0] + index;
- src.type = dest.type;
- index++;
-
- fs_inst *inst = MOV(dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
- dest.reg_offset++;
- }
+ case nir_intrinsic_load_uniform_indirect:
+ has_indirect = true;
+ /* fallthrough */
+ case nir_intrinsic_load_uniform: {
+ unsigned index = instr->const_index[0];
+
+ fs_reg uniform_reg;
+ if (index < num_direct_uniforms) {
+ uniform_reg = fs_reg(UNIFORM, 0);
+ } else {
+ uniform_reg = fs_reg(UNIFORM, num_direct_uniforms);
+ index -= num_direct_uniforms;
}
- break;
- }
- case nir_intrinsic_load_uniform_vec1_indirect:
- case nir_intrinsic_load_uniform_vec2_indirect:
- case nir_intrinsic_load_uniform_vec3_indirect:
- case nir_intrinsic_load_uniform_vec4_indirect: {
- unsigned index = 0;
- for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].dest_components; j++) {
- fs_reg src = nir_uniforms;
- src.reg_offset = instr->const_index[0] + index;
+ for (unsigned j = 0; j < instr->num_components; j++) {
+ fs_reg src = offset(retype(uniform_reg, dest.type), bld, index);
+ if (has_indirect)
src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
- src.reladdr->type = BRW_REGISTER_TYPE_D;
- src.type = dest.type;
- index++;
-
- fs_inst *inst = MOV(dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
- dest.reg_offset++;
- }
+ index++;
+
+ bld.MOV(dest, src);
+ dest = offset(dest, bld, 1);
}
break;
}
- case nir_intrinsic_load_ubo_vec1:
- case nir_intrinsic_load_ubo_vec2:
- case nir_intrinsic_load_ubo_vec3:
- case nir_intrinsic_load_ubo_vec4: {
- fs_reg surf_index = fs_reg(prog_data->binding_table.ubo_start +
- (unsigned) instr->const_index[0]);
- fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
- packed_consts.type = dest.type;
-
- fs_reg const_offset_reg = fs_reg((unsigned) instr->const_index[1] & ~15);
- emit(new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
- packed_consts, surf_index, const_offset_reg));
-
- for (unsigned i = 0;
- i < nir_intrinsic_infos[instr->intrinsic].dest_components; i++) {
- packed_consts.set_smear(instr->const_index[1] % 16 / 4 + i);
-
- /* The std140 packing rules don't allow vectors to cross 16-byte
- * boundaries, and a reg is 32 bytes.
- */
- assert(packed_consts.subreg_offset < 32);
+ case nir_intrinsic_load_ubo_indirect:
+ has_indirect = true;
+ /* fallthrough */
+ case nir_intrinsic_load_ubo: {
+ nir_const_value *const_index = nir_src_as_const_value(instr->src[0]);
+ fs_reg surf_index;
- fs_inst *inst = MOV(dest, packed_consts);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
+ if (const_index) {
+ surf_index = fs_reg(stage_prog_data->binding_table.ubo_start +
+ const_index->u[0]);
+ } else {
+ /* The block index is not a constant. Evaluate the index expression
+ * per-channel and add the base UBO index; we have to select a value
+ * from any live channel.
+ */
+ surf_index = vgrf(glsl_type::uint_type);
+ bld.ADD(surf_index, get_nir_src(instr->src[0]),
+ fs_reg(stage_prog_data->binding_table.ubo_start));
+ surf_index = bld.emit_uniformize(surf_index);
- dest.reg_offset++;
+ /* Assume this may touch any UBO. It would be nice to provide
+ * a tighter bound, but the array information is already lowered away.
+ */
+ brw_mark_surface_used(prog_data,
+ stage_prog_data->binding_table.ubo_start +
+ shader_prog->NumUniformBlocks - 1);
}
- break;
- }
- case nir_intrinsic_load_ubo_vec1_indirect:
- case nir_intrinsic_load_ubo_vec2_indirect:
- case nir_intrinsic_load_ubo_vec3_indirect:
- case nir_intrinsic_load_ubo_vec4_indirect: {
- fs_reg surf_index = fs_reg(prog_data->binding_table.ubo_start +
- instr->const_index[0]);
- /* Turn the byte offset into a dword offset. */
- unsigned base_offset = instr->const_index[1] / 4;
- fs_reg offset = fs_reg(this, glsl_type::int_type);
- emit(SHR(offset, retype(get_nir_src(instr->src[0]), BRW_REGISTER_TYPE_D),
- fs_reg(2)));
-
- for (unsigned i = 0;
- i < nir_intrinsic_infos[instr->intrinsic].dest_components; i++) {
- exec_list list = VARYING_PULL_CONSTANT_LOAD(dest, surf_index,
- offset, base_offset + i);
- fs_inst *last_inst = (fs_inst *) list.get_tail();
- if (instr->has_predicate)
- last_inst->predicate = BRW_PREDICATE_NORMAL;
- emit(list);
-
- dest.reg_offset++;
- }
- break;
- }
+ if (has_indirect) {
+ /* Turn the byte offset into a dword offset. */
+ fs_reg base_offset = vgrf(glsl_type::int_type);
+ bld.SHR(base_offset, retype(get_nir_src(instr->src[1]),
+ BRW_REGISTER_TYPE_D),
+ fs_reg(2));
+
+ unsigned vec4_offset = instr->const_index[0] / 4;
+ for (int i = 0; i < instr->num_components; i++)
+ VARYING_PULL_CONSTANT_LOAD(bld, offset(dest, bld, i), surf_index,
+ base_offset, vec4_offset + i);
+ } else {
+ fs_reg packed_consts = vgrf(glsl_type::float_type);
+ packed_consts.type = dest.type;
- case nir_intrinsic_load_input_vec1:
- case nir_intrinsic_load_input_vec2:
- case nir_intrinsic_load_input_vec3:
- case nir_intrinsic_load_input_vec4: {
- unsigned index = 0;
- for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].dest_components; j++) {
- fs_reg src = nir_inputs;
- src.reg_offset = instr->const_index[0] + index;
- src.type = dest.type;
- index++;
-
- fs_inst *inst = MOV(dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
- dest.reg_offset++;
+ fs_reg const_offset_reg((unsigned) instr->const_index[0] & ~15);
+ bld.emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, packed_consts,
+ surf_index, const_offset_reg);
+
+ for (unsigned i = 0; i < instr->num_components; i++) {
+ packed_consts.set_smear(instr->const_index[0] % 16 / 4 + i);
+
+ /* The std140 packing rules don't allow vectors to cross 16-byte
+ * boundaries, and a reg is 32 bytes.
+ */
+ assert(packed_consts.subreg_offset < 32);
+
+ bld.MOV(dest, packed_consts);
+ dest = offset(dest, bld, 1);
}
}
break;
}
- case nir_intrinsic_load_input_vec1_indirect:
- case nir_intrinsic_load_input_vec2_indirect:
- case nir_intrinsic_load_input_vec3_indirect:
- case nir_intrinsic_load_input_vec4_indirect: {
+ case nir_intrinsic_load_input_indirect:
+ has_indirect = true;
+ /* fallthrough */
+ case nir_intrinsic_load_input: {
unsigned index = 0;
- for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].dest_components; j++) {
- fs_reg src = nir_inputs;
- src.reg_offset = instr->const_index[0] + index;
+ for (unsigned j = 0; j < instr->num_components; j++) {
+ fs_reg src = offset(retype(nir_inputs, dest.type), bld,
+ instr->const_index[0] + index);
+ if (has_indirect)
src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[0]));
- src.reladdr->type = BRW_REGISTER_TYPE_D;
- src.type = dest.type;
- index++;
-
- fs_inst *inst = MOV(dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
- dest.reg_offset++;
- }
+ index++;
+
+ bld.MOV(dest, src);
+ dest = offset(dest, bld, 1);
}
break;
}
- case nir_intrinsic_store_output_vec1:
- case nir_intrinsic_store_output_vec2:
- case nir_intrinsic_store_output_vec3:
- case nir_intrinsic_store_output_vec4: {
- fs_reg src = get_nir_src(instr->src[0]);
- unsigned index = 0;
- for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].src_components[0]; j++) {
- fs_reg new_dest = nir_outputs;
- new_dest.reg_offset = instr->const_index[0] + index;
- new_dest.type = src.type;
- index++;
- fs_inst *inst = MOV(new_dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(inst);
- src.reg_offset++;
+ /* Handle ARB_gpu_shader5 interpolation intrinsics
+ *
+ * It's worth a quick word of explanation as to why we handle the full
+ * variable-based interpolation intrinsic rather than a lowered version
+ * with like we do for other inputs. We have to do that because the way
+ * we set up inputs doesn't allow us to use the already setup inputs for
+ * interpolation. At the beginning of the shader, we go through all of
+ * the input variables and do the initial interpolation and put it in
+ * the nir_inputs array based on its location as determined in
+ * nir_lower_io. If the input isn't used, dead code cleans up and
+ * everything works fine. However, when we get to the ARB_gpu_shader5
+ * interpolation intrinsics, we need to reinterpolate the input
+ * differently. If we used an intrinsic that just had an index it would
+ * only give us the offset into the nir_inputs array. However, this is
+ * useless because that value is post-interpolation and we need
+ * pre-interpolation. In order to get the actual location of the bits
+ * we get from the vertex fetching hardware, we need the variable.
+ */
+ case nir_intrinsic_interp_var_at_centroid:
+ case nir_intrinsic_interp_var_at_sample:
+ case nir_intrinsic_interp_var_at_offset: {
+ assert(stage == MESA_SHADER_FRAGMENT);
+
+ ((struct brw_wm_prog_data *) prog_data)->pulls_bary = true;
+
+ fs_reg dst_xy = bld.vgrf(BRW_REGISTER_TYPE_F, 2);
+
+ /* For most messages, we need one reg of ignored data; the hardware
+ * requires mlen==1 even when there is no payload. in the per-slot
+ * offset case, we'll replace this with the proper source data.
+ */
+ fs_reg src = vgrf(glsl_type::float_type);
+ int mlen = 1; /* one reg unless overriden */
+ fs_inst *inst;
+
+ switch (instr->intrinsic) {
+ case nir_intrinsic_interp_var_at_centroid:
+ inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_CENTROID,
+ dst_xy, src, fs_reg(0u));
+ break;
+
+ case nir_intrinsic_interp_var_at_sample: {
+ /* XXX: We should probably handle non-constant sample id's */
+ nir_const_value *const_sample = nir_src_as_const_value(instr->src[0]);
+ assert(const_sample);
+ unsigned msg_data = const_sample ? const_sample->i[0] << 4 : 0;
+ inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_xy, src,
+ fs_reg(msg_data));
+ break;
+ }
+
+ case nir_intrinsic_interp_var_at_offset: {
+ nir_const_value *const_offset = nir_src_as_const_value(instr->src[0]);
+
+ if (const_offset) {
+ unsigned off_x = MIN2((int)(const_offset->f[0] * 16), 7) & 0xf;
+ unsigned off_y = MIN2((int)(const_offset->f[1] * 16), 7) & 0xf;
+
+ inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_xy, src,
+ fs_reg(off_x | (off_y << 4)));
+ } else {
+ src = vgrf(glsl_type::ivec2_type);
+ fs_reg offset_src = retype(get_nir_src(instr->src[0]),
+ BRW_REGISTER_TYPE_F);
+ for (int i = 0; i < 2; i++) {
+ fs_reg temp = vgrf(glsl_type::float_type);
+ bld.MUL(temp, offset(offset_src, bld, i), fs_reg(16.0f));
+ fs_reg itemp = vgrf(glsl_type::int_type);
+ bld.MOV(itemp, temp); /* float to int */
+
+ /* Clamp the upper end of the range to +7/16.
+ * ARB_gpu_shader5 requires that we support a maximum offset
+ * of +0.5, which isn't representable in a S0.4 value -- if
+ * we didn't clamp it, we'd end up with -8/16, which is the
+ * opposite of what the shader author wanted.
+ *
+ * This is legal due to ARB_gpu_shader5's quantization
+ * rules:
+ *
+ * "Not all values of <offset> may be supported; x and y
+ * offsets may be rounded to fixed-point values with the
+ * number of fraction bits given by the
+ * implementation-dependent constant
+ * FRAGMENT_INTERPOLATION_OFFSET_BITS"
+ */
+ set_condmod(BRW_CONDITIONAL_L,
+ bld.SEL(offset(src, bld, i), itemp, fs_reg(7)));
+ }
+
+ mlen = 2 * dispatch_width / 8;
+ inst = bld.emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, dst_xy, src,
+ fs_reg(0u));
}
+ break;
+ }
+
+ default:
+ unreachable("Invalid intrinsic");
+ }
+
+ inst->mlen = mlen;
+ /* 2 floats per slot returned */
+ inst->regs_written = 2 * dispatch_width / 8;
+ inst->pi_noperspective = instr->variables[0]->var->data.interpolation ==
+ INTERP_QUALIFIER_NOPERSPECTIVE;
+
+ for (unsigned j = 0; j < instr->num_components; j++) {
+ fs_reg src = interp_reg(instr->variables[0]->var->data.location, j);
+ src.type = dest.type;
+
+ bld.emit(FS_OPCODE_LINTERP, dest, dst_xy, src);
+ dest = offset(dest, bld, 1);
}
break;
}
- case nir_intrinsic_store_output_vec1_indirect:
- case nir_intrinsic_store_output_vec2_indirect:
- case nir_intrinsic_store_output_vec3_indirect:
- case nir_intrinsic_store_output_vec4_indirect: {
+ case nir_intrinsic_store_output_indirect:
+ has_indirect = true;
+ /* fallthrough */
+ case nir_intrinsic_store_output: {
fs_reg src = get_nir_src(instr->src[0]);
- fs_reg indirect = get_nir_src(instr->src[1]);
unsigned index = 0;
- for (int i = 0; i < instr->const_index[1]; i++) {
- for (unsigned j = 0;
- j < nir_intrinsic_infos[instr->intrinsic].src_components[0]; j++) {
- fs_reg new_dest = nir_outputs;
- new_dest.reg_offset = instr->const_index[0] + index;
- new_dest.reladdr = new(mem_ctx) fs_reg(indirect);
- new_dest.type = src.type;
- index++;
- fs_inst *inst = MOV(new_dest, src);
- if (instr->has_predicate)
- inst->predicate = BRW_PREDICATE_NORMAL;
- emit(MOV(new_dest, src));
- src.reg_offset++;
- }
+ for (unsigned j = 0; j < instr->num_components; j++) {
+ fs_reg new_dest = offset(retype(nir_outputs, src.type), bld,
+ instr->const_index[0] + index);
+ if (has_indirect)
+ src.reladdr = new(mem_ctx) fs_reg(get_nir_src(instr->src[1]));
+ index++;
+ bld.MOV(new_dest, src);
+ src = offset(src, bld, 1);
}
break;
}
+ case nir_intrinsic_barrier:
+ emit_barrier();
+ break;
+
default:
unreachable("unknown intrinsic");
}
}
void
-fs_visitor::nir_emit_texture(nir_tex_instr *instr)
+fs_visitor::nir_emit_texture(const fs_builder &bld, nir_tex_instr *instr)
{
- brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
unsigned sampler = instr->sampler_index;
+ fs_reg sampler_reg(sampler);
/* FINISHME: We're failing to recompile our programs when the sampler is
* updated. This only matters for the texture rectangle scale parameters
bool is_cube_array = instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE &&
instr->is_array;
- int lod_components, offset_components = 0;
+ int lod_components = 0;
+ int UNUSED offset_components = 0;
- fs_reg coordinate, shadow_comparitor, lod, lod2, sample_index, mcs, offset;
+ fs_reg coordinate, shadow_comparitor, lod, lod2, sample_index, mcs, tex_offset;
for (unsigned i = 0; i < instr->num_srcs; i++) {
- fs_reg src = get_nir_src(instr->src[i]);
- switch (instr->src_type[i]) {
+ fs_reg src = get_nir_src(instr->src[i].src);
+ switch (instr->src[i].src_type) {
case nir_tex_src_bias:
lod = retype(src, BRW_REGISTER_TYPE_F);
break;
sample_index = retype(src, BRW_REGISTER_TYPE_UD);
break;
case nir_tex_src_offset:
- offset = retype(src, BRW_REGISTER_TYPE_D);
+ tex_offset = retype(src, BRW_REGISTER_TYPE_D);
if (instr->is_array)
offset_components = instr->coord_components - 1;
else
break;
case nir_tex_src_projector:
unreachable("should be lowered");
- case nir_tex_src_sampler_index:
- unreachable("not yet supported");
+
+ case nir_tex_src_sampler_offset: {
+ /* Figure out the highest possible sampler index and mark it as used */
+ uint32_t max_used = sampler + instr->sampler_array_size - 1;
+ if (instr->op == nir_texop_tg4 && devinfo->gen < 8) {
+ max_used += stage_prog_data->binding_table.gather_texture_start;
+ } else {
+ max_used += stage_prog_data->binding_table.texture_start;
+ }
+ brw_mark_surface_used(prog_data, max_used);
+
+ /* Emit code to evaluate the actual indexing expression */
+ sampler_reg = vgrf(glsl_type::uint_type);
+ bld.ADD(sampler_reg, src, fs_reg(sampler));
+ sampler_reg = bld.emit_uniformize(sampler_reg);
+ break;
+ }
+
default:
unreachable("unknown texture source");
}
}
if (instr->op == nir_texop_txf_ms) {
- if (brw->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
- mcs = emit_mcs_fetch(coordinate, instr->coord_components, fs_reg(sampler));
- else
+ if (devinfo->gen >= 7 &&
+ key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
+ mcs = emit_mcs_fetch(coordinate, instr->coord_components, sampler_reg);
+ } else {
mcs = fs_reg(0u);
+ }
}
for (unsigned i = 0; i < 3; i++) {
if (instr->const_offset[i] != 0) {
assert(offset_components == 0);
- offset = fs_reg(brw_texture_offset(ctx, instr->const_offset, 3));
+ tex_offset = fs_reg(brw_texture_offset(instr->const_offset, 3));
break;
}
}
emit_texture(op, dest_type, coordinate, instr->coord_components,
shadow_comparitor, lod, lod2, lod_components, sample_index,
- offset, offset_components, mcs, gather_component,
- is_cube_array, is_rect, sampler, fs_reg(sampler), texunit);
+ tex_offset, mcs, gather_component,
+ is_cube_array, is_rect, sampler, sampler_reg, texunit);
fs_reg dest = get_nir_dest(instr->dest);
dest.type = this->result.type;
unsigned num_components = nir_tex_instr_dest_size(instr);
- emit_percomp(MOV(dest, this->result), (1 << num_components) - 1);
-}
-
-void
-fs_visitor::nir_emit_load_const(nir_load_const_instr *instr)
-{
- fs_reg dest = get_nir_dest(instr->dest);
- dest.type = BRW_REGISTER_TYPE_UD;
- if (instr->array_elems == 0) {
- for (unsigned i = 0; i < instr->num_components; i++) {
- emit(MOV(dest, fs_reg(instr->value.u[i])));
- dest.reg_offset++;
- }
- } else {
- for (unsigned i = 0; i < instr->array_elems; i++) {
- for (unsigned j = 0; j < instr->num_components; j++) {
- emit(MOV(dest, fs_reg(instr->array[i].u[j])));
- dest.reg_offset++;
- }
- }
- }
+ emit_percomp(bld, fs_inst(BRW_OPCODE_MOV, bld.dispatch_width(),
+ dest, this->result),
+ (1 << num_components) - 1);
}
void
-fs_visitor::nir_emit_jump(nir_jump_instr *instr)
+fs_visitor::nir_emit_jump(const fs_builder &bld, nir_jump_instr *instr)
{
switch (instr->type) {
case nir_jump_break:
- emit(BRW_OPCODE_BREAK);
+ bld.emit(BRW_OPCODE_BREAK);
break;
case nir_jump_continue:
- emit(BRW_OPCODE_CONTINUE);
+ bld.emit(BRW_OPCODE_CONTINUE);
break;
case nir_jump_return:
default:
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