#include "glsl/glsl_types.h"
#include "glsl/ir_optimization.h"
+using namespace brw;
+
static void
assign_reg(unsigned *reg_hw_locations, fs_reg *reg)
{
}
static void
-brw_alloc_reg_set(struct intel_screen *screen, int reg_width)
+brw_alloc_reg_set(struct brw_compiler *compiler, int reg_width)
{
- const struct brw_device_info *devinfo = screen->devinfo;
+ const struct brw_device_info *devinfo = compiler->devinfo;
int base_reg_count = BRW_MAX_GRF;
int index = reg_width - 1;
class_sizes[class_count++] = 8;
}
- memset(screen->wm_reg_sets[index].class_to_ra_reg_range, 0,
- sizeof(screen->wm_reg_sets[index].class_to_ra_reg_range));
- int *class_to_ra_reg_range = screen->wm_reg_sets[index].class_to_ra_reg_range;
+ memset(compiler->fs_reg_sets[index].class_to_ra_reg_range, 0,
+ sizeof(compiler->fs_reg_sets[index].class_to_ra_reg_range));
+ int *class_to_ra_reg_range = compiler->fs_reg_sets[index].class_to_ra_reg_range;
/* Compute the total number of registers across all classes. */
int ra_reg_count = 0;
class_to_ra_reg_range[i] = class_to_ra_reg_range[i-1];
}
- uint8_t *ra_reg_to_grf = ralloc_array(screen, uint8_t, ra_reg_count);
- struct ra_regs *regs = ra_alloc_reg_set(screen, ra_reg_count);
+ uint8_t *ra_reg_to_grf = ralloc_array(compiler, uint8_t, ra_reg_count);
+ struct ra_regs *regs = ra_alloc_reg_set(compiler, ra_reg_count);
if (devinfo->gen >= 6)
ra_set_allocate_round_robin(regs);
- int *classes = ralloc_array(screen, int, class_count);
+ int *classes = ralloc_array(compiler, int, class_count);
int aligned_pairs_class = -1;
/* Allocate space for q values. We allocate class_count + 1 because we
* want to leave room for the aligned pairs class if we have it. */
- unsigned int **q_values = ralloc_array(screen, unsigned int *,
+ unsigned int **q_values = ralloc_array(compiler, unsigned int *,
class_count + 1);
for (int i = 0; i < class_count + 1; ++i)
q_values[i] = ralloc_array(q_values, unsigned int, class_count + 1);
}
assert(reg == ra_reg_count);
- /* Add a special class for aligned pairs, which we'll put delta_x/y
+ /* Add a special class for aligned pairs, which we'll put delta_xy
* in on Gen <= 6 so that we can do PLN.
*/
if (devinfo->has_pln && reg_width == 1 && devinfo->gen <= 6) {
ralloc_free(q_values);
- screen->wm_reg_sets[index].regs = regs;
- for (unsigned i = 0; i < ARRAY_SIZE(screen->wm_reg_sets[index].classes); i++)
- screen->wm_reg_sets[index].classes[i] = -1;
+ compiler->fs_reg_sets[index].regs = regs;
+ for (unsigned i = 0; i < ARRAY_SIZE(compiler->fs_reg_sets[index].classes); i++)
+ compiler->fs_reg_sets[index].classes[i] = -1;
for (int i = 0; i < class_count; i++)
- screen->wm_reg_sets[index].classes[class_sizes[i] - 1] = classes[i];
- screen->wm_reg_sets[index].ra_reg_to_grf = ra_reg_to_grf;
- screen->wm_reg_sets[index].aligned_pairs_class = aligned_pairs_class;
+ compiler->fs_reg_sets[index].classes[class_sizes[i] - 1] = classes[i];
+ compiler->fs_reg_sets[index].ra_reg_to_grf = ra_reg_to_grf;
+ compiler->fs_reg_sets[index].aligned_pairs_class = aligned_pairs_class;
}
void
-brw_fs_alloc_reg_sets(struct intel_screen *screen)
+brw_fs_alloc_reg_sets(struct brw_compiler *compiler)
{
- brw_alloc_reg_set(screen, 1);
- brw_alloc_reg_set(screen, 2);
+ brw_alloc_reg_set(compiler, 1);
+ brw_alloc_reg_set(compiler, 2);
}
static int
int loop_end_ip = 0;
int payload_last_use_ip[payload_node_count];
- memset(payload_last_use_ip, 0, sizeof(payload_last_use_ip));
+ for (int i = 0; i < payload_node_count; i++)
+ payload_last_use_ip[i] = -1;
+
int ip = 0;
foreach_block_and_inst(block, fs_inst, inst, cfg) {
switch (inst->opcode) {
if (node_nr >= payload_node_count)
continue;
- payload_last_use_ip[node_nr] = use_ip;
+ for (int j = 0; j < inst->regs_read(i); j++) {
+ payload_last_use_ip[node_nr + j] = use_ip;
+ assert(node_nr + j < payload_node_count);
+ }
}
}
/* Special case instructions which have extra implied registers used. */
switch (inst->opcode) {
- case FS_OPCODE_LINTERP:
- /* On gen6+ in SIMD16, there are 4 adjacent registers used by
- * PLN's sourcing of the deltas, while we list only the first one
- * in the arguments. Pre-gen6, the deltas are computed in normal
- * VGRFs.
- */
- if (brw->gen >= 6) {
- int delta_x_arg = 0;
- if (inst->src[delta_x_arg].file == HW_REG &&
- inst->src[delta_x_arg].fixed_hw_reg.file ==
- BRW_GENERAL_REGISTER_FILE) {
- for (int i = 1; i < 4; ++i) {
- int node = inst->src[delta_x_arg].fixed_hw_reg.nr + i;
- assert(node < payload_node_count);
- payload_last_use_ip[node] = use_ip;
- }
- }
- }
+ case CS_OPCODE_CS_TERMINATE:
+ payload_last_use_ip[0] = use_ip;
break;
default:
}
for (int i = 0; i < payload_node_count; i++) {
+ if (payload_last_use_ip[i] == -1)
+ continue;
+
/* Mark the payload node as interfering with any virtual grf that is
* live between the start of the program and our last use of the payload
* node.
* The alternative would be to have per-physical-register classes, which
* would just be silly.
*/
- if (brw->intelScreen->devinfo->gen <= 5 && dispatch_width == 16) {
+ if (devinfo->gen <= 5 && dispatch_width == 16) {
/* We have to divide by 2 here because we only have even numbered
* registers. Some of the payload registers will be odd, but
* that's ok because their physical register numbers have already
* see if we can actually use MRFs to do spills without overwriting normal MRF
* contents.
*/
-void
-fs_visitor::get_used_mrfs(bool *mrf_used)
+static void
+get_used_mrfs(fs_visitor *v, bool *mrf_used)
{
- int reg_width = dispatch_width / 8;
+ int reg_width = v->dispatch_width / 8;
memset(mrf_used, 0, BRW_MAX_MRF * sizeof(bool));
- foreach_block_and_inst(block, fs_inst, inst, cfg) {
+ foreach_block_and_inst(block, fs_inst, inst, v->cfg) {
if (inst->dst.file == MRF) {
int reg = inst->dst.reg & ~BRW_MRF_COMPR4;
mrf_used[reg] = true;
}
if (inst->mlen > 0) {
- for (int i = 0; i < implied_mrf_writes(inst); i++) {
+ for (int i = 0; i < v->implied_mrf_writes(inst); i++) {
mrf_used[inst->base_mrf + i] = true;
}
}
* Sets interference between virtual GRFs and usage of the high GRFs for SEND
* messages (treated as MRFs in code generation).
*/
-void
-fs_visitor::setup_mrf_hack_interference(struct ra_graph *g, int first_mrf_node)
+static void
+setup_mrf_hack_interference(fs_visitor *v, struct ra_graph *g,
+ int first_mrf_node, int *first_used_mrf)
{
bool mrf_used[BRW_MAX_MRF];
- get_used_mrfs(mrf_used);
+ get_used_mrfs(v, mrf_used);
+ *first_used_mrf = BRW_MAX_MRF;
for (int i = 0; i < BRW_MAX_MRF; i++) {
/* Mark each MRF reg node as being allocated to its physical register.
*
* that are used as conflicting with all virtual GRFs.
*/
if (mrf_used[i]) {
- for (unsigned j = 0; j < this->alloc.count; j++) {
+ if (i < *first_used_mrf)
+ *first_used_mrf = i;
+
+ for (unsigned j = 0; j < v->alloc.count; j++) {
ra_add_node_interference(g, first_mrf_node + i, j);
}
}
bool
fs_visitor::assign_regs(bool allow_spilling)
{
- struct intel_screen *screen = brw->intelScreen;
/* Most of this allocation was written for a reg_width of 1
* (dispatch_width == 8). In extending to SIMD16, the code was
* left in place and it was converted to have the hardware
int reg_width = dispatch_width / 8;
unsigned hw_reg_mapping[this->alloc.count];
int payload_node_count = ALIGN(this->first_non_payload_grf, reg_width);
- int rsi = reg_width - 1; /* Which screen->wm_reg_sets[] to use */
+ int rsi = reg_width - 1; /* Which compiler->fs_reg_sets[] to use */
calculate_live_intervals();
int node_count = this->alloc.count;
int first_payload_node = node_count;
node_count += payload_node_count;
int first_mrf_hack_node = node_count;
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START;
struct ra_graph *g =
- ra_alloc_interference_graph(screen->wm_reg_sets[rsi].regs, node_count);
+ ra_alloc_interference_graph(compiler->fs_reg_sets[rsi].regs, node_count);
for (unsigned i = 0; i < this->alloc.count; i++) {
unsigned size = this->alloc.sizes[i];
int c;
- assert(size <= ARRAY_SIZE(screen->wm_reg_sets[rsi].classes) &&
+ assert(size <= ARRAY_SIZE(compiler->fs_reg_sets[rsi].classes) &&
"Register allocation relies on split_virtual_grfs()");
- c = screen->wm_reg_sets[rsi].classes[size - 1];
+ c = compiler->fs_reg_sets[rsi].classes[size - 1];
/* Special case: on pre-GEN6 hardware that supports PLN, the
* second operand of a PLN instruction needs to be an
* even-numbered register, so we have a special register class
* wm_aligned_pairs_class to handle this case. pre-GEN6 always
- * uses this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
+ * uses this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] as the
* second operand of a PLN instruction (since it doesn't support
* any other interpolation modes). So all we need to do is find
* that register and set it to the appropriate class.
*/
- if (screen->wm_reg_sets[rsi].aligned_pairs_class >= 0 &&
- this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF &&
- this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg == i) {
- c = screen->wm_reg_sets[rsi].aligned_pairs_class;
+ if (compiler->fs_reg_sets[rsi].aligned_pairs_class >= 0 &&
+ this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].file == GRF &&
+ this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg == i) {
+ c = compiler->fs_reg_sets[rsi].aligned_pairs_class;
}
ra_set_node_class(g, i, c);
}
setup_payload_interference(g, payload_node_count, first_payload_node);
- if (brw->gen >= 7) {
- setup_mrf_hack_interference(g, first_mrf_hack_node);
+ if (devinfo->gen >= 7) {
+ int first_used_mrf = BRW_MAX_MRF;
+ setup_mrf_hack_interference(this, g, first_mrf_hack_node,
+ &first_used_mrf);
foreach_block_and_inst(block, fs_inst, inst, cfg) {
/* When we do send-from-GRF for FB writes, we need to ensure that
*/
if (inst->eot) {
int size = alloc.sizes[inst->src[0].reg];
- int reg = screen->wm_reg_sets[rsi].class_to_ra_reg_range[size] - 1;
+ int reg = compiler->fs_reg_sets[rsi].class_to_ra_reg_range[size] - 1;
+
+ /* If something happened to spill, we want to push the EOT send
+ * register early enough in the register file that we don't
+ * conflict with any used MRF hack registers.
+ */
+ reg -= BRW_MAX_MRF - first_used_mrf;
+
ra_set_node_reg(g, inst->src[0].reg, reg);
break;
}
}
/* Debug of register spilling: Go spill everything. */
- if (0) {
+ if (unlikely(INTEL_DEBUG & DEBUG_SPILL)) {
int reg = choose_spill_reg(g);
if (reg != -1) {
for (unsigned i = 0; i < this->alloc.count; i++) {
int reg = ra_get_node_reg(g, i);
- hw_reg_mapping[i] = screen->wm_reg_sets[rsi].ra_reg_to_grf[reg];
+ hw_reg_mapping[i] = compiler->fs_reg_sets[rsi].ra_reg_to_grf[reg];
this->grf_used = MAX2(this->grf_used,
hw_reg_mapping[i] + this->alloc.sizes[i]);
}
uint32_t spill_offset, int count)
{
int reg_size = 1;
- if (dispatch_width == 16 && count % 2 == 0) {
+ if (dispatch_width == 16 && count % 2 == 0)
reg_size = 2;
- dst.width = 16;
- }
+
+ const fs_builder ibld = bld.annotate(inst->annotation, inst->ir)
+ .group(reg_size * 8, 0)
+ .at(block, inst);
for (int i = 0; i < count / reg_size; i++) {
/* The gen7 descriptor-based offset is 12 bits of HWORD units. */
- bool gen7_read = brw->gen >= 7 && spill_offset < (1 << 12) * REG_SIZE;
-
- fs_inst *unspill_inst =
- new(mem_ctx) fs_inst(gen7_read ?
- SHADER_OPCODE_GEN7_SCRATCH_READ :
- SHADER_OPCODE_GEN4_SCRATCH_READ,
- dst);
+ bool gen7_read = devinfo->gen >= 7 && spill_offset < (1 << 12) * REG_SIZE;
+ fs_inst *unspill_inst = ibld.emit(gen7_read ?
+ SHADER_OPCODE_GEN7_SCRATCH_READ :
+ SHADER_OPCODE_GEN4_SCRATCH_READ,
+ dst);
unspill_inst->offset = spill_offset;
- unspill_inst->ir = inst->ir;
- unspill_inst->annotation = inst->annotation;
unspill_inst->regs_written = reg_size;
if (!gen7_read) {
unspill_inst->base_mrf = 14;
unspill_inst->mlen = 1; /* header contains offset */
}
- inst->insert_before(block, unspill_inst);
dst.reg_offset += reg_size;
spill_offset += reg_size * REG_SIZE;
reg_size = 2;
}
+ const fs_builder ibld = bld.annotate(inst->annotation, inst->ir)
+ .group(reg_size * 8, 0)
+ .at(block, inst->next);
+
for (int i = 0; i < count / reg_size; i++) {
fs_inst *spill_inst =
- new(mem_ctx) fs_inst(SHADER_OPCODE_GEN4_SCRATCH_WRITE,
- reg_size * 8, reg_null_f, src);
+ ibld.emit(SHADER_OPCODE_GEN4_SCRATCH_WRITE, ibld.null_reg_f(), src);
src.reg_offset += reg_size;
spill_inst->offset = spill_offset + i * reg_size * REG_SIZE;
- spill_inst->ir = inst->ir;
- spill_inst->annotation = inst->annotation;
spill_inst->mlen = 1 + reg_size; /* header, value */
spill_inst->base_mrf = spill_base_mrf;
- inst->insert_after(block, spill_inst);
}
}
*/
if (!spilled_any_registers) {
bool mrf_used[BRW_MAX_MRF];
- get_used_mrfs(mrf_used);
+ get_used_mrfs(this, mrf_used);
for (int i = spill_base_mrf; i < BRW_MAX_MRF; i++) {
if (mrf_used[i]) {
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