i965/fs: Add support for translating ir_triop_fma into MAD.

[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_reg_allocate.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index b8936dcfe7d10c1e49074a6ccb37f33e2b95c354..b9102d97e1fe4bef710cff82c431207ca2169740 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -28,7 +28,6 @@
 #include "brw_fs.h"
 #include "glsl/glsl_types.h"
 #include "glsl/ir_optimization.h"
-#include "glsl/ir_print_visitor.h"
 
 static void
 assign_reg(int *reg_hw_locations, fs_reg *reg, int reg_width)
@@ -74,7 +73,6 @@ fs_visitor::assign_regs_trivial()
 static void
 brw_alloc_reg_set(struct brw_context *brw, int reg_width)
 {
-   struct intel_context *intel = &brw->intel;
    int base_reg_count = BRW_MAX_GRF / reg_width;
    int index = reg_width - 1;
 
@@ -108,6 +106,8 @@ brw_alloc_reg_set(struct brw_context *brw, int reg_width)
 
    uint8_t *ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
    struct ra_regs *regs = ra_alloc_reg_set(brw, ra_reg_count);
+   if (brw->gen >= 6)
+      ra_set_allocate_round_robin(regs);
    int *classes = ralloc_array(brw, int, class_count);
    int aligned_pairs_class = -1;
 
@@ -146,7 +146,7 @@ brw_alloc_reg_set(struct brw_context *brw, int reg_width)
    /* Add a special class for aligned pairs, which we'll put delta_x/y
     * in on gen5 so that we can do PLN.
     */
-   if (brw->has_pln && reg_width == 1 && intel->gen < 6) {
+   if (brw->has_pln && reg_width == 1 && brw->gen < 6) {
       aligned_pairs_class = ra_alloc_reg_class(regs);
 
       for (int i = 0; i < pairs_reg_count; i++) {
@@ -256,7 +256,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
        * the start (see interp_reg()).
        */
       for (int i = 0; i < 3; i++) {
-         if (inst->src[i].file == FIXED_HW_REG &&
+         if (inst->src[i].file == HW_REG &&
              inst->src[i].fixed_hw_reg.file == BRW_GENERAL_REGISTER_FILE) {
             int node_nr = inst->src[i].fixed_hw_reg.nr / reg_width;
             if (node_nr >= payload_node_count)
@@ -284,9 +284,9 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
           * two in the arguments (1 node).  Pre-gen6, the deltas are computed
           * in normal VGRFs.
           */
-         if (intel->gen >= 6) {
+         if (brw->gen >= 6) {
             int delta_x_arg = 0;
-            if (inst->src[delta_x_arg].file == FIXED_HW_REG &&
+            if (inst->src[delta_x_arg].file == HW_REG &&
                 inst->src[delta_x_arg].fixed_hw_reg.file ==
                 BRW_GENERAL_REGISTER_FILE) {
                int sechalf_node = (inst->src[delta_x_arg].fixed_hw_reg.nr /
@@ -314,8 +314,7 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
           * in order to not have to worry about the uniform issue described in
           * calculate_live_intervals().
           */
-         if (this->virtual_grf_def[j] <= payload_last_use_ip[i] ||
-             this->virtual_grf_use[j] <= payload_last_use_ip[i]) {
+         if (this->virtual_grf_start[j] <= payload_last_use_ip[i]) {
             ra_add_node_interference(g, first_payload_node + i, j);
          }
       }
@@ -406,7 +405,7 @@ fs_visitor::assign_regs()
    int first_payload_node = node_count;
    node_count += payload_node_count;
    int first_mrf_hack_node = node_count;
-   if (intel->gen >= 7)
+   if (brw->gen >= 7)
       node_count += BRW_MAX_GRF - GEN7_MRF_HACK_START;
    struct ra_graph *g = ra_alloc_interference_graph(brw->wm.reg_sets[rsi].regs,
                                                     node_count);
@@ -448,7 +447,7 @@ fs_visitor::assign_regs()
    }
 
    setup_payload_interference(g, payload_node_count, first_payload_node);
-   if (intel->gen >= 7)
+   if (brw->gen >= 7)
       setup_mrf_hack_interference(g, first_mrf_hack_node);
 
    if (!ra_allocate_no_spills(g)) {
@@ -458,7 +457,8 @@ fs_visitor::assign_regs()
       int reg = choose_spill_reg(g);
 
       if (reg == -1) {
-        fail("no register to spill\n");
+         fail("no register to spill:\n");
+         dump_instructions();
       } else if (dispatch_width == 16) {
         fail("Failure to register allocate.  Reduce number of live scalar "
               "values to avoid this.");
@@ -553,7 +553,7 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
       }
 
       if (inst->dst.file == GRF) {
-        spill_costs[inst->dst.reg] += inst->regs_written() * loop_scale;
+        spill_costs[inst->dst.reg] += inst->regs_written * loop_scale;
 
          if (inst->dst.smear >= 0) {
             no_spill[inst->dst.reg] = true;
@@ -622,7 +622,7 @@ fs_visitor::spill_reg(int spill_reg)
          inst->dst.reg == spill_reg) {
          int subset_spill_offset = (spill_offset +
                                     REG_SIZE * inst->dst.reg_offset);
-         inst->dst.reg = virtual_grf_alloc(inst->regs_written());
+         inst->dst.reg = virtual_grf_alloc(inst->regs_written);
          inst->dst.reg_offset = 0;
 
         /* If our write is going to affect just part of the
@@ -631,7 +631,7 @@ fs_visitor::spill_reg(int spill_reg)
          */
         if (inst->predicate || inst->force_uncompressed || inst->force_sechalf) {
             fs_reg unspill_reg = inst->dst;
-            for (int chan = 0; chan < inst->regs_written(); chan++) {
+            for (int chan = 0; chan < inst->regs_written; chan++) {
                emit_unspill(inst, unspill_reg,
                             subset_spill_offset + REG_SIZE * chan);
                unspill_reg.reg_offset++;
@@ -644,7 +644,7 @@ fs_visitor::spill_reg(int spill_reg)
         spill_src.negate = false;
         spill_src.smear = -1;
 
-        for (int chan = 0; chan < inst->regs_written(); chan++) {
+        for (int chan = 0; chan < inst->regs_written; chan++) {
            fs_inst *spill_inst = new(mem_ctx) fs_inst(FS_OPCODE_SPILL,
                                                       reg_null_f, spill_src);
            spill_src.reg_offset++;