i965: Add HiZ operation state to brw_context

[mesa.git] / src / mesa / drivers / dri / i965 / brw_fs_schedule_instructions.cpp

diff --git a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
index 0ea4e5c36f091b0e47b982c472a0c3b6dbb71a9a..910f3297d27d14a34f16280356478319cc2e9858 100644 (file)
--- a/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_schedule_instructions.cpp
@@ -26,9 +26,9 @@
  */
 
 #include "brw_fs.h"
-#include "../glsl/glsl_types.h"
-#include "../glsl/ir_optimization.h"
-#include "../glsl/ir_print_visitor.h"
+#include "glsl/glsl_types.h"
+#include "glsl/ir_optimization.h"
+#include "glsl/ir_print_visitor.h"
 
 /** @file brw_fs_schedule_instructions.cpp
  *
@@ -75,11 +75,13 @@ public:
       case SHADER_OPCODE_RSQ:
         this->latency = 2 * chans * math_latency;
         break;
+      case SHADER_OPCODE_INT_QUOTIENT:
       case SHADER_OPCODE_SQRT:
       case SHADER_OPCODE_LOG2:
         /* full precision log.  partial is 2. */
         this->latency = 3 * chans * math_latency;
         break;
+      case SHADER_OPCODE_INT_REMAINDER:
       case SHADER_OPCODE_EXP2:
         /* full precision.  partial is 3, same throughput. */
         this->latency = 4 * chans * math_latency;