#include "program/prog_parameter.h"
#include "program/prog_print.h"
#include "program/prog_optimize.h"
-#include "program/register_allocate.h"
+#include "util/register_allocate.h"
#include "program/sampler.h"
#include "program/hash_table.h"
#include "brw_context.h"
if (!strcmp(ir->name, "gl_FragCoord")) {
reg = emit_fragcoord_interpolation(ir);
} else if (!strcmp(ir->name, "gl_FrontFacing")) {
- reg = emit_frontfacing_interpolation(ir);
+ reg = emit_frontfacing_interpolation();
} else {
reg = emit_general_interpolation(ir);
}
this->do_dual_src = true;
} else if (ir->data.location == FRAG_RESULT_COLOR) {
/* Writing gl_FragColor outputs to all color regions. */
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
for (unsigned int i = 0; i < MAX2(key->nr_color_regions, 1); i++) {
this->outputs[i] = *reg;
this->output_components[i] = 4;
/* General color output. */
for (unsigned int i = 0; i < MAX2(1, ir->type->length); i++) {
int output = ir->data.location - FRAG_RESULT_DATA0 + i;
- this->outputs[output] = *reg;
- this->outputs[output].reg_offset += vector_elements * i;
+ this->outputs[output] = offset(*reg, vector_elements * i);
this->output_components[output] = vector_elements;
}
}
* ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
* variables, so no need for them to be in variable_ht.
*
- * Atomic counters take no uniform storage, no need to do
- * anything here.
+ * Some uniforms, such as samplers and atomic counters, have no actual
+ * storage, so we should ignore them.
*/
- if (ir->is_in_uniform_block() || ir->type->contains_atomic())
+ if (ir->is_in_uniform_block() || type_size(ir->type) == 0)
return;
if (dispatch_width == 16) {
} else if (ir->data.mode == ir_var_system_value) {
if (ir->data.location == SYSTEM_VALUE_SAMPLE_POS) {
- reg = emit_samplepos_setup(ir);
+ reg = emit_samplepos_setup();
} else if (ir->data.location == SYSTEM_VALUE_SAMPLE_ID) {
- reg = emit_sampleid_setup(ir);
+ reg = emit_sampleid_setup();
} else if (ir->data.location == SYSTEM_VALUE_SAMPLE_MASK_IN) {
assert(brw->gen >= 7);
reg = new(mem_ctx)
ir->record->accept(this);
- unsigned int offset = 0;
+ unsigned int off = 0;
for (unsigned int i = 0; i < struct_type->length; i++) {
if (strcmp(struct_type->fields.structure[i].name, ir->field) == 0)
break;
- offset += type_size(struct_type->fields.structure[i].type);
+ off += type_size(struct_type->fields.structure[i].type);
}
- this->result.reg_offset += offset;
+ this->result = offset(this->result, off);
this->result.type = brw_type_for_base_type(ir->type);
}
if (constant_index) {
assert(src.file == UNIFORM || src.file == GRF || src.file == HW_REG);
- src.reg_offset += constant_index->value.i[0] * element_size;
+ src = offset(src, constant_index->value.i[0] * element_size);
} else {
/* Variable index array dereference. We attach the variable index
* component to the reg as a pointer to a register containing the
}
}
-/* Instruction selection: Produce a MOV.sat instead of
- * MIN(MAX(val, 0), 1) when possible.
- */
bool
fs_visitor::try_emit_saturate(ir_expression *ir)
{
- ir_rvalue *sat_val = ir->as_rvalue_to_saturate();
-
- if (!sat_val)
+ if (ir->operation != ir_unop_saturate)
return false;
+ ir_rvalue *sat_val = ir->operands[0];
+
fs_inst *pre_inst = (fs_inst *) this->instructions.get_tail();
sat_val->accept(this);
fs_inst *last_inst = (fs_inst *) this->instructions.get_tail();
- /* If the last instruction from our accept() didn't generate our
- * src, generate a saturated MOV
+ /* If the last instruction from our accept() generated our
+ * src, just set the saturate flag instead of emmitting a separate mov.
*/
fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src);
- if (!modify || modify->regs_written != 1) {
- this->result = fs_reg(this, ir->type);
- fs_inst *inst = emit(MOV(this->result, src));
- inst->saturate = true;
- } else {
+ if (modify && modify->regs_written == modify->dst.width / 8 &&
+ modify->can_do_saturate()) {
modify->saturate = true;
this->result = src;
+ return true;
}
-
- return true;
+ return false;
}
bool
*/
no16("interpolate_at_* not yet supported in SIMD16 mode.");
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+
ir_dereference * deref = ir->operands[0]->as_dereference();
ir_swizzle * swiz = NULL;
if (!deref) {
/* 1. collect interpolation factors */
fs_reg dst_x = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 2, 1));
- fs_reg dst_y = dst_x;
- dst_y.reg_offset++;
+ fs_reg dst_y = offset(dst_x, 1);
/* for most messages, we need one reg of ignored data; the hardware requires mlen==1
* even when there is no payload. in the per-slot offset case, we'll replace this with
fs_inst *inst = emit(BRW_OPCODE_SEL, src2, src2, fs_reg(7));
inst->conditional_mod = BRW_CONDITIONAL_L; /* min(src2, 7) */
- src2.reg_offset++;
- this->result.reg_offset++;
+ src2 = offset(src2, 1);
+ this->result = offset(this->result, 1);
}
mlen = 2 * reg_width;
emit(FS_OPCODE_LINTERP, res,
dst_x, dst_y,
fs_reg(interp_reg(var->data.location, ch)));
- res.reg_offset++;
+ res = offset(res, 1);
}
}
if (brw->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
- struct brw_reg acc = retype(brw_acc_reg(), this->result.type);
+ struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
+ this->result.type);
emit(MUL(acc, op[0], op[1]));
emit(MACH(reg_null_d, op[0], op[1]));
}
break;
case ir_binop_imul_high: {
- if (brw->gen >= 7)
+ if (brw->gen == 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
- struct brw_reg acc = retype(brw_acc_reg(), this->result.type);
+ struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
+ this->result.type);
- emit(MUL(acc, op[0], op[1]));
+ fs_inst *mul = emit(MUL(acc, op[0], op[1]));
emit(MACH(this->result, op[0], op[1]));
+
+ /* Until Gen8, integer multiplies read 32-bits from one source, and
+ * 16-bits from the other, and relying on the MACH instruction to
+ * generate the high bits of the result.
+ *
+ * On Gen8, the multiply instruction does a full 32x32-bit multiply,
+ * but in order to do a 64x64-bit multiply we have to simulate the
+ * previous behavior and then use a MACH instruction.
+ *
+ * FINISHME: Don't use source modifiers on src1.
+ */
+ if (brw->gen >= 8) {
+ assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
+ mul->src[1].type == BRW_REGISTER_TYPE_UD);
+ if (mul->src[1].type == BRW_REGISTER_TYPE_D) {
+ mul->src[1].type = BRW_REGISTER_TYPE_W;
+ } else {
+ mul->src[1].type = BRW_REGISTER_TYPE_UW;
+ }
+ }
+
break;
}
case ir_binop_div:
emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
break;
case ir_binop_carry: {
- if (brw->gen >= 7)
+ if (brw->gen == 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
- struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD);
+ struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
+ BRW_REGISTER_TYPE_UD);
emit(ADDC(reg_null_ud, op[0], op[1]));
emit(MOV(this->result, fs_reg(acc)));
break;
}
case ir_binop_borrow: {
- if (brw->gen >= 7)
+ if (brw->gen == 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
- struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD);
+ struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
+ BRW_REGISTER_TYPE_UD);
emit(SUBB(reg_null_ud, op[0], op[1]));
emit(MOV(this->result, fs_reg(acc)));
/* The block index is a constant, so just emit the binding table entry
* as an immediate.
*/
- surf_index = fs_reg(prog_data->base.binding_table.ubo_start +
+ surf_index = fs_reg(stage_prog_data->binding_table.ubo_start +
const_uniform_block->value.u[0]);
} else {
/* The block index is not a constant. Evaluate the index expression
*/
surf_index = fs_reg(this, glsl_type::uint_type);
emit(ADD(surf_index, op[0],
- fs_reg(prog_data->base.binding_table.ubo_start)))
+ fs_reg(stage_prog_data->binding_table.ubo_start)))
->force_writemask_all = true;
/* Assume this may touch any UBO. It would be nice to provide
* a tighter bound, but the array information is already lowered away.
*/
- brw_mark_surface_used(&prog_data->base,
- prog_data->base.binding_table.ubo_start +
+ brw_mark_surface_used(prog_data,
+ stage_prog_data->binding_table.ubo_start +
shader_prog->NumUniformBlocks - 1);
}
packed_consts.type = result.type;
fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
- emit(new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
+ emit(new(mem_ctx) fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD, 8,
packed_consts, surf_index, const_offset_reg));
for (int i = 0; i < ir->type->vector_elements; i++) {
emit(MOV(result, packed_consts));
}
- result.reg_offset++;
+ result = offset(result, 1);
}
} else {
/* Turn the byte offset into a dword offset. */
if (ir->type->base_type == GLSL_TYPE_BOOL)
emit(CMP(result, result, fs_reg(0), BRW_CONDITIONAL_NZ));
- result.reg_offset++;
+ result = offset(result, 1);
}
}
inst->predicate = predicated ? BRW_PREDICATE_NORMAL : BRW_PREDICATE_NONE;
}
- l.reg_offset++;
- r.reg_offset++;
+ l = offset(l, 1);
+ r = offset(r, 1);
}
break;
case GLSL_TYPE_ARRAY:
inst = emit(MOV(l, r));
if (ir->condition)
inst->predicate = BRW_PREDICATE_NORMAL;
- r.reg_offset++;
+ r = offset(r, 1);
}
- l.reg_offset++;
+ l = offset(l, 1);
}
} else {
emit_assignment_writes(l, r, ir->lhs->type, ir->condition != NULL);
}
fs_inst *
-fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg dPdy,
+fs_visitor::emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg dPdy, int grad_components,
uint32_t sampler)
{
int mlen;
/* g0 header. */
mlen = 1;
- if (ir->shadow_comparitor) {
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ if (shadow_c.file != BAD_FILE) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present.
* the unused slots must be zeroed.
*/
- for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
+ for (int i = coord_components; i < 3; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
}
mlen += 3;
- if (ir->op == ir_tex) {
+ if (op == ir_tex) {
/* There's no plain shadow compare message, so we use shadow
* compare with a bias of 0.0.
*/
emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
mlen++;
- } else if (ir->op == ir_txb || ir->op == ir_txl) {
+ } else if (op == ir_txb || op == ir_txl) {
emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
mlen++;
} else {
emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
mlen++;
- } else if (ir->op == ir_tex) {
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ } else if (op == ir_tex) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
}
/* zero the others. */
- for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
+ for (int i = coord_components; i<3; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
mlen += 3;
- } else if (ir->op == ir_txd) {
+ } else if (op == ir_txd) {
fs_reg &dPdx = lod;
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
}
/* the slots for u and v are always present, but r is optional */
- mlen += MAX2(ir->coordinate->type->vector_elements, 2);
+ mlen += MAX2(coord_components, 2);
/* P = u, v, r
* dPdx = dudx, dvdx, drdx
* dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
* m5 m6 m7 m8 m9 m10
*/
- for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
+ for (int i = 0; i < grad_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdx));
- dPdx.reg_offset++;
+ dPdx = offset(dPdx, 1);
}
- mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2);
+ mlen += MAX2(grad_components, 2);
- for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) {
+ for (int i = 0; i < grad_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdy));
- dPdy.reg_offset++;
+ dPdy = offset(dPdy, 1);
}
- mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2);
- } else if (ir->op == ir_txs) {
+ mlen += MAX2(grad_components, 2);
+ } else if (op == ir_txs) {
/* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
simd16 = true;
emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
* instructions. We'll need to do SIMD16 here.
*/
simd16 = true;
- assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
+ assert(op == ir_txb || op == ir_txl || op == ir_txf);
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
}
/* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
* be necessary for TXF (ld), but seems wise to do for all messages.
*/
- for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
+ for (int i = coord_components; i < 3; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)));
}
* this weirdness around to the expected layout.
*/
orig_dst = dst;
- dst = fs_reg(GRF, virtual_grf_alloc(8),
- (brw->is_g4x ?
- brw_type_for_base_type(ir->type) :
- BRW_REGISTER_TYPE_F));
+ dst = fs_reg(GRF, virtual_grf_alloc(8), orig_dst.type);
}
enum opcode opcode;
-
- switch (ir->op) {
+ switch (op) {
case ir_tex: opcode = SHADER_OPCODE_TEX; break;
case ir_txb: opcode = FS_OPCODE_TXB; break;
case ir_txl: opcode = SHADER_OPCODE_TXL; break;
if (simd16) {
for (int i = 0; i < 4; i++) {
emit(MOV(orig_dst, dst));
- orig_dst.reg_offset++;
- dst.reg_offset += 2;
+ orig_dst = offset(orig_dst, 1);
+ dst = offset(dst, 2);
}
}
* surprising in the disassembly.
*/
fs_inst *
-fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg lod2,
- fs_reg sample_index, uint32_t sampler)
+fs_visitor::emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int vector_elements,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg lod2, int grad_components,
+ fs_reg sample_index, uint32_t sampler,
+ bool has_offset)
{
- int mlen = 0;
- int base_mrf = 2;
int reg_width = dispatch_width / 8;
bool header_present = false;
- const int vector_elements =
- ir->coordinate ? ir->coordinate->type->vector_elements : 0;
- if (ir->offset) {
+ fs_reg message(MRF, 2, BRW_REGISTER_TYPE_F, dispatch_width);
+ fs_reg msg_coords = message;
+
+ if (has_offset) {
/* The offsets set up by the ir_texture visitor are in the
* m1 header, so we can't go headerless.
*/
header_present = true;
- mlen++;
- base_mrf--;
+ message.reg--;
}
for (int i = 0; i < vector_elements; i++) {
- emit(MOV(fs_reg(MRF, base_mrf + mlen + i * reg_width, coordinate.type),
- coordinate));
- coordinate.reg_offset++;
+ emit(MOV(retype(offset(msg_coords, i), coordinate.type), coordinate));
+ coordinate = offset(coordinate, 1);
}
- mlen += vector_elements * reg_width;
+ fs_reg msg_end = offset(msg_coords, vector_elements);
+ fs_reg msg_lod = offset(msg_coords, 4);
- if (ir->shadow_comparitor) {
- mlen = MAX2(mlen, header_present + 4 * reg_width);
-
- emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
- mlen += reg_width;
+ if (shadow_c.file != BAD_FILE) {
+ fs_reg msg_shadow = msg_lod;
+ emit(MOV(msg_shadow, shadow_c));
+ msg_lod = offset(msg_shadow, 1);
+ msg_end = msg_lod;
}
enum opcode opcode;
- switch (ir->op) {
+ switch (op) {
case ir_tex:
opcode = SHADER_OPCODE_TEX;
break;
case ir_txb:
- mlen = MAX2(mlen, header_present + 4 * reg_width);
- emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
- mlen += reg_width;
+ emit(MOV(msg_lod, lod));
+ msg_end = offset(msg_lod, 1);
opcode = FS_OPCODE_TXB;
break;
case ir_txl:
- mlen = MAX2(mlen, header_present + 4 * reg_width);
- emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
- mlen += reg_width;
+ emit(MOV(msg_lod, lod));
+ msg_end = offset(msg_lod, 1);
opcode = SHADER_OPCODE_TXL;
break;
case ir_txd: {
- mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
-
/**
* P = u, v, r
* dPdx = dudx, dvdx, drdx
* - dudx dudy dvdx dvdy drdx drdy
* - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
*/
- for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
- emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
- lod.reg_offset++;
- mlen += reg_width;
+ msg_end = msg_lod;
+ for (int i = 0; i < grad_components; i++) {
+ emit(MOV(msg_end, lod));
+ lod = offset(lod, 1);
+ msg_end = offset(msg_end, 1);
- emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
- lod2.reg_offset++;
- mlen += reg_width;
+ emit(MOV(msg_end, lod2));
+ lod2 = offset(lod2, 1);
+ msg_end = offset(msg_end, 1);
}
opcode = SHADER_OPCODE_TXD;
break;
}
case ir_txs:
- emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
- mlen += reg_width;
+ msg_lod = retype(msg_end, BRW_REGISTER_TYPE_UD);
+ emit(MOV(msg_lod, lod));
+ msg_end = offset(msg_lod, 1);
opcode = SHADER_OPCODE_TXS;
break;
case ir_query_levels:
- emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
- mlen += reg_width;
+ msg_lod = msg_end;
+ emit(MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
+ msg_end = offset(msg_lod, 1);
opcode = SHADER_OPCODE_TXS;
break;
case ir_txf:
- mlen = header_present + 4 * reg_width;
- emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
+ msg_lod = offset(msg_coords, 3);
+ emit(MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), lod));
+ msg_end = offset(msg_lod, 1);
opcode = SHADER_OPCODE_TXF;
break;
case ir_txf_ms:
- mlen = header_present + 4 * reg_width;
-
+ msg_lod = offset(msg_coords, 3);
/* lod */
- emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0)));
+ emit(MOV(retype(msg_lod, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
/* sample index */
- emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
- mlen += reg_width;
+ emit(MOV(retype(offset(msg_lod, 1), BRW_REGISTER_TYPE_UD), sample_index));
+ msg_end = offset(msg_lod, 2);
opcode = SHADER_OPCODE_TXF_CMS;
break;
}
fs_inst *inst = emit(opcode, dst, reg_undef, fs_reg(sampler));
- inst->base_mrf = base_mrf;
- inst->mlen = mlen;
+ inst->base_mrf = message.reg;
+ inst->mlen = msg_end.reg - message.reg;
inst->header_present = header_present;
- inst->regs_written = 4;
+ inst->regs_written = 4 * reg_width;
- if (mlen > MAX_SAMPLER_MESSAGE_SIZE) {
+ if (inst->mlen > MAX_SAMPLER_MESSAGE_SIZE) {
fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE)
" disallowed by hardware\n");
}
}
fs_inst *
-fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg lod2,
- fs_reg sample_index, fs_reg mcs, fs_reg sampler)
+fs_visitor::emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg lod2, int grad_components,
+ fs_reg sample_index, fs_reg mcs, fs_reg sampler,
+ fs_reg offset_value)
{
int reg_width = dispatch_width / 8;
bool header_present = false;
}
int length = 0;
- if (ir->op == ir_tg4 || (ir->offset && ir->op != ir_txf) ||
+ if (op == ir_tg4 || offset_value.file != BAD_FILE ||
is_high_sampler(brw, sampler)) {
/* For general texture offsets (no txf workaround), we need a header to
* put them in. Note that for SIMD16 we're making space for two actual
* need to offset the Sampler State Pointer in the header.
*/
header_present = true;
- sources[length] = reg_undef;
+ sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
length++;
}
- if (ir->shadow_comparitor) {
+ if (shadow_c.file != BAD_FILE) {
emit(MOV(sources[length], shadow_c));
length++;
}
- bool has_nonconstant_offset = ir->offset && !ir->offset->as_constant();
+ bool has_nonconstant_offset =
+ offset_value.file != BAD_FILE && offset_value.file != IMM;
bool coordinate_done = false;
/* Set up the LOD info */
- switch (ir->op) {
+ switch (op) {
case ir_tex:
case ir_lod:
break;
/* Load dPdx and the coordinate together:
* [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
*/
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(sources[length], coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
length++;
/* For cube map array, the coordinate is (u,v,r,ai) but there are
* only derivatives for (u, v, r).
*/
- if (i < ir->lod_info.grad.dPdx->type->vector_elements) {
+ if (i < grad_components) {
emit(MOV(sources[length], lod));
- lod.reg_offset++;
+ lod = offset(lod, 1);
length++;
emit(MOV(sources[length], lod2));
- lod2.reg_offset++;
+ lod2 = offset(lod2, 1);
length++;
}
}
case ir_txf:
/* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
length++;
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), lod));
length++;
- for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 1; i < coord_components; i++) {
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
length++;
}
/* there is no offsetting for this message; just copy in the integer
* texture coordinates
*/
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
length++;
}
break;
case ir_tg4:
if (has_nonconstant_offset) {
- if (ir->shadow_comparitor)
+ if (shadow_c.file != BAD_FILE)
no16("Gen7 does not support gather4_po_c in SIMD16 mode.");
/* More crazy intermixing */
- ir->offset->accept(this);
- fs_reg offset_value = this->result;
-
for (int i = 0; i < 2; i++) { /* u, v */
emit(MOV(sources[length], coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
length++;
}
for (int i = 0; i < 2; i++) { /* offu, offv */
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), offset_value));
- offset_value.reg_offset++;
+ offset_value = offset(offset_value, 1);
length++;
}
- if (ir->coordinate->type->vector_elements == 3) { /* r if present */
+ if (coord_components == 3) { /* r if present */
emit(MOV(sources[length], coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
length++;
}
}
/* Set up the coordinate (except for cases where it was done above) */
- if (ir->coordinate && !coordinate_done) {
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ if (!coordinate_done) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(sources[length], coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
length++;
}
}
- fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(length),
+ int mlen;
+ if (reg_width == 2)
+ mlen = length * reg_width - header_present;
+ else
+ mlen = length * reg_width;
+
+ fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
BRW_REGISTER_TYPE_F);
emit(LOAD_PAYLOAD(src_payload, sources, length));
/* Generate the SEND */
enum opcode opcode;
- switch (ir->op) {
+ switch (op) {
case ir_tex: opcode = SHADER_OPCODE_TEX; break;
case ir_txb: opcode = FS_OPCODE_TXB; break;
case ir_txl: opcode = SHADER_OPCODE_TXL; break;
}
fs_inst *inst = emit(opcode, dst, src_payload, sampler);
inst->base_mrf = -1;
- if (reg_width == 2)
- inst->mlen = length * reg_width - header_present;
- else
- inst->mlen = length * reg_width;
+ inst->mlen = mlen;
inst->header_present = header_present;
- inst->regs_written = 4;
+ inst->regs_written = 4 * reg_width;
if (inst->mlen > MAX_SAMPLER_MESSAGE_SIZE) {
fail("Message length >" STRINGIFY(MAX_SAMPLER_MESSAGE_SIZE)
}
fs_reg
-fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
+fs_visitor::rescale_texcoord(fs_reg coordinate, const glsl_type *coord_type,
bool is_rect, uint32_t sampler, int texunit)
{
fs_inst *inst = NULL;
bool needs_gl_clamp = true;
fs_reg scale_x, scale_y;
+ const struct brw_sampler_prog_key_data *tex =
+ (stage == MESA_SHADER_FRAGMENT) ?
+ &((brw_wm_prog_key*) this->key)->tex : NULL;
+ assert(tex);
/* The 965 requires the EU to do the normalization of GL rectangle
* texture coordinates. We use the program parameter state
*/
if (is_rect &&
(brw->gen < 6 ||
- (brw->gen >= 6 && (key->tex.gl_clamp_mask[0] & (1 << sampler) ||
- key->tex.gl_clamp_mask[1] & (1 << sampler))))) {
+ (brw->gen >= 6 && (tex->gl_clamp_mask[0] & (1 << sampler) ||
+ tex->gl_clamp_mask[1] & (1 << sampler))))) {
struct gl_program_parameter_list *params = prog->Parameters;
int tokens[STATE_LENGTH] = {
STATE_INTERNAL,
* tracking to get the scaling factor.
*/
if (brw->gen < 6 && is_rect) {
- fs_reg dst = fs_reg(this, ir->coordinate->type);
+ fs_reg dst = fs_reg(this, coord_type);
fs_reg src = coordinate;
coordinate = dst;
emit(MUL(dst, src, scale_x));
- dst.reg_offset++;
- src.reg_offset++;
+ dst = offset(dst, 1);
+ src = offset(src, 1);
emit(MUL(dst, src, scale_y));
} else if (is_rect) {
/* On gen6+, the sampler handles the rectangle coordinates
needs_gl_clamp = false;
for (int i = 0; i < 2; i++) {
- if (key->tex.gl_clamp_mask[i] & (1 << sampler)) {
+ if (tex->gl_clamp_mask[i] & (1 << sampler)) {
fs_reg chan = coordinate;
- chan.reg_offset += i;
+ chan = offset(chan, i);
inst = emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f));
inst->conditional_mod = BRW_CONDITIONAL_G;
}
}
- if (ir->coordinate && needs_gl_clamp) {
- for (unsigned int i = 0;
- i < MIN2(ir->coordinate->type->vector_elements, 3); i++) {
- if (key->tex.gl_clamp_mask[i] & (1 << sampler)) {
+ if (coord_type && needs_gl_clamp) {
+ for (unsigned int i = 0; i < MIN2(coord_type->vector_elements, 3); i++) {
+ if (tex->gl_clamp_mask[i] & (1 << sampler)) {
fs_reg chan = coordinate;
- chan.reg_offset += i;
+ chan = offset(chan, i);
fs_inst *inst = emit(MOV(chan, chan));
inst->saturate = true;
/* Sample from the MCS surface attached to this multisample texture. */
fs_reg
-fs_visitor::emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler)
+fs_visitor::emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler)
{
int reg_width = dispatch_width / 8;
- int length = ir->coordinate->type->vector_elements;
- fs_reg payload = fs_reg(GRF, virtual_grf_alloc(length),
+ fs_reg payload = fs_reg(GRF, virtual_grf_alloc(components * reg_width),
BRW_REGISTER_TYPE_F);
fs_reg dest = fs_reg(this, glsl_type::uvec4_type);
- fs_reg *sources = ralloc_array(mem_ctx, fs_reg, length);
+ fs_reg *sources = ralloc_array(mem_ctx, fs_reg, components);
/* parameters are: u, v, r; missing parameters are treated as zero */
- for (int i = 0; i < length; i++) {
+ for (int i = 0; i < components; i++) {
sources[i] = fs_reg(this, glsl_type::float_type);
emit(MOV(retype(sources[i], BRW_REGISTER_TYPE_D), coordinate));
- coordinate.reg_offset++;
+ coordinate = offset(coordinate, 1);
}
- emit(LOAD_PAYLOAD(payload, sources, length));
+ emit(LOAD_PAYLOAD(payload, sources, components));
fs_inst *inst = emit(SHADER_OPCODE_TXF_MCS, dest, payload, sampler);
inst->base_mrf = -1;
- inst->mlen = length * reg_width;
+ inst->mlen = components * reg_width;
inst->header_present = false;
- inst->regs_written = 4; /* we only care about one reg of response,
- * but the sampler always writes 4/8
- */
+ inst->regs_written = 4 * reg_width; /* we only care about one reg of
+ * response, but the sampler always
+ * writes 4/8
+ */
return dest;
}
void
-fs_visitor::visit(ir_texture *ir)
+fs_visitor::emit_texture(ir_texture_opcode op,
+ const glsl_type *dest_type,
+ fs_reg coordinate, const struct glsl_type *coord_type,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg lod2, int grad_components,
+ fs_reg sample_index,
+ fs_reg offset_value, unsigned offset_components,
+ fs_reg mcs,
+ int gather_component,
+ bool is_cube_array,
+ bool is_rect,
+ uint32_t sampler,
+ fs_reg sampler_reg, int texunit)
{
+ const struct brw_sampler_prog_key_data *tex =
+ (stage == MESA_SHADER_FRAGMENT) ?
+ &((brw_wm_prog_key*) this->key)->tex : NULL;
+ assert(tex);
fs_inst *inst = NULL;
+ if (op == ir_tg4) {
+ /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
+ * emitting anything other than setting up the constant result.
+ */
+ int swiz = GET_SWZ(tex->swizzles[sampler], gather_component);
+ if (swiz == SWIZZLE_ZERO || swiz == SWIZZLE_ONE) {
+
+ fs_reg res = fs_reg(this, glsl_type::vec4_type);
+ this->result = res;
+
+ for (int i=0; i<4; i++) {
+ emit(MOV(res, fs_reg(swiz == SWIZZLE_ZERO ? 0.0f : 1.0f)));
+ res = offset(res, 1);
+ }
+ return;
+ }
+ }
+
+ if (coordinate.file != BAD_FILE) {
+ /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
+ * samplers. This should only be a problem with GL_CLAMP on Gen7.
+ */
+ coordinate = rescale_texcoord(coordinate, coord_type, is_rect,
+ sampler, texunit);
+ }
+
+ /* Writemasking doesn't eliminate channels on SIMD8 texture
+ * samples, so don't worry about them.
+ */
+ fs_reg dst(this, glsl_type::get_instance(dest_type->base_type, 4, 1));
+
+ int coord_components = coord_type ? coord_type->vector_elements : 0;
+
+ if (brw->gen >= 7) {
+ inst = emit_texture_gen7(op, dst, coordinate, coord_components,
+ shadow_c, lod, lod2, grad_components,
+ sample_index, mcs, sampler_reg,
+ offset_value);
+ } else if (brw->gen >= 5) {
+ inst = emit_texture_gen5(op, dst, coordinate, coord_components,
+ shadow_c, lod, lod2, grad_components,
+ sample_index, sampler,
+ offset_value.file != BAD_FILE);
+ } else {
+ inst = emit_texture_gen4(op, dst, coordinate, coord_components,
+ shadow_c, lod, lod2, grad_components,
+ sampler);
+ }
+
+ if (shadow_c.file != BAD_FILE)
+ inst->shadow_compare = true;
+
+ if (offset_value.file == IMM)
+ inst->texture_offset = offset_value.fixed_hw_reg.dw1.ud;
+
+ if (op == ir_tg4) {
+ inst->texture_offset |=
+ gather_channel(gather_component, sampler) << 16; /* M0.2:16-17 */
+
+ if (brw->gen == 6)
+ emit_gen6_gather_wa(tex->gen6_gather_wa[sampler], dst);
+ }
+
+ /* fixup #layers for cube map arrays */
+ if (op == ir_txs && is_cube_array) {
+ fs_reg depth = offset(dst, 2);
+ fs_reg fixed_depth = fs_reg(this, glsl_type::int_type);
+ emit_math(SHADER_OPCODE_INT_QUOTIENT, fixed_depth, depth, fs_reg(6));
+
+ fs_reg *fixed_payload = ralloc_array(mem_ctx, fs_reg, inst->regs_written);
+ int components = inst->regs_written / (dst.width / 8);
+ for (int i = 0; i < components; i++) {
+ if (i == 2) {
+ fixed_payload[i] = fixed_depth;
+ } else {
+ fixed_payload[i] = offset(dst, i);
+ }
+ }
+ emit(LOAD_PAYLOAD(dst, fixed_payload, components));
+ }
+
+ swizzle_result(op, dest_type->vector_elements, dst, sampler);
+}
+
+void
+fs_visitor::visit(ir_texture *ir)
+{
+ const struct brw_sampler_prog_key_data *tex =
+ (stage == MESA_SHADER_FRAGMENT) ?
+ &((brw_wm_prog_key*) this->key)->tex : NULL;
+ assert(tex);
+
uint32_t sampler =
_mesa_get_sampler_uniform_value(ir->sampler, shader_prog, prog);
uint32_t max_used = sampler + array_size - 1;
if (ir->op == ir_tg4 && brw->gen < 8) {
- max_used += prog_data->base.binding_table.gather_texture_start;
+ max_used += stage_prog_data->binding_table.gather_texture_start;
} else {
- max_used += prog_data->base.binding_table.texture_start;
+ max_used += stage_prog_data->binding_table.texture_start;
}
- brw_mark_surface_used(&prog_data->base, max_used);
+ brw_mark_surface_used(prog_data, max_used);
/* Emit code to evaluate the actual indexing expression */
nonconst_sampler_index->accept(this);
*/
int texunit = prog->SamplerUnits[sampler];
- if (ir->op == ir_tg4) {
- /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
- * emitting anything other than setting up the constant result.
- */
- ir_constant *chan = ir->lod_info.component->as_constant();
- int swiz = GET_SWZ(key->tex.swizzles[sampler], chan->value.i[0]);
- if (swiz == SWIZZLE_ZERO || swiz == SWIZZLE_ONE) {
-
- fs_reg res = fs_reg(this, glsl_type::vec4_type);
- this->result = res;
-
- for (int i=0; i<4; i++) {
- emit(MOV(res, fs_reg(swiz == SWIZZLE_ZERO ? 0.0f : 1.0f)));
- res.reg_offset++;
- }
- return;
- }
- }
-
/* Should be lowered by do_lower_texture_projection */
assert(!ir->projector);
* generating these values may involve SEND messages that need the MRFs.
*/
fs_reg coordinate;
+ const glsl_type *coord_type = NULL;
if (ir->coordinate) {
+ coord_type = ir->coordinate->type;
ir->coordinate->accept(this);
-
- coordinate = rescale_texcoord(ir, this->result,
- ir->sampler->type->sampler_dimensionality ==
- GLSL_SAMPLER_DIM_RECT,
- sampler, texunit);
+ coordinate = this->result;
}
fs_reg shadow_comparitor;
shadow_comparitor = this->result;
}
+ fs_reg offset_value;
+ int offset_components = 0;
+ if (ir->offset) {
+ ir_constant *const_offset = ir->offset->as_constant();
+ if (const_offset) {
+ /* Store the header bitfield in an IMM register. This allows us to
+ * use offset_value.file to distinguish between no offset, a constant
+ * offset, and a non-constant offset.
+ */
+ offset_value =
+ fs_reg(brw_texture_offset(ctx, const_offset->value.i,
+ const_offset->type->vector_elements));
+ } else {
+ ir->offset->accept(this);
+ offset_value = this->result;
+ }
+ offset_components = ir->offset->type->vector_elements;
+ }
+
fs_reg lod, lod2, sample_index, mcs;
+ int grad_components = 0;
switch (ir->op) {
case ir_tex:
case ir_lod:
ir->lod_info.grad.dPdy->accept(this);
lod2 = this->result;
+
+ grad_components = ir->lod_info.grad.dPdx->type->vector_elements;
break;
case ir_txf:
case ir_txl:
ir->lod_info.sample_index->accept(this);
sample_index = this->result;
- if (brw->gen >= 7 && key->tex.compressed_multisample_layout_mask & (1<<sampler))
- mcs = emit_mcs_fetch(ir, coordinate, sampler_reg);
+ if (brw->gen >= 7 && tex->compressed_multisample_layout_mask & (1<<sampler))
+ mcs = emit_mcs_fetch(coordinate, ir->coordinate->type->vector_elements,
+ sampler_reg);
else
mcs = fs_reg(0u);
break;
unreachable("Unrecognized texture opcode");
};
- /* Writemasking doesn't eliminate channels on SIMD8 texture
- * samples, so don't worry about them.
- */
- fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
-
- if (brw->gen >= 7) {
- inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
- lod, lod2, sample_index, mcs, sampler_reg);
- } else if (brw->gen >= 5) {
- inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
- lod, lod2, sample_index, sampler);
- } else {
- inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
- lod, lod2, sampler);
- }
-
- if (ir->offset != NULL && ir->op != ir_txf)
- inst->texture_offset = brw_texture_offset(ctx, ir->offset->as_constant());
-
+ int gather_component = 0;
if (ir->op == ir_tg4)
- inst->texture_offset |= gather_channel(ir, sampler) << 16; // M0.2:16-17
+ gather_component = ir->lod_info.component->as_constant()->value.i[0];
- if (ir->shadow_comparitor)
- inst->shadow_compare = true;
+ bool is_rect =
+ ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT;
- /* fixup #layers for cube map arrays */
- if (ir->op == ir_txs) {
- glsl_type const *type = ir->sampler->type;
- if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
- type->sampler_array) {
- fs_reg depth = dst;
- depth.reg_offset = 2;
- fs_reg fixed_depth = fs_reg(this, glsl_type::int_type);
- emit_math(SHADER_OPCODE_INT_QUOTIENT, fixed_depth, depth, fs_reg(6));
-
- fs_reg *fixed_payload = ralloc_array(mem_ctx, fs_reg, inst->regs_written);
- fs_reg d = dst;
- for (int i = 0; i < inst->regs_written; i++) {
- if (i == 2) {
- fixed_payload[i] = fixed_depth;
- } else {
- d.reg_offset = i;
- fixed_payload[i] = d;
- }
- }
- emit(LOAD_PAYLOAD(dst, fixed_payload, inst->regs_written));
- }
- }
-
- if (brw->gen == 6 && ir->op == ir_tg4) {
- emit_gen6_gather_wa(key->tex.gen6_gather_wa[sampler], dst);
- }
+ bool is_cube_array =
+ ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
+ ir->sampler->type->sampler_array;
- swizzle_result(ir, dst, sampler);
+ emit_texture(ir->op, ir->type, coordinate, coord_type, shadow_comparitor,
+ lod, lod2, grad_components, sample_index, offset_value,
+ offset_components, mcs, gather_component,
+ is_cube_array, is_rect, sampler, sampler_reg, texunit);
}
/**
emit(ASR(dst, dst, fs_reg(32 - width)));
}
- dst.reg_offset++;
+ dst = offset(dst, 1);
}
}
* Set up the gather channel based on the swizzle, for gather4.
*/
uint32_t
-fs_visitor::gather_channel(ir_texture *ir, uint32_t sampler)
+fs_visitor::gather_channel(int orig_chan, uint32_t sampler)
{
- ir_constant *chan = ir->lod_info.component->as_constant();
- int swiz = GET_SWZ(key->tex.swizzles[sampler], chan->value.i[0]);
+ const struct brw_sampler_prog_key_data *tex =
+ (stage == MESA_SHADER_FRAGMENT) ?
+ &((brw_wm_prog_key*) this->key)->tex : NULL;
+ assert(tex);
+ int swiz = GET_SWZ(tex->swizzles[sampler], orig_chan);
switch (swiz) {
case SWIZZLE_X: return 0;
case SWIZZLE_Y:
/* gather4 sampler is broken for green channel on RG32F --
* we must ask for blue instead.
*/
- if (key->tex.gather_channel_quirk_mask & (1<<sampler))
+ if (tex->gather_channel_quirk_mask & (1<<sampler))
return 2;
return 1;
case SWIZZLE_Z: return 2;
* EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
*/
void
-fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler)
+fs_visitor::swizzle_result(ir_texture_opcode op, int dest_components,
+ fs_reg orig_val, uint32_t sampler)
{
- if (ir->op == ir_query_levels) {
+ if (op == ir_query_levels) {
/* # levels is in .w */
- orig_val.reg_offset += 3;
- this->result = orig_val;
+ this->result = offset(orig_val, 3);
return;
}
/* txs,lod don't actually sample the texture, so swizzling the result
* makes no sense.
*/
- if (ir->op == ir_txs || ir->op == ir_lod || ir->op == ir_tg4)
+ if (op == ir_txs || op == ir_lod || op == ir_tg4)
return;
- if (ir->type == glsl_type::float_type) {
+ const struct brw_sampler_prog_key_data *tex =
+ (stage == MESA_SHADER_FRAGMENT) ?
+ &((brw_wm_prog_key*) this->key)->tex : NULL;
+ assert(tex);
+
+ if (dest_components == 1) {
/* Ignore DEPTH_TEXTURE_MODE swizzling. */
- assert(ir->sampler->type->sampler_shadow);
- } else if (key->tex.swizzles[sampler] != SWIZZLE_NOOP) {
+ } else if (tex->swizzles[sampler] != SWIZZLE_NOOP) {
fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
+ swizzled_result.type = orig_val.type;
for (int i = 0; i < 4; i++) {
- int swiz = GET_SWZ(key->tex.swizzles[sampler], i);
+ int swiz = GET_SWZ(tex->swizzles[sampler], i);
fs_reg l = swizzled_result;
- l.reg_offset += i;
+ l = offset(l, i);
if (swiz == SWIZZLE_ZERO) {
emit(MOV(l, fs_reg(0.0f)));
} else if (swiz == SWIZZLE_ONE) {
emit(MOV(l, fs_reg(1.0f)));
} else {
- fs_reg r = orig_val;
- r.reg_offset += GET_SWZ(key->tex.swizzles[sampler], i);
- emit(MOV(l, r));
+ emit(MOV(l, offset(orig_val,
+ GET_SWZ(tex->swizzles[sampler], i))));
}
}
this->result = swizzled_result;
fs_reg val = this->result;
if (ir->type->vector_elements == 1) {
- this->result.reg_offset += ir->mask.x;
+ this->result = offset(this->result, ir->mask.x);
return;
}
break;
}
- channel.reg_offset += swiz;
- emit(MOV(result, channel));
- result.reg_offset++;
+ emit(MOV(result, offset(channel, swiz)));
+ result = offset(result, 1);
}
}
dst_reg.type = src_reg.type;
for (unsigned j = 0; j < size; j++) {
emit(MOV(dst_reg, src_reg));
- src_reg.reg_offset++;
- dst_reg.reg_offset++;
+ src_reg = offset(src_reg, 1);
+ dst_reg = offset(dst_reg, 1);
}
}
} else if (ir->type->is_record()) {
dst_reg.type = src_reg.type;
for (unsigned j = 0; j < size; j++) {
emit(MOV(dst_reg, src_reg));
- src_reg.reg_offset++;
- dst_reg.reg_offset++;
+ src_reg = offset(src_reg, 1);
+ dst_reg = offset(dst_reg, 1);
}
}
} else {
default:
unreachable("Non-float/uint/int/bool constant");
}
- dst_reg.reg_offset++;
+ dst_reg = offset(dst_reg, 1);
}
}
{
ir_expression *expr = ir->as_expression();
- if (!expr) {
+ if (!expr || expr->operation == ir_binop_ubo_load) {
ir->accept(this);
fs_inst *inst = emit(AND(reg_null_d, this->result, fs_reg(1)));
return;
}
- fs_reg op[2];
+ fs_reg op[3];
fs_inst *inst;
- assert(expr->get_num_operands() <= 2);
+ assert(expr->get_num_operands() <= 3);
for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
assert(expr->operands[i]->type->is_scalar());
brw_conditional_for_comparison(expr->operation)));
break;
+ case ir_triop_csel: {
+ /* Expand the boolean condition into the flag register. */
+ inst = emit(MOV(reg_null_d, op[0]));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+
+ /* Select which boolean to return. */
+ fs_reg temp(this, expr->operands[1]->type);
+ inst = emit(SEL(temp, op[1], op[2]));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+
+ /* Expand the result to a condition code. */
+ inst = emit(MOV(reg_null_d, temp));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ break;
+ }
+
default:
unreachable("not reached");
}
{
ir_expression *expr = ir->condition->as_expression();
- if (expr) {
- fs_reg op[2];
+ if (expr && expr->operation != ir_binop_ubo_load) {
+ fs_reg op[3];
fs_inst *inst;
fs_reg temp;
- assert(expr->get_num_operands() <= 2);
+ assert(expr->get_num_operands() <= 3);
for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
assert(expr->operands[i]->type->is_scalar());
switch (expr->operation) {
case ir_unop_logic_not:
+ emit(IF(op[0], fs_reg(0), BRW_CONDITIONAL_Z));
+ return;
+
case ir_binop_logic_xor:
+ emit(IF(op[0], op[1], BRW_CONDITIONAL_NZ));
+ return;
+
case ir_binop_logic_or:
+ temp = fs_reg(this, glsl_type::bool_type);
+ emit(OR(temp, op[0], op[1]));
+ emit(IF(temp, fs_reg(0), BRW_CONDITIONAL_NZ));
+ return;
+
case ir_binop_logic_and:
- /* For operations on bool arguments, only the low bit of the bool is
- * valid, and the others are undefined. Fall back to the condition
- * code path.
- */
- break;
+ temp = fs_reg(this, glsl_type::bool_type);
+ emit(AND(temp, op[0], op[1]));
+ emit(IF(temp, fs_reg(0), BRW_CONDITIONAL_NZ));
+ return;
case ir_unop_f2b:
inst = emit(BRW_OPCODE_IF, reg_null_f, op[0], fs_reg(0));
emit(IF(op[0], op[1],
brw_conditional_for_comparison(expr->operation)));
return;
+
+ case ir_triop_csel: {
+ /* Expand the boolean condition into the flag register. */
+ fs_inst *inst = emit(MOV(reg_null_d, op[0]));
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
+
+ /* Select which boolean to use as the result. */
+ fs_reg temp(this, expr->operands[1]->type);
+ inst = emit(SEL(temp, op[1], op[2]));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+
+ emit(IF(temp, fs_reg(0), BRW_CONDITIONAL_NZ));
+ return;
+ }
+
default:
unreachable("not reached");
}
}
- emit_bool_to_cond_code(ir->condition);
- fs_inst *inst = emit(BRW_OPCODE_IF);
- inst->predicate = BRW_PREDICATE_NORMAL;
+ ir->condition->accept(this);
+ emit(IF(this->result, fs_reg(0), BRW_CONDITIONAL_NZ));
}
/**
/* Remove the matched instructions; we'll emit a SEL to replace them. */
while (!if_inst->next->is_tail_sentinel())
- if_inst->next->remove();
- if_inst->remove();
+ if_inst->next->exec_node::remove();
+ if_inst->exec_node::remove();
/* Only the last source register can be a constant, so if the MOV in
* the "then" clause uses a constant, we need to put it in a temporary.
ir_dereference *deref = static_cast<ir_dereference *>(
ir->actual_parameters.get_head());
ir_variable *location = deref->variable_referenced();
- unsigned surf_index = (prog_data->base.binding_table.abo_start +
+ unsigned surf_index = (stage_prog_data->binding_table.abo_start +
location->data.binding);
/* Calculate the surface offset */
deref_array->array_index->accept(this);
fs_reg tmp(this, glsl_type::uint_type);
- emit(MUL(tmp, this->result, ATOMIC_COUNTER_SIZE));
- emit(ADD(offset, tmp, location->data.atomic.offset));
+ emit(MUL(tmp, this->result, fs_reg(ATOMIC_COUNTER_SIZE)));
+ emit(ADD(offset, tmp, fs_reg(location->data.atomic.offset)));
} else {
- offset = location->data.atomic.offset;
+ offset = fs_reg(location->data.atomic.offset);
}
/* Emit the appropriate machine instruction */
fs_reg dst, fs_reg offset, fs_reg src0,
fs_reg src1)
{
- const unsigned operand_len = dispatch_width / 8;
- unsigned mlen = 0;
+ bool uses_kill =
+ (stage == MESA_SHADER_FRAGMENT) &&
+ ((brw_wm_prog_data*) this->prog_data)->uses_kill;
+ int reg_width = dispatch_width / 8;
+ int length = 0;
+ fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 4);
+
+ sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
/* Initialize the sample mask in the message header. */
- emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
+ emit(MOV(sources[0], fs_reg(0u)))
->force_writemask_all = true;
- if (fp->UsesKill) {
- emit(MOV(brw_uvec_mrf(1, mlen, 7), brw_flag_reg(0, 1)))
+ if (uses_kill) {
+ emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
->force_writemask_all = true;
} else {
- emit(MOV(brw_uvec_mrf(1, mlen, 7),
+ emit(MOV(component(sources[0], 7),
retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
->force_writemask_all = true;
}
-
- mlen++;
+ length++;
/* Set the atomic operation offset. */
- emit(MOV(brw_uvec_mrf(dispatch_width, mlen, 0), offset));
- mlen += operand_len;
+ sources[1] = fs_reg(this, glsl_type::uint_type);
+ emit(MOV(sources[1], offset));
+ length++;
/* Set the atomic operation arguments. */
if (src0.file != BAD_FILE) {
- emit(MOV(brw_uvec_mrf(dispatch_width, mlen, 0), src0));
- mlen += operand_len;
+ sources[length] = fs_reg(this, glsl_type::uint_type);
+ emit(MOV(sources[length], src0));
+ length++;
}
if (src1.file != BAD_FILE) {
- emit(MOV(brw_uvec_mrf(dispatch_width, mlen, 0), src1));
- mlen += operand_len;
+ sources[length] = fs_reg(this, glsl_type::uint_type);
+ emit(MOV(sources[length], src1));
+ length++;
}
+ int mlen = 1 + (length - 1) * reg_width;
+ fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
+ BRW_REGISTER_TYPE_UD);
+ emit(LOAD_PAYLOAD(src_payload, sources, length));
+
/* Emit the instruction. */
- fs_inst *inst = new(mem_ctx) fs_inst(SHADER_OPCODE_UNTYPED_ATOMIC, dst,
- atomic_op, surf_index);
- inst->base_mrf = 0;
+ fs_inst *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst, src_payload,
+ fs_reg(atomic_op), fs_reg(surf_index));
inst->mlen = mlen;
- inst->header_present = true;
- emit(inst);
}
void
fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
fs_reg offset)
{
- const unsigned operand_len = dispatch_width / 8;
- unsigned mlen = 0;
+ bool uses_kill =
+ (stage == MESA_SHADER_FRAGMENT) &&
+ ((brw_wm_prog_data*) this->prog_data)->uses_kill;
+ int reg_width = dispatch_width / 8;
+ fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
+
+ sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
/* Initialize the sample mask in the message header. */
- emit(MOV(brw_uvec_mrf(8, mlen, 0), fs_reg(0u)))
+ emit(MOV(sources[0], fs_reg(0u)))
->force_writemask_all = true;
- if (fp->UsesKill) {
- emit(MOV(brw_uvec_mrf(1, mlen, 7), brw_flag_reg(0, 1)))
+ if (uses_kill) {
+ emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
->force_writemask_all = true;
} else {
- emit(MOV(brw_uvec_mrf(1, mlen, 7),
+ emit(MOV(component(sources[0], 7),
retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
->force_writemask_all = true;
}
- mlen++;
-
/* Set the surface read offset. */
- emit(MOV(brw_uvec_mrf(dispatch_width, mlen, 0), offset));
- mlen += operand_len;
+ sources[1] = fs_reg(this, glsl_type::uint_type);
+ emit(MOV(sources[1], offset));
+
+ int mlen = 1 + reg_width;
+ fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
+ BRW_REGISTER_TYPE_UD);
+ fs_inst *inst = emit(LOAD_PAYLOAD(src_payload, sources, 2));
/* Emit the instruction. */
- fs_inst *inst = new(mem_ctx)
- fs_inst(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst, surf_index);
- inst->base_mrf = 0;
+ inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst, src_payload,
+ fs_reg(surf_index));
inst->mlen = mlen;
- inst->header_present = true;
- emit(inst);
}
fs_inst *
fs_visitor::emit(fs_inst *inst)
{
if (force_uncompressed_stack > 0)
+ inst->exec_size = 8;
+
+ if (dispatch_width == 16 && inst->exec_size == 8)
inst->force_uncompressed = true;
inst->annotation = this->current_annotation;
fs_visitor::emit(exec_list list)
{
foreach_in_list_safe(fs_inst, inst, &list) {
- inst->remove();
+ inst->exec_node::remove();
emit(inst);
}
}
struct brw_reg
fs_visitor::interp_reg(int location, int channel)
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
int regnr = prog_data->urb_setup[location] * 2 + channel / 2;
int stride = (channel & 1) * 4;
this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
fs_reg(this, glsl_type::vec2_type);
this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
- this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC].reg_offset++;
+ offset(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1);
} else {
this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
fs_reg(this, glsl_type::float_type);
this->current_annotation = NULL;
}
-void
-fs_visitor::emit_color_write(int target, int index, int first_color_mrf)
+int
+fs_visitor::setup_color_payload(fs_reg *dst, fs_reg color, unsigned components)
{
- int reg_width = dispatch_width / 8;
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
fs_inst *inst;
- fs_reg color = outputs[target];
- fs_reg mrf;
- /* If there's no color data to be written, skip it. */
- if (color.file == BAD_FILE)
- return;
+ if (color.file == BAD_FILE) {
+ return 4 * (dispatch_width / 8);
+ }
- color.reg_offset += index;
+ uint8_t colors_enabled;
+ if (components == 0) {
+ /* We want to write one component to the alpha channel */
+ colors_enabled = 0x8;
+ } else {
+ /* Enable the first components-many channels */
+ colors_enabled = (1 << components) - 1;
+ }
if (dispatch_width == 8 || brw->gen >= 6) {
/* SIMD8 write looks like:
* m + 6: a0
* m + 7: a1
*/
- inst = emit(MOV(fs_reg(MRF, first_color_mrf + index * reg_width,
- color.type),
- color));
- inst->saturate = key->clamp_fragment_color;
+ int len = 0;
+ for (unsigned i = 0; i < 4; ++i) {
+ if (colors_enabled & (1 << i)) {
+ dst[len] = fs_reg(GRF, virtual_grf_alloc(color.width / 8),
+ color.type, color.width);
+ inst = emit(MOV(dst[len], offset(color, i)));
+ inst->saturate = key->clamp_fragment_color;
+ } else if (color.width == 16) {
+ /* We need two BAD_FILE slots for a 16-wide color */
+ len++;
+ }
+ len++;
+ }
+ return len;
} else {
/* pre-gen6 SIMD16 single source DP write looks like:
* m + 0: r0
* m + 6: b1
* m + 7: a1
*/
- if (brw->has_compr4) {
- /* By setting the high bit of the MRF register number, we
- * indicate that we want COMPR4 mode - instead of doing the
- * usual destination + 1 for the second half we get
- * destination + 4.
- */
- inst = emit(MOV(fs_reg(MRF, BRW_MRF_COMPR4 + first_color_mrf + index,
- color.type),
- color));
- inst->saturate = key->clamp_fragment_color;
- } else {
- push_force_uncompressed();
- inst = emit(MOV(fs_reg(MRF, first_color_mrf + index, color.type),
- color));
- inst->saturate = key->clamp_fragment_color;
- pop_force_uncompressed();
-
- inst = emit(MOV(fs_reg(MRF, first_color_mrf + index + 4, color.type),
- half(color, 1)));
- inst->force_sechalf = true;
- inst->saturate = key->clamp_fragment_color;
+ for (unsigned i = 0; i < 4; ++i) {
+ if (colors_enabled & (1 << i)) {
+ dst[i] = fs_reg(GRF, virtual_grf_alloc(1), color.type);
+ inst = emit(MOV(dst[i], half(offset(color, i), 0)));
+ inst->saturate = key->clamp_fragment_color;
+
+ dst[i + 4] = fs_reg(GRF, virtual_grf_alloc(1), color.type);
+ inst = emit(MOV(dst[i + 4], half(offset(color, i), 1)));
+ inst->saturate = key->clamp_fragment_color;
+ inst->force_sechalf = true;
+ }
}
+ return 8;
}
}
void
fs_visitor::emit_alpha_test()
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
this->current_annotation = "Alpha test";
fs_inst *cmp;
BRW_CONDITIONAL_NEQ));
} else {
/* RT0 alpha */
- fs_reg color = outputs[0];
- color.reg_offset += 3;
+ fs_reg color = offset(outputs[0], 3);
/* f0.1 &= func(color, ref) */
cmp = emit(CMP(reg_null_f, color, fs_reg(key->alpha_test_ref),
cmp->flag_subreg = 1;
}
-void
-fs_visitor::emit_fb_writes()
+fs_inst *
+fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1,
+ fs_reg src0_alpha, unsigned components)
{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+
this->current_annotation = "FB write header";
bool header_present = true;
+ int reg_size = dispatch_width / 8;
+
/* We can potentially have a message length of up to 15, so we have to set
* base_mrf to either 0 or 1 in order to fit in m0..m15.
*/
- int base_mrf = 1;
- int nr = base_mrf;
- int reg_width = dispatch_width / 8;
- bool src0_alpha_to_render_target = false;
-
- if (do_dual_src) {
- no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
- if (dispatch_width == 16)
- do_dual_src = false;
- }
+ fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 15);
+ int length = 0;
/* From the Sandy Bridge PRM, volume 4, page 198:
*
* thread message and on all dual-source messages."
*/
if (brw->gen >= 6 &&
- (brw->is_haswell || brw->gen >= 8 || !this->fp->UsesKill) &&
- !do_dual_src &&
+ (brw->is_haswell || brw->gen >= 8 || !prog_data->uses_kill) &&
+ color1.file == BAD_FILE &&
key->nr_color_regions == 1) {
header_present = false;
}
- if (header_present) {
- src0_alpha_to_render_target = brw->gen >= 6 &&
- !do_dual_src &&
- key->replicate_alpha;
- /* m2, m3 header */
- nr += 2;
- }
+ if (header_present)
+ /* Allocate 2 registers for a header */
+ length += 2;
if (payload.aa_dest_stencil_reg) {
- push_force_uncompressed();
- emit(MOV(fs_reg(MRF, nr++),
+ sources[length] = fs_reg(GRF, virtual_grf_alloc(1));
+ emit(MOV(sources[length],
fs_reg(brw_vec8_grf(payload.aa_dest_stencil_reg, 0))));
- pop_force_uncompressed();
+ length++;
}
prog_data->uses_omask =
- fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
+ prog->OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_SAMPLE_MASK);
if (prog_data->uses_omask) {
this->current_annotation = "FB write oMask";
assert(this->sample_mask.file != BAD_FILE);
- /* Hand over gl_SampleMask. Only lower 16 bits are relevant. */
- emit(FS_OPCODE_SET_OMASK, fs_reg(MRF, nr, BRW_REGISTER_TYPE_UW), this->sample_mask);
- nr += 1;
+ /* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
+ * it's unsinged single words, one vgrf is always 16-wide.
+ */
+ sources[length] = fs_reg(GRF, virtual_grf_alloc(1),
+ BRW_REGISTER_TYPE_UW, 16);
+ emit(FS_OPCODE_SET_OMASK, sources[length], this->sample_mask);
+ length++;
}
- /* Reserve space for color. It'll be filled in per MRT below. */
- int color_mrf = nr;
- nr += 4 * reg_width;
- if (do_dual_src)
- nr += 4;
- if (src0_alpha_to_render_target)
- nr += reg_width;
+ if (color0.file == BAD_FILE) {
+ /* Even if there's no color buffers enabled, we still need to send
+ * alpha out the pipeline to our null renderbuffer to support
+ * alpha-testing, alpha-to-coverage, and so on.
+ */
+ length += setup_color_payload(sources + length, this->outputs[0], 0);
+ } else if (color1.file == BAD_FILE) {
+ if (src0_alpha.file != BAD_FILE) {
+ sources[length] = fs_reg(GRF, virtual_grf_alloc(reg_size),
+ src0_alpha.type, src0_alpha.width);
+ fs_inst *inst = emit(MOV(sources[length], src0_alpha));
+ inst->saturate = key->clamp_fragment_color;
+ length++;
+ }
+
+ length += setup_color_payload(sources + length, color0, components);
+ } else {
+ length += setup_color_payload(sources + length, color0, components);
+ length += setup_color_payload(sources + length, color1, components);
+ }
if (source_depth_to_render_target) {
if (brw->gen == 6) {
no16("Missing support for simd16 depth writes on gen6\n");
}
+ sources[length] = fs_reg(this, glsl_type::float_type);
if (prog->OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
/* Hand over gl_FragDepth. */
assert(this->frag_depth.file != BAD_FILE);
- emit(MOV(fs_reg(MRF, nr), this->frag_depth));
+ emit(MOV(sources[length], this->frag_depth));
} else {
/* Pass through the payload depth. */
- emit(MOV(fs_reg(MRF, nr),
+ emit(MOV(sources[length],
fs_reg(brw_vec8_grf(payload.source_depth_reg, 0))));
}
- nr += reg_width;
+ length++;
}
if (payload.dest_depth_reg) {
- emit(MOV(fs_reg(MRF, nr),
+ sources[length] = fs_reg(this, glsl_type::float_type);
+ emit(MOV(sources[length],
fs_reg(brw_vec8_grf(payload.dest_depth_reg, 0))));
- nr += reg_width;
+ length++;
}
- if (do_dual_src) {
- fs_reg src0 = this->outputs[0];
- fs_reg src1 = this->dual_src_output;
+ fs_inst *load;
+ fs_inst *write;
+ if (brw->gen >= 7) {
+ /* Send from the GRF */
+ fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F);
+ load = emit(LOAD_PAYLOAD(payload, sources, length));
+ payload.reg = virtual_grf_alloc(load->regs_written);
+ load->dst = payload;
+ write = emit(FS_OPCODE_FB_WRITE, reg_undef, payload);
+ write->base_mrf = -1;
+ } else {
+ /* Send from the MRF */
+ load = emit(LOAD_PAYLOAD(fs_reg(MRF, 1, BRW_REGISTER_TYPE_F),
+ sources, length));
+ write = emit(FS_OPCODE_FB_WRITE);
+ write->base_mrf = 1;
+ }
- this->current_annotation = ralloc_asprintf(this->mem_ctx,
- "FB write src0");
- for (int i = 0; i < 4; i++) {
- fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + i, src0.type), src0));
- src0.reg_offset++;
- inst->saturate = key->clamp_fragment_color;
- }
+ write->mlen = load->regs_written;
+ write->header_present = header_present;
+ if ((brw->gen >= 8 || brw->is_haswell) && prog_data->uses_kill) {
+ write->predicate = BRW_PREDICATE_NORMAL;
+ write->flag_subreg = 1;
+ }
+ return write;
+}
- this->current_annotation = ralloc_asprintf(this->mem_ctx,
- "FB write src1");
- for (int i = 0; i < 4; i++) {
- fs_inst *inst = emit(MOV(fs_reg(MRF, color_mrf + 4 + i, src1.type),
- src1));
- src1.reg_offset++;
- inst->saturate = key->clamp_fragment_color;
- }
+void
+fs_visitor::emit_fb_writes()
+{
+ assert(stage == MESA_SHADER_FRAGMENT);
+ brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
+ brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+
+ if (do_dual_src) {
+ no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
+ if (dispatch_width == 16)
+ do_dual_src = false;
+ }
+ fs_inst *inst;
+ if (do_dual_src) {
if (INTEL_DEBUG & DEBUG_SHADER_TIME)
emit_shader_time_end();
- fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
+ this->current_annotation = ralloc_asprintf(this->mem_ctx,
+ "FB dual-source write");
+ inst = emit_single_fb_write(this->outputs[0], this->dual_src_output,
+ reg_undef, 4);
inst->target = 0;
- inst->base_mrf = base_mrf;
- inst->mlen = nr - base_mrf;
- inst->eot = true;
- inst->header_present = header_present;
- if ((brw->gen >= 8 || brw->is_haswell) && fp->UsesKill) {
- inst->predicate = BRW_PREDICATE_NORMAL;
- inst->flag_subreg = 1;
- }
-
prog_data->dual_src_blend = true;
- this->current_annotation = NULL;
- return;
- }
-
- for (int target = 0; target < key->nr_color_regions; target++) {
- this->current_annotation = ralloc_asprintf(this->mem_ctx,
- "FB write target %d",
- target);
- /* If src0_alpha_to_render_target is true, include source zero alpha
- * data in RenderTargetWrite message for targets > 0.
- */
- int write_color_mrf = color_mrf;
- if (src0_alpha_to_render_target && target != 0) {
- fs_inst *inst;
- fs_reg color = outputs[0];
- color.reg_offset += 3;
-
- inst = emit(MOV(fs_reg(MRF, write_color_mrf, color.type),
- color));
- inst->saturate = key->clamp_fragment_color;
- write_color_mrf = color_mrf + reg_width;
- }
-
- for (unsigned i = 0; i < this->output_components[target]; i++)
- emit_color_write(target, i, write_color_mrf);
-
- bool eot = false;
- if (target == key->nr_color_regions - 1) {
- eot = true;
-
- if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ } else if (key->nr_color_regions > 0) {
+ for (int target = 0; target < key->nr_color_regions; target++) {
+ this->current_annotation = ralloc_asprintf(this->mem_ctx,
+ "FB write target %d",
+ target);
+ fs_reg src0_alpha;
+ if (brw->gen >= 6 && key->replicate_alpha && target != 0)
+ src0_alpha = offset(outputs[0], 3);
+
+ if (target == key->nr_color_regions - 1 &&
+ (INTEL_DEBUG & DEBUG_SHADER_TIME))
emit_shader_time_end();
- }
- fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
- inst->target = target;
- inst->base_mrf = base_mrf;
- if (src0_alpha_to_render_target && target == 0)
- inst->mlen = nr - base_mrf - reg_width;
- else
- inst->mlen = nr - base_mrf;
- inst->eot = eot;
- inst->header_present = header_present;
- if ((brw->gen >= 8 || brw->is_haswell) && fp->UsesKill) {
- inst->predicate = BRW_PREDICATE_NORMAL;
- inst->flag_subreg = 1;
+ inst = emit_single_fb_write(this->outputs[target], reg_undef,
+ src0_alpha,
+ this->output_components[target]);
+ inst->target = target;
}
- }
+ } else {
+ if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ emit_shader_time_end();
- if (key->nr_color_regions == 0) {
/* Even if there's no color buffers enabled, we still need to send
* alpha out the pipeline to our null renderbuffer to support
* alpha-testing, alpha-to-coverage, and so on.
*/
- emit_color_write(0, 3, color_mrf);
-
- if (INTEL_DEBUG & DEBUG_SHADER_TIME)
- emit_shader_time_end();
-
- fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
- inst->base_mrf = base_mrf;
- inst->mlen = nr - base_mrf;
- inst->eot = true;
- inst->header_present = header_present;
- if ((brw->gen >= 8 || brw->is_haswell) && fp->UsesKill) {
- inst->predicate = BRW_PREDICATE_NORMAL;
- inst->flag_subreg = 1;
- }
+ inst = emit_single_fb_write(reg_undef, reg_undef, reg_undef, 0);
+ inst->target = 0;
}
+ inst->eot = true;
this->current_annotation = NULL;
}
unsigned dispatch_width)
: backend_visitor(brw, shader_prog, &fp->Base, &prog_data->base,
MESA_SHADER_FRAGMENT),
- key(key), prog_data(prog_data),
+ reg_null_f(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_F)),
+ reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
+ reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),
+ key(key), prog_data(&prog_data->base),
dispatch_width(dispatch_width)
{
- this->fp = fp;
this->mem_ctx = mem_ctx;
+ init();
+}
+
+void
+fs_visitor::init()
+{
this->failed = false;
this->simd16_unsupported = false;
this->no16_msg = NULL;
projects / mesa.git / blobdiff