#include "brw_context.h"
#include "brw_eu.h"
#include "brw_wm.h"
+#include "brw_cs.h"
#include "brw_vec4.h"
#include "brw_fs.h"
#include "main/uniforms.h"
reg = emit_sampleid_setup();
break;
case SYSTEM_VALUE_SAMPLE_MASK_IN:
- assert(brw->gen >= 7);
+ assert(devinfo->gen >= 7);
reg = new(mem_ctx)
fs_reg(retype(brw_vec8_grf(payload.sample_mask_in_reg, 0),
BRW_REGISTER_TYPE_D));
this->result = src;
}
-void
+fs_inst *
fs_visitor::emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
const fs_reg &a)
{
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
fs_reg y_times_a = vgrf(glsl_type::float_type);
fs_reg one_minus_a = vgrf(glsl_type::float_type);
emit(ADD(one_minus_a, negative_a, fs_reg(1.0f)));
emit(MUL(x_times_one_minus_a, x, one_minus_a));
- emit(ADD(dst, x_times_one_minus_a, y_times_a));
+ return emit(ADD(dst, x_times_one_minus_a, y_times_a));
} else {
/* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
* we need to reorder the operands.
*/
- emit(LRP(dst, a, y, x));
+ return emit(LRP(dst, a, y, x));
}
}
fs_inst *inst;
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->conditional_mod = conditionalmod;
} else {
}
}
+void
+fs_visitor::emit_uniformize(const fs_reg &dst, const fs_reg &src)
+{
+ const fs_reg chan_index = vgrf(glsl_type::uint_type);
+
+ emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, component(chan_index, 0))
+ ->force_writemask_all = true;
+ emit(SHADER_OPCODE_BROADCAST, component(dst, 0),
+ src, component(chan_index, 0))
+ ->force_writemask_all = true;
+}
+
bool
fs_visitor::try_emit_saturate(ir_expression *ir)
{
fs_visitor::try_emit_mad(ir_expression *ir)
{
/* 3-src instructions were introduced in gen6. */
- if (brw->gen < 6)
+ if (devinfo->gen < 6)
return false;
/* MAD can only handle floating-point data. */
* and(16) g4<1>D g2<8,8,1>D 1D
* and(16) m6<1>D -g4<8,8,1>D 0x3f800000UD
*
- * When the comparison is either == 0.0 or != 0.0 using the knowledge that
- * the true (or false) case already results in zero would allow better code
- * generation by possibly avoiding a load-immediate instruction.
+ * When the comparison is != 0.0 using the knowledge that the false case
+ * already results in zero would allow better code generation by possibly
+ * avoiding a load-immediate instruction.
*/
ir_expression *cmp = ir->operands[0]->as_expression();
if (cmp == NULL)
return false;
- if (cmp->operation == ir_binop_equal || cmp->operation == ir_binop_nequal) {
+ if (cmp->operation == ir_binop_nequal) {
for (unsigned i = 0; i < 2; i++) {
ir_constant *c = cmp->operands[i]->as_constant();
if (c == NULL || !c->is_zero())
fs_inst *inst = emit(SEL(this->result, op[i ^ 1], fs_reg(1.0f)));
inst->predicate = BRW_PREDICATE_NORMAL;
- inst->predicate_inverse = cmp->operation == ir_binop_equal;
+ inst->predicate_inverse = true;
return true;
}
}
/* 1. collect interpolation factors */
- fs_reg dst_x = vgrf(glsl_type::get_instance(ir->type->base_type, 2, 1));
- fs_reg dst_y = offset(dst_x, 1);
+ fs_reg dst_xy = vgrf(glsl_type::get_instance(ir->type->base_type, 2, 1));
/* for most messages, we need one reg of ignored data; the hardware requires mlen==1
* even when there is no payload. in the per-slot offset case, we'll replace this with
switch (ir->operation) {
case ir_unop_interpolate_at_centroid:
- inst = emit(FS_OPCODE_INTERPOLATE_AT_CENTROID, dst_x, src, fs_reg(0u));
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_CENTROID, dst_xy, src, fs_reg(0u));
break;
case ir_binop_interpolate_at_sample: {
assert(sample_num || !"nonconstant sample number should have been lowered.");
unsigned msg_data = sample_num->value.i[0] << 4;
- inst = emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_x, src, fs_reg(msg_data));
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_xy, src, fs_reg(msg_data));
break;
}
if (const_offset) {
unsigned msg_data = pack_pixel_offset(const_offset->value.f[0]) |
(pack_pixel_offset(const_offset->value.f[1]) << 4);
- inst = emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_x, src,
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_xy, src,
fs_reg(msg_data));
} else {
/* pack the operands: hw wants offsets as 4 bit signed ints */
}
mlen = 2 * reg_width;
- inst = emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, dst_x, src,
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, dst_xy, src,
fs_reg(0u));
}
break;
for (int i = 0; i < ir->type->vector_elements; i++) {
int ch = swiz ? ((*(int *)&swiz->mask) >> 2*i) & 3 : i;
- emit(FS_OPCODE_LINTERP, res,
- dst_x, dst_y,
+ emit(FS_OPCODE_LINTERP, res, dst_xy,
fs_reg(interp_reg(var->data.location, ch)));
res = offset(res, 1);
}
/* Deal with the real oddball stuff first */
switch (ir->operation) {
case ir_binop_add:
- if (brw->gen <= 5 && try_emit_line(ir))
+ if (devinfo->gen <= 5 && try_emit_line(ir))
return;
if (try_emit_mad(ir))
return;
return;
case ir_unop_b2f:
- if (brw->gen <= 5 && try_emit_b2f_of_comparison(ir))
+ if (devinfo->gen <= 5 && try_emit_b2f_of_comparison(ir))
return;
break;
case ir_unop_log:
unreachable("not reached: should be handled by ir_explog_to_explog2");
case ir_unop_sin:
- case ir_unop_sin_reduced:
emit_math(SHADER_OPCODE_SIN, this->result, op[0]);
break;
case ir_unop_cos:
- case ir_unop_cos_reduced:
emit_math(SHADER_OPCODE_COS, this->result, op[0]);
break;
unreachable("not reached: should be handled by ir_sub_to_add_neg");
case ir_binop_mul:
- if (brw->gen < 8 && ir->type->is_integer()) {
+ if (devinfo->gen < 8 && ir->type->is_integer()) {
/* For integer multiplication, the MUL uses the low 16 bits
* of one of the operands (src0 on gen6, src1 on gen7). The
* MACH accumulates in the contribution of the upper 16 bits
* of that operand.
*/
if (ir->operands[0]->is_uint16_constant()) {
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
emit(MUL(this->result, op[0], op[1]));
else
emit(MUL(this->result, op[1], op[0]));
} else if (ir->operands[1]->is_uint16_constant()) {
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
emit(MUL(this->result, op[1], op[0]));
else
emit(MUL(this->result, op[0], op[1]));
} else {
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
}
break;
case ir_binop_imul_high: {
- if (brw->gen == 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
*
* FINISHME: Don't use source modifiers on src1.
*/
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
mul->src[1].type == BRW_REGISTER_TYPE_UD);
if (mul->src[1].type == BRW_REGISTER_TYPE_D) {
mul->src[1].type = BRW_REGISTER_TYPE_W;
+ mul->src[1].stride = 2;
} else {
mul->src[1].type = BRW_REGISTER_TYPE_UW;
+ mul->src[1].stride = 2;
}
}
emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
break;
case ir_binop_carry: {
- if (brw->gen == 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
break;
}
case ir_binop_borrow: {
- if (brw->gen == 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
resolve_bool_comparison(ir->operands[1], &op[1]);
}
emit(AND(this->result, op[0], fs_reg(1)));
break;
case ir_unop_b2f:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
}
op[0].type = BRW_REGISTER_TYPE_D;
const_uniform_block->value.u[0]);
} else {
/* The block index is not a constant. Evaluate the index expression
- * per-channel and add the base UBO index; the generator will select
- * a value from any live channel.
+ * per-channel and add the base UBO index; we have to select a value
+ * from any live channel.
*/
surf_index = vgrf(glsl_type::uint_type);
emit(ADD(surf_index, op[0],
- fs_reg(stage_prog_data->binding_table.ubo_start)))
- ->force_writemask_all = true;
+ fs_reg(stage_prog_data->binding_table.ubo_start)));
+ emit_uniformize(surf_index, surf_index);
/* Assume this may touch any UBO. It would be nice to provide
* a tighter bound, but the array information is already lowered away.
return inst;
}
+fs_inst *
+fs_visitor::emit_texture_gen4_simd16(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int vector_elements,
+ fs_reg shadow_c, fs_reg lod,
+ uint32_t sampler)
+{
+ fs_reg message(MRF, 2, BRW_REGISTER_TYPE_F, dispatch_width);
+ bool has_lod = op == ir_txl || op == ir_txb || op == ir_txf;
+
+ if (has_lod && shadow_c.file != BAD_FILE)
+ no16("TXB and TXL with shadow comparison unsupported in SIMD16.");
+
+ if (op == ir_txd)
+ no16("textureGrad unsupported in SIMD16.");
+
+ /* Copy the coordinates. */
+ for (int i = 0; i < vector_elements; i++) {
+ emit(MOV(retype(offset(message, i), coordinate.type), coordinate));
+ coordinate = offset(coordinate, 1);
+ }
+
+ fs_reg msg_end = offset(message, vector_elements);
+
+ /* Messages other than sample and ld require all three components */
+ if (has_lod || shadow_c.file != BAD_FILE) {
+ for (int i = vector_elements; i < 3; i++) {
+ emit(MOV(offset(message, i), fs_reg(0.0f)));
+ }
+ }
+
+ if (has_lod) {
+ fs_reg msg_lod = retype(offset(message, 3), op == ir_txf ?
+ BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_F);
+ emit(MOV(msg_lod, lod));
+ msg_end = offset(msg_lod, 1);
+ }
+
+ if (shadow_c.file != BAD_FILE) {
+ fs_reg msg_ref = offset(message, 3 + has_lod);
+ emit(MOV(msg_ref, shadow_c));
+ msg_end = offset(msg_ref, 1);
+ }
+
+ enum opcode opcode;
+ switch (op) {
+ case ir_tex: opcode = SHADER_OPCODE_TEX; break;
+ case ir_txb: opcode = FS_OPCODE_TXB; break;
+ case ir_txd: opcode = SHADER_OPCODE_TXD; break;
+ case ir_txl: opcode = SHADER_OPCODE_TXL; break;
+ case ir_txs: opcode = SHADER_OPCODE_TXS; break;
+ case ir_txf: opcode = SHADER_OPCODE_TXF; break;
+ default: unreachable("not reached");
+ }
+
+ fs_inst *inst = emit(opcode, dst, reg_undef, fs_reg(sampler));
+ inst->base_mrf = message.reg - 1;
+ inst->mlen = msg_end.reg - inst->base_mrf;
+ inst->header_present = true;
+ inst->regs_written = 8;
+
+ return inst;
+}
+
/* gen5's sampler has slots for u, v, r, array index, then optional
* parameters like shadow comparitor or LOD bias. If optional
* parameters aren't present, those base slots are optional and don't
}
static bool
-is_high_sampler(struct brw_context *brw, fs_reg sampler)
+is_high_sampler(const struct brw_device_info *devinfo, fs_reg sampler)
{
- if (brw->gen < 8 && !brw->is_haswell)
+ if (devinfo->gen < 8 && !devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
int length = 0;
if (op == ir_tg4 || offset_value.file != BAD_FILE ||
- is_high_sampler(brw, sampler)) {
+ is_high_sampler(devinfo, sampler)) {
/* For general texture offsets (no txf workaround), we need a header to
* put them in. Note that for SIMD16 we're making space for two actual
* hardware registers here, so the emit will have to fix up for this.
offset_value.file != BAD_FILE && offset_value.file != IMM;
bool coordinate_done = false;
+ /* The sampler can only meaningfully compute LOD for fragment shader
+ * messages. For all other stages, we change the opcode to ir_txl and
+ * hardcode the LOD to 0.
+ */
+ if (stage != MESA_SHADER_FRAGMENT && op == ir_tex) {
+ op = ir_txl;
+ lod = fs_reg(0.0f);
+ }
+
/* Set up the LOD info */
switch (op) {
case ir_tex:
length++;
break;
case ir_txf:
- /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
+ /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
+ * On Gen9 they are u, v, lod, r
+ */
+
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
coordinate = offset(coordinate, 1);
length++;
+ if (devinfo->gen >= 9) {
+ if (coord_components >= 2) {
+ emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
+ coordinate = offset(coordinate, 1);
+ }
+ length++;
+ }
+
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), lod));
length++;
- for (int i = 1; i < coord_components; i++) {
+ for (int i = devinfo->gen >= 9 ? 2 : 1; i < coord_components; i++) {
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
coordinate = offset(coordinate, 1);
length++;
* tracking to get the scaling factor.
*/
if (is_rect &&
- (brw->gen < 6 ||
- (brw->gen >= 6 && (key_tex->gl_clamp_mask[0] & (1 << sampler) ||
- key_tex->gl_clamp_mask[1] & (1 << sampler))))) {
+ (devinfo->gen < 6 ||
+ (devinfo->gen >= 6 && (key_tex->gl_clamp_mask[0] & (1 << sampler) ||
+ key_tex->gl_clamp_mask[1] & (1 << sampler))))) {
struct gl_program_parameter_list *params = prog->Parameters;
int tokens[STATE_LENGTH] = {
STATE_INTERNAL,
* texture coordinates. We use the program parameter state
* tracking to get the scaling factor.
*/
- if (brw->gen < 6 && is_rect) {
+ if (devinfo->gen < 6 && is_rect) {
fs_reg dst = fs_reg(GRF, alloc.allocate(coord_components));
fs_reg src = coordinate;
coordinate = dst;
*/
fs_reg dst = vgrf(glsl_type::get_instance(dest_type->base_type, 4, 1));
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
inst = emit_texture_gen7(op, dst, coordinate, coord_components,
shadow_c, lod, lod2, grad_components,
sample_index, mcs, sampler_reg,
offset_value);
- } else if (brw->gen >= 5) {
+ } else if (devinfo->gen >= 5) {
inst = emit_texture_gen5(op, dst, coordinate, coord_components,
shadow_c, lod, lod2, grad_components,
sample_index, sampler,
offset_value.file != BAD_FILE);
+ } else if (dispatch_width == 16) {
+ inst = emit_texture_gen4_simd16(op, dst, coordinate, coord_components,
+ shadow_c, lod, sampler);
} else {
inst = emit_texture_gen4(op, dst, coordinate, coord_components,
shadow_c, lod, lod2, grad_components,
inst->offset |=
gather_channel(gather_component, sampler) << 16; /* M0.2:16-17 */
- if (brw->gen == 6)
+ if (devinfo->gen == 6)
emit_gen6_gather_wa(key_tex->gen6_gather_wa[sampler], dst);
}
->array->type->array_size();
uint32_t max_used = sampler + array_size - 1;
- if (ir->op == ir_tg4 && brw->gen < 8) {
+ if (ir->op == ir_tg4 && devinfo->gen < 8) {
max_used += stage_prog_data->binding_table.gather_texture_start;
} else {
max_used += stage_prog_data->binding_table.texture_start;
* offset, and a non-constant offset.
*/
offset_value =
- fs_reg(brw_texture_offset(ctx, const_offset->value.i,
+ fs_reg(brw_texture_offset(const_offset->value.i,
const_offset->type->vector_elements));
} else {
ir->offset->accept(this);
ir->lod_info.sample_index->accept(this);
sample_index = this->result;
- if (brw->gen >= 7 &&
+ if (devinfo->gen >= 7 &&
key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
mcs = emit_mcs_fetch(coordinate, ir->coordinate->type->vector_elements,
sampler_reg);
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
- if (brw->gen >= 6) {
- /* For performance, after a discard, jump to the end of the shader.
- * Only jump if all relevant channels have been discarded.
- */
- fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
- discard_jump->flag_subreg = 1;
-
- discard_jump->predicate = (dispatch_width == 8)
- ? BRW_PREDICATE_ALIGN1_ANY8H
- : BRW_PREDICATE_ALIGN1_ANY16H;
- discard_jump->predicate_inverse = true;
+ if (devinfo->gen >= 6) {
+ emit_discard_jump();
}
}
emit(MOV(dst_reg, fs_reg(ir->value.i[i])));
break;
case GLSL_TYPE_BOOL:
- emit(MOV(dst_reg,
- fs_reg(ir->value.b[i] != 0 ? (int)ctx->Const.UniformBooleanTrue
- : 0)));
+ emit(MOV(dst_reg, fs_reg(ir->value.b[i] != 0 ? ~0 : 0)));
break;
default:
unreachable("Non-float/uint/int/bool constant");
break;
case ir_binop_logic_xor:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
fs_reg temp = vgrf(expr->type);
emit(XOR(temp, op[0], op[1]));
inst = emit(AND(reg_null_d, temp, fs_reg(1)));
break;
case ir_binop_logic_or:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
fs_reg temp = vgrf(expr->type);
emit(OR(temp, op[0], op[1]));
inst = emit(AND(reg_null_d, temp, fs_reg(1)));
break;
case ir_binop_logic_and:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
fs_reg temp = vgrf(expr->type);
emit(AND(temp, op[0], op[1]));
inst = emit(AND(reg_null_d, temp, fs_reg(1)));
break;
case ir_unop_f2b:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_f, op[0]));
break;
case ir_unop_i2b:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_d, op[0]));
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- if (brw->gen <= 5) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
dst.type = BRW_REGISTER_TYPE_D;
fs_reg tmp = vgrf(glsl_type::int_type);
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
/* Bit 15 of g0.0 is 0 if the polygon is front facing. */
fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
*/
this->base_ir = ir->condition;
- if (brw->gen == 6) {
+ if (devinfo->gen == 6) {
emit_if_gen6(ir);
} else {
emit_bool_to_cond_code(ir->condition);
emit(BRW_OPCODE_ENDIF);
- if (!try_replace_with_sel() && brw->gen < 6) {
+ if (!try_replace_with_sel() && devinfo->gen < 6) {
no16("Can't support (non-uniform) control flow on SIMD16\n");
}
}
void
fs_visitor::visit(ir_loop *ir)
{
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
no16("Can't support (non-uniform) control flow on SIMD16\n");
}
/* Emit the instruction. */
fs_inst *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst, src_payload,
- fs_reg(atomic_op), fs_reg(surf_index));
+ fs_reg(surf_index), fs_reg(atomic_op));
inst->mlen = mlen;
}
/* Emit the instruction. */
inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst, src_payload,
- fs_reg(surf_index));
+ fs_reg(surf_index), fs_reg(1));
inst->mlen = mlen;
}
fs_inst *write;
write = emit(FS_OPCODE_FB_WRITE);
write->eot = true;
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
write->base_mrf = 2;
write->mlen = 4 * reg_width;
} else {
* varying to avoid GPU hangs, so set that.
*/
brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data;
- wm_prog_data->num_varying_inputs = brw->gen < 6 ? 1 : 0;
+ wm_prog_data->num_varying_inputs = devinfo->gen < 6 ? 1 : 0;
memset(wm_prog_data->urb_setup, -1,
sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
void
fs_visitor::emit_interpolation_setup_gen4()
{
+ struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
+
this->current_annotation = "compute pixel centers";
this->pixel_x = vgrf(glsl_type::uint_type);
this->pixel_y = vgrf(glsl_type::uint_type);
this->pixel_x.type = BRW_REGISTER_TYPE_UW;
this->pixel_y.type = BRW_REGISTER_TYPE_UW;
-
- emit(FS_OPCODE_PIXEL_X, this->pixel_x);
- emit(FS_OPCODE_PIXEL_Y, this->pixel_y);
+ emit(ADD(this->pixel_x,
+ fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x10101010))));
+ emit(ADD(this->pixel_y,
+ fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x11001100))));
this->current_annotation = "compute pixel deltas from v0";
- if (brw->has_pln) {
- this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- vgrf(glsl_type::vec2_type);
- this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- offset(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1);
+
+ this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
+ vgrf(glsl_type::vec2_type);
+ const fs_reg &delta_xy = this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
+ const fs_reg xstart(negate(brw_vec1_grf(1, 0)));
+ const fs_reg ystart(negate(brw_vec1_grf(1, 1)));
+
+ if (devinfo->has_pln && dispatch_width == 16) {
+ emit(ADD(half(offset(delta_xy, 0), 0), half(this->pixel_x, 0), xstart));
+ emit(ADD(half(offset(delta_xy, 0), 1), half(this->pixel_y, 0), ystart));
+ emit(ADD(half(offset(delta_xy, 1), 0), half(this->pixel_x, 1), xstart))
+ ->force_sechalf = true;
+ emit(ADD(half(offset(delta_xy, 1), 1), half(this->pixel_y, 1), ystart))
+ ->force_sechalf = true;
} else {
- this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- vgrf(glsl_type::float_type);
- this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- vgrf(glsl_type::float_type);
+ emit(ADD(offset(delta_xy, 0), this->pixel_x, xstart));
+ emit(ADD(offset(delta_xy, 1), this->pixel_y, ystart));
}
- emit(ADD(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))));
- emit(ADD(this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))));
this->current_annotation = "compute pos.w and 1/pos.w";
/* Compute wpos.w. It's always in our setup, since it's needed to
* interpolate the other attributes.
*/
this->wpos_w = vgrf(glsl_type::float_type);
- emit(FS_OPCODE_LINTERP, wpos_w,
- this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- interp_reg(VARYING_SLOT_POS, 3));
+ emit(FS_OPCODE_LINTERP, wpos_w, delta_xy, interp_reg(VARYING_SLOT_POS, 3));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = vgrf(glsl_type::float_type);
emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
{
struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
- /* If the pixel centers end up used, the setup is the same as for gen4. */
this->current_annotation = "compute pixel centers";
- fs_reg int_pixel_x = vgrf(glsl_type::uint_type);
- fs_reg int_pixel_y = vgrf(glsl_type::uint_type);
- int_pixel_x.type = BRW_REGISTER_TYPE_UW;
- int_pixel_y.type = BRW_REGISTER_TYPE_UW;
- emit(ADD(int_pixel_x,
- fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
- fs_reg(brw_imm_v(0x10101010))));
- emit(ADD(int_pixel_y,
- fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
- fs_reg(brw_imm_v(0x11001100))));
-
- /* As of gen6, we can no longer mix float and int sources. We have
- * to turn the integer pixel centers into floats for their actual
- * use.
- */
- this->pixel_x = vgrf(glsl_type::float_type);
- this->pixel_y = vgrf(glsl_type::float_type);
- emit(MOV(this->pixel_x, int_pixel_x));
- emit(MOV(this->pixel_y, int_pixel_y));
+ if (brw->gen >= 8 || dispatch_width == 8) {
+ /* The "Register Region Restrictions" page says for BDW (and newer,
+ * presumably):
+ *
+ * "When destination spans two registers, the source may be one or
+ * two registers. The destination elements must be evenly split
+ * between the two registers."
+ *
+ * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
+ * compute our pixel centers.
+ */
+ fs_reg int_pixel_xy(GRF, alloc.allocate(dispatch_width / 8),
+ BRW_REGISTER_TYPE_UW, dispatch_width * 2);
+ emit(ADD(int_pixel_xy,
+ fs_reg(stride(suboffset(g1_uw, 4), 1, 4, 0)),
+ fs_reg(brw_imm_v(0x11001010))))
+ ->force_writemask_all = true;
+
+ this->pixel_x = vgrf(glsl_type::float_type);
+ this->pixel_y = vgrf(glsl_type::float_type);
+ emit(FS_OPCODE_PIXEL_X, this->pixel_x, int_pixel_xy);
+ emit(FS_OPCODE_PIXEL_Y, this->pixel_y, int_pixel_xy);
+ } else {
+ /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
+ *
+ * "When destination spans two registers, the source MUST span two
+ * registers."
+ *
+ * Since the GRF source of the ADD will only read a single register, we
+ * must do two separate ADDs in SIMD16.
+ */
+ fs_reg int_pixel_x = vgrf(glsl_type::uint_type);
+ fs_reg int_pixel_y = vgrf(glsl_type::uint_type);
+ int_pixel_x.type = BRW_REGISTER_TYPE_UW;
+ int_pixel_y.type = BRW_REGISTER_TYPE_UW;
+ emit(ADD(int_pixel_x,
+ fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x10101010))));
+ emit(ADD(int_pixel_y,
+ fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x11001100))));
+
+ /* As of gen6, we can no longer mix float and int sources. We have
+ * to turn the integer pixel centers into floats for their actual
+ * use.
+ */
+ this->pixel_x = vgrf(glsl_type::float_type);
+ this->pixel_y = vgrf(glsl_type::float_type);
+ emit(MOV(this->pixel_x, int_pixel_x));
+ emit(MOV(this->pixel_y, int_pixel_y));
+ }
this->current_annotation = "compute pos.w";
this->pixel_w = fs_reg(brw_vec8_grf(payload.source_w_reg, 0));
for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
uint8_t reg = payload.barycentric_coord_reg[i];
- this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0));
- this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0));
+ this->delta_xy[i] = fs_reg(brw_vec16_grf(reg, 0));
}
this->current_annotation = NULL;
colors_enabled = (1 << components) - 1;
}
- if (dispatch_width == 8 || (brw->gen >= 6 && !do_dual_src)) {
+ if (dispatch_width == 8 || (devinfo->gen >= 6 && !do_dual_src)) {
/* SIMD8 write looks like:
* m + 0: r0
* m + 1: r1
len++;
}
return len;
- } else if (brw->gen >= 6 && do_dual_src) {
+ } else if (devinfo->gen >= 6 && do_dual_src) {
/* SIMD16 dual source blending for gen6+.
*
* From the SNB PRM, volume 4, part 1, page 193:
* dispatched. This field is only required for the end-of-
* thread message and on all dual-source messages."
*/
- if (brw->gen >= 6 &&
- (brw->is_haswell || brw->gen >= 8 || !prog_data->uses_kill) &&
+ if (devinfo->gen >= 6 &&
+ (devinfo->is_haswell || devinfo->gen >= 8 || !prog_data->uses_kill) &&
color1.file == BAD_FILE &&
key->nr_color_regions == 1) {
header_present = false;
}
if (source_depth_to_render_target) {
- if (brw->gen == 6) {
+ if (devinfo->gen == 6) {
/* For outputting oDepth on gen6, SIMD8 writes have to be
* used. This would require SIMD8 moves of each half to
* message regs, kind of like pre-gen5 SIMD16 FB writes.
fs_inst *load;
fs_inst *write;
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
/* Send from the GRF */
fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F);
load = emit(LOAD_PAYLOAD(payload, sources, length));
"FB write target %d",
target);
fs_reg src0_alpha;
- if (brw->gen >= 6 && key->replicate_alpha && target != 0)
+ if (devinfo->gen >= 6 && key->replicate_alpha && target != 0)
src0_alpha = offset(outputs[0], 3);
inst = emit_single_fb_write(this->outputs[target], reg_undef,
*reg = temp;
}
+void
+fs_visitor::emit_cs_terminate()
+{
+ assert(brw->gen >= 7);
+
+ /* We are getting the thread ID from the compute shader header */
+ assert(stage == MESA_SHADER_COMPUTE);
+
+ /* We can't directly send from g0, since sends with EOT have to use
+ * g112-127. So, copy it to a virtual register, The register allocator will
+ * make sure it uses the appropriate register range.
+ */
+ struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD);
+ fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ fs_inst *inst = emit(MOV(payload, g0));
+ inst->force_writemask_all = true;
+
+ /* Send a message to the thread spawner to terminate the thread. */
+ inst = emit(CS_OPCODE_CS_TERMINATE, reg_undef, payload);
+ inst->eot = true;
+}
+
/**
* Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
*
void
fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
{
- assert(brw->gen <= 5);
+ assert(devinfo->gen <= 5);
if (rvalue->type != glsl_type::bool_type)
return;
reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),
key(key), prog_data(&prog_data->base),
- dispatch_width(dispatch_width)
+ dispatch_width(dispatch_width), promoted_constants(0)
{
this->mem_ctx = mem_ctx;
init();
reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),
key(key), prog_data(&prog_data->base.base),
+ dispatch_width(dispatch_width), promoted_constants(0)
+{
+ this->mem_ctx = mem_ctx;
+ init();
+}
+
+fs_visitor::fs_visitor(struct brw_context *brw,
+ void *mem_ctx,
+ const struct brw_cs_prog_key *key,
+ struct brw_cs_prog_data *prog_data,
+ struct gl_shader_program *shader_prog,
+ struct gl_compute_program *cp,
+ unsigned dispatch_width)
+ : backend_visitor(brw, shader_prog, &cp->Base, &prog_data->base,
+ MESA_SHADER_COMPUTE),
+ reg_null_f(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_F)),
+ reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
+ reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),
+ key(key), prog_data(&prog_data->base),
dispatch_width(dispatch_width)
{
this->mem_ctx = mem_ctx;
case MESA_SHADER_GEOMETRY:
key_tex = &((const brw_vue_prog_key *) key)->tex;
break;
+ case MESA_SHADER_COMPUTE:
+ key_tex = &((const brw_cs_prog_key*) key)->tex;
+ break;
default:
unreachable("unhandled shader stage");
}
this->source_depth_to_render_target = false;
this->runtime_check_aads_emit = false;
this->first_non_payload_grf = 0;
- this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+ this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->current_annotation = NULL;
this->base_ir = NULL;
projects / mesa.git / blobdiff