* makes it easier to do backend-specific optimizations than doing so
* in the GLSL IR or in the native code.
*/
-extern "C" {
-
#include <sys/types.h>
#include "main/macros.h"
#include "program/prog_print.h"
#include "program/prog_optimize.h"
#include "util/register_allocate.h"
-#include "program/sampler.h"
#include "program/hash_table.h"
#include "brw_context.h"
#include "brw_eu.h"
#include "brw_wm.h"
-}
+#include "brw_cs.h"
+#include "brw_vec4.h"
#include "brw_fs.h"
#include "main/uniforms.h"
#include "glsl/glsl_types.h"
#include "glsl/ir_optimization.h"
+#include "program/sampler.h"
+
+
+fs_reg *
+fs_visitor::emit_vs_system_value(int location)
+{
+ fs_reg *reg = new(this->mem_ctx)
+ fs_reg(ATTR, VERT_ATTRIB_MAX, BRW_REGISTER_TYPE_D);
+ brw_vs_prog_data *vs_prog_data = (brw_vs_prog_data *) prog_data;
+
+ switch (location) {
+ case SYSTEM_VALUE_BASE_VERTEX:
+ reg->reg_offset = 0;
+ vs_prog_data->uses_vertexid = true;
+ break;
+ case SYSTEM_VALUE_VERTEX_ID:
+ case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
+ reg->reg_offset = 2;
+ vs_prog_data->uses_vertexid = true;
+ break;
+ case SYSTEM_VALUE_INSTANCE_ID:
+ reg->reg_offset = 3;
+ vs_prog_data->uses_instanceid = true;
+ break;
+ default:
+ unreachable("not reached");
+ }
+
+ return reg;
+}
void
fs_visitor::visit(ir_variable *ir)
return;
if (ir->data.mode == ir_var_shader_in) {
- if (!strcmp(ir->name, "gl_FragCoord")) {
- reg = emit_fragcoord_interpolation(ir);
- } else if (!strcmp(ir->name, "gl_FrontFacing")) {
+ assert(ir->data.location != -1);
+ if (stage == MESA_SHADER_VERTEX) {
+ reg = new(this->mem_ctx)
+ fs_reg(ATTR, ir->data.location,
+ brw_type_for_base_type(ir->type->get_scalar_type()));
+ } else if (ir->data.location == VARYING_SLOT_POS) {
+ reg = emit_fragcoord_interpolation(ir->data.pixel_center_integer,
+ ir->data.origin_upper_left);
+ } else if (ir->data.location == VARYING_SLOT_FACE) {
reg = emit_frontfacing_interpolation();
} else {
- reg = emit_general_interpolation(ir);
+ reg = new(this->mem_ctx) fs_reg(vgrf(ir->type));
+ emit_general_interpolation(*reg, ir->name, ir->type,
+ (glsl_interp_qualifier) ir->data.interpolation,
+ ir->data.location, ir->data.centroid,
+ ir->data.sample);
}
assert(reg);
hash_table_insert(this->variable_ht, reg, ir);
return;
} else if (ir->data.mode == ir_var_shader_out) {
- reg = new(this->mem_ctx) fs_reg(this, ir->type);
+ reg = new(this->mem_ctx) fs_reg(vgrf(ir->type));
+
+ if (stage == MESA_SHADER_VERTEX) {
+ int vector_elements =
+ ir->type->is_array() ? ir->type->fields.array->vector_elements
+ : ir->type->vector_elements;
+
+ for (int i = 0; i < (type_size(ir->type) + 3) / 4; i++) {
+ int output = ir->data.location + i;
+ this->outputs[output] = *reg;
+ this->outputs[output].reg_offset = i * 4;
+ this->output_components[output] = vector_elements;
+ }
- if (ir->data.index > 0) {
+ } else if (ir->data.index > 0) {
assert(ir->data.location == FRAG_RESULT_DATA0);
assert(ir->data.index == 1);
this->dual_src_output = *reg;
reg->type = brw_type_for_base_type(ir->type);
} else if (ir->data.mode == ir_var_system_value) {
- if (ir->data.location == SYSTEM_VALUE_SAMPLE_POS) {
+ switch (ir->data.location) {
+ case SYSTEM_VALUE_BASE_VERTEX:
+ case SYSTEM_VALUE_VERTEX_ID:
+ case SYSTEM_VALUE_VERTEX_ID_ZERO_BASE:
+ case SYSTEM_VALUE_INSTANCE_ID:
+ reg = emit_vs_system_value(ir->data.location);
+ break;
+ case SYSTEM_VALUE_SAMPLE_POS:
reg = emit_samplepos_setup();
- } else if (ir->data.location == SYSTEM_VALUE_SAMPLE_ID) {
- reg = emit_sampleid_setup(ir);
- } else if (ir->data.location == SYSTEM_VALUE_SAMPLE_MASK_IN) {
- assert(brw->gen >= 7);
+ break;
+ case SYSTEM_VALUE_SAMPLE_ID:
+ reg = emit_sampleid_setup();
+ break;
+ case SYSTEM_VALUE_SAMPLE_MASK_IN:
+ assert(devinfo->gen >= 7);
reg = new(mem_ctx)
fs_reg(retype(brw_vec8_grf(payload.sample_mask_in_reg, 0),
BRW_REGISTER_TYPE_D));
+ break;
}
}
if (!reg)
- reg = new(this->mem_ctx) fs_reg(this, ir->type);
+ reg = new(this->mem_ctx) fs_reg(vgrf(ir->type));
hash_table_insert(this->variable_ht, reg, ir);
}
src.type = brw_type_for_base_type(ir->type);
if (constant_index) {
- assert(src.file == UNIFORM || src.file == GRF || src.file == HW_REG);
- src = offset(src, constant_index->value.i[0] * element_size);
+ if (src.file == ATTR) {
+ /* Attribute arrays get loaded as one vec4 per element. In that case
+ * offset the source register.
+ */
+ src.reg += constant_index->value.i[0];
+ } else {
+ assert(src.file == UNIFORM || src.file == GRF || src.file == HW_REG);
+ src = offset(src, constant_index->value.i[0] * element_size);
+ }
} else {
/* Variable index array dereference. We attach the variable index
* component to the reg as a pointer to a register containing the
ir->array_index->accept(this);
fs_reg index_reg;
- index_reg = fs_reg(this, glsl_type::int_type);
+ index_reg = vgrf(glsl_type::int_type);
emit(BRW_OPCODE_MUL, index_reg, this->result, fs_reg(element_size));
if (src.reladdr) {
this->result = src;
}
-void
+fs_inst *
fs_visitor::emit_lrp(const fs_reg &dst, const fs_reg &x, const fs_reg &y,
const fs_reg &a)
{
- if (brw->gen < 6 ||
- !x.is_valid_3src() ||
- !y.is_valid_3src() ||
- !a.is_valid_3src()) {
+ if (devinfo->gen < 6) {
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
- fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
- fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
- fs_reg x_times_one_minus_a = fs_reg(this, glsl_type::float_type);
+ fs_reg y_times_a = vgrf(glsl_type::float_type);
+ fs_reg one_minus_a = vgrf(glsl_type::float_type);
+ fs_reg x_times_one_minus_a = vgrf(glsl_type::float_type);
emit(MUL(y_times_a, y, a));
emit(ADD(one_minus_a, negative_a, fs_reg(1.0f)));
emit(MUL(x_times_one_minus_a, x, one_minus_a));
- emit(ADD(dst, x_times_one_minus_a, y_times_a));
+ return emit(ADD(dst, x_times_one_minus_a, y_times_a));
} else {
/* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
* we need to reorder the operands.
*/
- emit(LRP(dst, a, y, x));
+ return emit(LRP(dst, a, y, x));
}
}
fs_visitor::emit_minmax(enum brw_conditional_mod conditionalmod, const fs_reg &dst,
const fs_reg &src0, const fs_reg &src1)
{
+ assert(conditionalmod == BRW_CONDITIONAL_GE ||
+ conditionalmod == BRW_CONDITIONAL_L);
+
fs_inst *inst;
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->conditional_mod = conditionalmod;
} else {
}
}
+void
+fs_visitor::emit_uniformize(const fs_reg &dst, const fs_reg &src)
+{
+ const fs_reg chan_index = vgrf(glsl_type::uint_type);
+
+ emit(SHADER_OPCODE_FIND_LIVE_CHANNEL, component(chan_index, 0))
+ ->force_writemask_all = true;
+ emit(SHADER_OPCODE_BROADCAST, component(dst, 0),
+ src, component(chan_index, 0))
+ ->force_writemask_all = true;
+}
+
bool
fs_visitor::try_emit_saturate(ir_expression *ir)
{
}
bool
-fs_visitor::try_emit_mad(ir_expression *ir)
+fs_visitor::try_emit_line(ir_expression *ir)
{
- /* 3-src instructions were introduced in gen6. */
- if (brw->gen < 6)
- return false;
-
- /* MAD can only handle floating-point data. */
+ /* LINE's src0 must be of type float. */
if (ir->type != glsl_type::float_type)
return false;
return false;
}
- if (nonmul->as_constant() ||
- mul->operands[0]->as_constant() ||
- mul->operands[1]->as_constant())
+ ir_constant *const_add = nonmul->as_constant();
+ if (!const_add)
+ return false;
+
+ int add_operand_vf = brw_float_to_vf(const_add->value.f[0]);
+ if (add_operand_vf == -1)
+ return false;
+
+ ir_rvalue *non_const_mul = mul->operands[1];
+ ir_constant *const_mul = mul->operands[0]->as_constant();
+ if (!const_mul) {
+ const_mul = mul->operands[1]->as_constant();
+
+ if (!const_mul)
+ return false;
+
+ non_const_mul = mul->operands[0];
+ }
+
+ int mul_operand_vf = brw_float_to_vf(const_mul->value.f[0]);
+ if (mul_operand_vf == -1)
+ return false;
+
+ non_const_mul->accept(this);
+ fs_reg src1 = this->result;
+
+ fs_reg src0 = vgrf(ir->type);
+ emit(BRW_OPCODE_MOV, src0,
+ fs_reg((uint8_t)mul_operand_vf, 0, 0, (uint8_t)add_operand_vf));
+
+ this->result = vgrf(ir->type);
+ emit(BRW_OPCODE_LINE, this->result, src0, src1);
+ return true;
+}
+
+bool
+fs_visitor::try_emit_mad(ir_expression *ir)
+{
+ /* 3-src instructions were introduced in gen6. */
+ if (devinfo->gen < 6)
+ return false;
+
+ /* MAD can only handle floating-point data. */
+ if (ir->type != glsl_type::float_type)
+ return false;
+
+ ir_rvalue *nonmul;
+ ir_expression *mul;
+ bool mul_negate, mul_abs;
+
+ for (int i = 0; i < 2; i++) {
+ mul_negate = false;
+ mul_abs = false;
+
+ mul = ir->operands[i]->as_expression();
+ nonmul = ir->operands[1 - i];
+
+ if (mul && mul->operation == ir_unop_abs) {
+ mul = mul->operands[0]->as_expression();
+ mul_abs = true;
+ } else if (mul && mul->operation == ir_unop_neg) {
+ mul = mul->operands[0]->as_expression();
+ mul_negate = true;
+ }
+
+ if (mul && mul->operation == ir_binop_mul)
+ break;
+ }
+
+ if (!mul || mul->operation != ir_binop_mul)
return false;
nonmul->accept(this);
mul->operands[0]->accept(this);
fs_reg src1 = this->result;
+ src1.negate ^= mul_negate;
+ src1.abs = mul_abs;
+ if (mul_abs)
+ src1.negate = false;
mul->operands[1]->accept(this);
fs_reg src2 = this->result;
+ src2.abs = mul_abs;
+ if (mul_abs)
+ src2.negate = false;
- this->result = fs_reg(this, ir->type);
+ this->result = vgrf(ir->type);
emit(BRW_OPCODE_MAD, this->result, src0, src1, src2);
return true;
}
+bool
+fs_visitor::try_emit_b2f_of_comparison(ir_expression *ir)
+{
+ /* On platforms that do not natively generate 0u and ~0u for Boolean
+ * results, b2f expressions that look like
+ *
+ * f = b2f(expr cmp 0)
+ *
+ * will generate better code by pretending the expression is
+ *
+ * f = ir_triop_csel(0.0, 1.0, expr cmp 0)
+ *
+ * This is because the last instruction of "expr" can generate the
+ * condition code for the "cmp 0". This avoids having to do the "-(b & 1)"
+ * trick to generate 0u or ~0u for the Boolean result. This means code like
+ *
+ * mov(16) g16<1>F 1F
+ * mul.ge.f0(16) null g6<8,8,1>F g14<8,8,1>F
+ * (+f0) sel(16) m6<1>F g16<8,8,1>F 0F
+ *
+ * will be generated instead of
+ *
+ * mul(16) g2<1>F g12<8,8,1>F g4<8,8,1>F
+ * cmp.ge.f0(16) g2<1>D g4<8,8,1>F 0F
+ * and(16) g4<1>D g2<8,8,1>D 1D
+ * and(16) m6<1>D -g4<8,8,1>D 0x3f800000UD
+ *
+ * When the comparison is != 0.0 using the knowledge that the false case
+ * already results in zero would allow better code generation by possibly
+ * avoiding a load-immediate instruction.
+ */
+ ir_expression *cmp = ir->operands[0]->as_expression();
+ if (cmp == NULL)
+ return false;
+
+ if (cmp->operation == ir_binop_nequal) {
+ for (unsigned i = 0; i < 2; i++) {
+ ir_constant *c = cmp->operands[i]->as_constant();
+ if (c == NULL || !c->is_zero())
+ continue;
+
+ ir_expression *expr = cmp->operands[i ^ 1]->as_expression();
+ if (expr != NULL) {
+ fs_reg op[2];
+
+ for (unsigned j = 0; j < 2; j++) {
+ cmp->operands[j]->accept(this);
+ op[j] = this->result;
+
+ resolve_ud_negate(&op[j]);
+ }
+
+ emit_bool_to_cond_code_of_reg(cmp, op);
+
+ /* In this case we know when the condition is true, op[i ^ 1]
+ * contains zero. Invert the predicate, use op[i ^ 1] as src0,
+ * and immediate 1.0f as src1.
+ */
+ this->result = vgrf(ir->type);
+ op[i ^ 1].type = BRW_REGISTER_TYPE_F;
+
+ fs_inst *inst = emit(SEL(this->result, op[i ^ 1], fs_reg(1.0f)));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ inst->predicate_inverse = true;
+ return true;
+ }
+ }
+ }
+
+ emit_bool_to_cond_code(cmp);
+
+ fs_reg temp = vgrf(ir->type);
+ emit(MOV(temp, fs_reg(1.0f)));
+
+ this->result = vgrf(ir->type);
+ fs_inst *inst = emit(SEL(this->result, temp, fs_reg(0.0f)));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+
+ return true;
+}
+
static int
pack_pixel_offset(float x)
{
/* 1. collect interpolation factors */
- fs_reg dst_x = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 2, 1));
- fs_reg dst_y = offset(dst_x, 1);
+ fs_reg dst_xy = vgrf(glsl_type::get_instance(ir->type->base_type, 2, 1));
/* for most messages, we need one reg of ignored data; the hardware requires mlen==1
* even when there is no payload. in the per-slot offset case, we'll replace this with
* the proper source data. */
- fs_reg src = fs_reg(this, glsl_type::float_type);
+ fs_reg src = vgrf(glsl_type::float_type);
int mlen = 1; /* one reg unless overriden */
int reg_width = dispatch_width / 8;
fs_inst *inst;
switch (ir->operation) {
case ir_unop_interpolate_at_centroid:
- inst = emit(FS_OPCODE_INTERPOLATE_AT_CENTROID, dst_x, src, fs_reg(0u));
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_CENTROID, dst_xy, src, fs_reg(0u));
break;
case ir_binop_interpolate_at_sample: {
assert(sample_num || !"nonconstant sample number should have been lowered.");
unsigned msg_data = sample_num->value.i[0] << 4;
- inst = emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_x, src, fs_reg(msg_data));
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_xy, src, fs_reg(msg_data));
break;
}
if (const_offset) {
unsigned msg_data = pack_pixel_offset(const_offset->value.f[0]) |
(pack_pixel_offset(const_offset->value.f[1]) << 4);
- inst = emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_x, src,
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_xy, src,
fs_reg(msg_data));
} else {
/* pack the operands: hw wants offsets as 4 bit signed ints */
ir->operands[1]->accept(this);
- src = fs_reg(this, glsl_type::ivec2_type);
+ src = vgrf(glsl_type::ivec2_type);
fs_reg src2 = src;
for (int i = 0; i < 2; i++) {
- fs_reg temp = fs_reg(this, glsl_type::float_type);
+ fs_reg temp = vgrf(glsl_type::float_type);
emit(MUL(temp, this->result, fs_reg(16.0f)));
emit(MOV(src2, temp)); /* float to int */
}
mlen = 2 * reg_width;
- inst = emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, dst_x, src,
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET, dst_xy, src,
fs_reg(0u));
}
break;
/* 2. emit linterp */
- fs_reg res(this, ir->type);
+ fs_reg res = vgrf(ir->type);
this->result = res;
for (int i = 0; i < ir->type->vector_elements; i++) {
int ch = swiz ? ((*(int *)&swiz->mask) >> 2*i) & 3 : i;
- emit(FS_OPCODE_LINTERP, res,
- dst_x, dst_y,
+ emit(FS_OPCODE_LINTERP, res, dst_xy,
fs_reg(interp_reg(var->data.location, ch)));
res = offset(res, 1);
}
unsigned int operand;
fs_reg op[3], temp;
fs_inst *inst;
+ struct brw_wm_prog_key *fs_key = (struct brw_wm_prog_key *) this->key;
assert(ir->get_num_operands() <= 3);
/* Deal with the real oddball stuff first */
switch (ir->operation) {
case ir_binop_add:
+ if (devinfo->gen <= 5 && try_emit_line(ir))
+ return;
if (try_emit_mad(ir))
return;
break;
+ case ir_triop_csel:
+ ir->operands[1]->accept(this);
+ op[1] = this->result;
+ ir->operands[2]->accept(this);
+ op[2] = this->result;
+
+ emit_bool_to_cond_code(ir->operands[0]);
+
+ this->result = vgrf(ir->type);
+ inst = emit(SEL(this->result, op[1], op[2]));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ return;
+
+ case ir_unop_b2f:
+ if (devinfo->gen <= 5 && try_emit_b2f_of_comparison(ir))
+ return;
+ break;
+
case ir_unop_interpolate_at_centroid:
case ir_binop_interpolate_at_offset:
case ir_binop_interpolate_at_sample:
ir->operands[operand]->fprint(stderr);
fprintf(stderr, "\n");
}
- assert(this->result.is_valid_3src());
+ assert(this->result.file == GRF ||
+ this->result.file == UNIFORM || this->result.file == ATTR);
op[operand] = this->result;
/* Matrix expression operands should have been broken down to vector
/* Storage for our result. If our result goes into an assignment, it will
* just get copy-propagated out, so no worries.
*/
- this->result = fs_reg(this, ir->type);
+ this->result = vgrf(ir->type);
switch (ir->operation) {
case ir_unop_logic_not:
- if (ctx->Const.UniformBooleanTrue != 1) {
- emit(NOT(this->result, op[0]));
- } else {
- emit(XOR(this->result, op[0], fs_reg(1)));
- }
+ emit(NOT(this->result, op[0]));
break;
case ir_unop_neg:
op[0].negate = !op[0].negate;
case ir_unop_log:
unreachable("not reached: should be handled by ir_explog_to_explog2");
case ir_unop_sin:
- case ir_unop_sin_reduced:
emit_math(SHADER_OPCODE_SIN, this->result, op[0]);
break;
case ir_unop_cos:
- case ir_unop_cos_reduced:
emit_math(SHADER_OPCODE_COS, this->result, op[0]);
break;
case ir_unop_dFdx:
- emit(FS_OPCODE_DDX, this->result, op[0], fs_reg(BRW_DERIVATIVE_BY_HINT));
+ /* Select one of the two opcodes based on the glHint value. */
+ if (fs_key->high_quality_derivatives)
+ emit(FS_OPCODE_DDX_FINE, this->result, op[0]);
+ else
+ emit(FS_OPCODE_DDX_COARSE, this->result, op[0]);
break;
+
case ir_unop_dFdx_coarse:
- emit(FS_OPCODE_DDX, this->result, op[0], fs_reg(BRW_DERIVATIVE_COARSE));
+ emit(FS_OPCODE_DDX_COARSE, this->result, op[0]);
break;
+
case ir_unop_dFdx_fine:
- emit(FS_OPCODE_DDX, this->result, op[0], fs_reg(BRW_DERIVATIVE_FINE));
+ emit(FS_OPCODE_DDX_FINE, this->result, op[0]);
break;
+
case ir_unop_dFdy:
- emit(FS_OPCODE_DDY, this->result, op[0], fs_reg(BRW_DERIVATIVE_BY_HINT));
+ /* Select one of the two opcodes based on the glHint value. */
+ if (fs_key->high_quality_derivatives)
+ emit(FS_OPCODE_DDY_FINE, result, op[0], fs_reg(fs_key->render_to_fbo));
+ else
+ emit(FS_OPCODE_DDY_COARSE, result, op[0], fs_reg(fs_key->render_to_fbo));
break;
+
case ir_unop_dFdy_coarse:
- emit(FS_OPCODE_DDY, this->result, op[0], fs_reg(BRW_DERIVATIVE_COARSE));
+ emit(FS_OPCODE_DDY_COARSE, result, op[0], fs_reg(fs_key->render_to_fbo));
break;
+
case ir_unop_dFdy_fine:
- emit(FS_OPCODE_DDY, this->result, op[0], fs_reg(BRW_DERIVATIVE_FINE));
+ emit(FS_OPCODE_DDY_FINE, result, op[0], fs_reg(fs_key->render_to_fbo));
break;
case ir_binop_add:
unreachable("not reached: should be handled by ir_sub_to_add_neg");
case ir_binop_mul:
- if (brw->gen < 8 && ir->type->is_integer()) {
+ if (devinfo->gen < 8 && ir->type->is_integer()) {
/* For integer multiplication, the MUL uses the low 16 bits
* of one of the operands (src0 on gen6, src1 on gen7). The
* MACH accumulates in the contribution of the upper 16 bits
* of that operand.
*/
if (ir->operands[0]->is_uint16_constant()) {
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
emit(MUL(this->result, op[0], op[1]));
else
emit(MUL(this->result, op[1], op[0]));
} else if (ir->operands[1]->is_uint16_constant()) {
- if (brw->gen < 7)
+ if (devinfo->gen < 7)
emit(MUL(this->result, op[1], op[0]));
else
emit(MUL(this->result, op[0], op[1]));
} else {
- if (brw->gen >= 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
}
break;
case ir_binop_imul_high: {
- if (brw->gen == 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
*
* FINISHME: Don't use source modifiers on src1.
*/
- if (brw->gen >= 8) {
+ if (devinfo->gen >= 8) {
assert(mul->src[1].type == BRW_REGISTER_TYPE_D ||
mul->src[1].type == BRW_REGISTER_TYPE_UD);
if (mul->src[1].type == BRW_REGISTER_TYPE_D) {
mul->src[1].type = BRW_REGISTER_TYPE_W;
+ mul->src[1].stride = 2;
} else {
mul->src[1].type = BRW_REGISTER_TYPE_UW;
+ mul->src[1].stride = 2;
}
}
emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
break;
case ir_binop_carry: {
- if (brw->gen == 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
break;
}
case ir_binop_borrow: {
- if (brw->gen == 7)
+ if (devinfo->gen >= 7)
no16("SIMD16 explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(dispatch_width),
break;
}
case ir_binop_mod:
- /* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
+ /* Floating point should be lowered by MOD_TO_FLOOR in the compiler. */
assert(ir->type->is_integer());
emit_math(SHADER_OPCODE_INT_REMAINDER, this->result, op[0], op[1]);
break;
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- if (ctx->Const.UniformBooleanTrue == 1) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(ir->operands[0], &op[0]);
resolve_bool_comparison(ir->operands[1], &op[1]);
}
emit(AND(this->result, op[0], fs_reg(1)));
break;
case ir_unop_b2f:
- if (ctx->Const.UniformBooleanTrue != 1) {
- op[0].type = BRW_REGISTER_TYPE_UD;
- this->result.type = BRW_REGISTER_TYPE_UD;
- emit(AND(this->result, op[0], fs_reg(0x3f800000u)));
- this->result.type = BRW_REGISTER_TYPE_F;
- } else {
- temp = fs_reg(this, glsl_type::int_type);
- emit(AND(temp, op[0], fs_reg(1)));
- emit(MOV(this->result, temp));
+ if (devinfo->gen <= 5) {
+ resolve_bool_comparison(ir->operands[0], &op[0]);
}
+ op[0].type = BRW_REGISTER_TYPE_D;
+ this->result.type = BRW_REGISTER_TYPE_D;
+ emit(AND(this->result, op[0], fs_reg(0x3f800000u)));
+ this->result.type = BRW_REGISTER_TYPE_F;
break;
case ir_unop_f2b:
case ir_unop_trunc:
emit(RNDZ(this->result, op[0]));
break;
- case ir_unop_ceil:
- op[0].negate = !op[0].negate;
- emit(RNDD(this->result, op[0]));
- this->result.negate = true;
+ case ir_unop_ceil: {
+ fs_reg tmp = vgrf(ir->type);
+ op[0].negate = !op[0].negate;
+ emit(RNDD(tmp, op[0]));
+ tmp.negate = true;
+ emit(MOV(this->result, tmp));
+ }
break;
case ir_unop_floor:
emit(RNDD(this->result, op[0]));
emit(CBIT(this->result, op[0]));
break;
case ir_unop_find_msb:
- temp = fs_reg(this, glsl_type::uint_type);
+ temp = vgrf(glsl_type::uint_type);
emit(FBH(temp, op[0]));
/* FBH counts from the MSB side, while GLSL's findMSB() wants the count
const_uniform_block->value.u[0]);
} else {
/* The block index is not a constant. Evaluate the index expression
- * per-channel and add the base UBO index; the generator will select
- * a value from any live channel.
+ * per-channel and add the base UBO index; we have to select a value
+ * from any live channel.
*/
- surf_index = fs_reg(this, glsl_type::uint_type);
+ surf_index = vgrf(glsl_type::uint_type);
emit(ADD(surf_index, op[0],
- fs_reg(stage_prog_data->binding_table.ubo_start)))
- ->force_writemask_all = true;
+ fs_reg(stage_prog_data->binding_table.ubo_start)));
+ emit_uniformize(surf_index, surf_index);
/* Assume this may touch any UBO. It would be nice to provide
* a tighter bound, but the array information is already lowered away.
}
if (const_offset) {
- fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
+ fs_reg packed_consts = vgrf(glsl_type::float_type);
packed_consts.type = result.type;
fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
}
} else {
/* Turn the byte offset into a dword offset. */
- fs_reg base_offset = fs_reg(this, glsl_type::int_type);
+ fs_reg base_offset = vgrf(glsl_type::int_type);
emit(SHR(base_offset, op[1], fs_reg(2)));
for (int i = 0; i < ir->type->vector_elements; i++) {
break;
case ir_triop_csel:
- emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
- inst = emit(BRW_OPCODE_SEL, this->result, op[1], op[2]);
- inst->predicate = BRW_PREDICATE_NORMAL;
- break;
-
case ir_unop_interpolate_at_centroid:
case ir_binop_interpolate_at_offset:
case ir_binop_interpolate_at_sample:
unreachable("already handled above");
break;
+
+ case ir_unop_d2f:
+ case ir_unop_f2d:
+ case ir_unop_d2i:
+ case ir_unop_i2d:
+ case ir_unop_d2u:
+ case ir_unop_u2d:
+ case ir_unop_d2b:
+ case ir_unop_pack_double_2x32:
+ case ir_unop_unpack_double_2x32:
+ case ir_unop_frexp_sig:
+ case ir_unop_frexp_exp:
+ unreachable("fp64 todo");
+ break;
}
}
case GLSL_TYPE_ATOMIC_UINT:
break;
+ case GLSL_TYPE_DOUBLE:
case GLSL_TYPE_VOID:
case GLSL_TYPE_ERROR:
case GLSL_TYPE_INTERFACE:
/* If last_rhs_inst wrote a different number of components than our LHS,
* we can't safely rewrite it.
*/
- if (virtual_grf_sizes[dst.reg] != modify->regs_written)
+ if (alloc.sizes[dst.reg] != modify->regs_written)
return false;
/* Success! Rewrite the instruction. */
}
fs_inst *
-fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg dPdy,
+fs_visitor::emit_texture_gen4(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg dPdy, int grad_components,
uint32_t sampler)
{
int mlen;
mlen = 1;
if (shadow_c.file != BAD_FILE) {
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
coordinate = offset(coordinate, 1);
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present.
* the unused slots must be zeroed.
*/
- for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
+ for (int i = coord_components; i < 3; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
}
mlen += 3;
- if (ir->op == ir_tex) {
+ if (op == ir_tex) {
/* There's no plain shadow compare message, so we use shadow
* compare with a bias of 0.0.
*/
emit(MOV(fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f)));
mlen++;
- } else if (ir->op == ir_txb || ir->op == ir_txl) {
+ } else if (op == ir_txb || op == ir_txl) {
emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
mlen++;
} else {
emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
mlen++;
- } else if (ir->op == ir_tex) {
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ } else if (op == ir_tex) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
coordinate = offset(coordinate, 1);
}
/* zero the others. */
- for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
+ for (int i = coord_components; i<3; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
}
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
mlen += 3;
- } else if (ir->op == ir_txd) {
+ } else if (op == ir_txd) {
fs_reg &dPdx = lod;
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
coordinate = offset(coordinate, 1);
}
/* the slots for u and v are always present, but r is optional */
- mlen += MAX2(ir->coordinate->type->vector_elements, 2);
+ mlen += MAX2(coord_components, 2);
/* P = u, v, r
* dPdx = dudx, dvdx, drdx
* dPdx.x dPdx.y dPdx.z dPdy.x dPdy.y dPdy.z
* m5 m6 m7 m8 m9 m10
*/
- for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
+ for (int i = 0; i < grad_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdx));
dPdx = offset(dPdx, 1);
}
- mlen += MAX2(ir->lod_info.grad.dPdx->type->vector_elements, 2);
+ mlen += MAX2(grad_components, 2);
- for (int i = 0; i < ir->lod_info.grad.dPdy->type->vector_elements; i++) {
+ for (int i = 0; i < grad_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen), dPdy));
dPdy = offset(dPdy, 1);
}
- mlen += MAX2(ir->lod_info.grad.dPdy->type->vector_elements, 2);
- } else if (ir->op == ir_txs) {
+ mlen += MAX2(grad_components, 2);
+ } else if (op == ir_txs) {
/* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
simd16 = true;
emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
* instructions. We'll need to do SIMD16 here.
*/
simd16 = true;
- assert(ir->op == ir_txb || ir->op == ir_txl || ir->op == ir_txf);
+ assert(op == ir_txb || op == ir_txl || op == ir_txf);
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2, coordinate.type),
coordinate));
coordinate = offset(coordinate, 1);
/* Initialize the rest of u/v/r with 0.0. Empirically, this seems to
* be necessary for TXF (ld), but seems wise to do for all messages.
*/
- for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
+ for (int i = coord_components; i < 3; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i * 2), fs_reg(0.0f)));
}
* this weirdness around to the expected layout.
*/
orig_dst = dst;
- dst = fs_reg(GRF, virtual_grf_alloc(8),
- (brw->is_g4x ?
- brw_type_for_base_type(ir->type) :
- BRW_REGISTER_TYPE_F));
+ dst = fs_reg(GRF, alloc.allocate(8), orig_dst.type);
}
enum opcode opcode;
-
- switch (ir->op) {
+ switch (op) {
case ir_tex: opcode = SHADER_OPCODE_TEX; break;
case ir_txb: opcode = FS_OPCODE_TXB; break;
case ir_txl: opcode = SHADER_OPCODE_TXL; break;
return inst;
}
+fs_inst *
+fs_visitor::emit_texture_gen4_simd16(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int vector_elements,
+ fs_reg shadow_c, fs_reg lod,
+ uint32_t sampler)
+{
+ fs_reg message(MRF, 2, BRW_REGISTER_TYPE_F, dispatch_width);
+ bool has_lod = op == ir_txl || op == ir_txb || op == ir_txf;
+
+ if (has_lod && shadow_c.file != BAD_FILE)
+ no16("TXB and TXL with shadow comparison unsupported in SIMD16.");
+
+ if (op == ir_txd)
+ no16("textureGrad unsupported in SIMD16.");
+
+ /* Copy the coordinates. */
+ for (int i = 0; i < vector_elements; i++) {
+ emit(MOV(retype(offset(message, i), coordinate.type), coordinate));
+ coordinate = offset(coordinate, 1);
+ }
+
+ fs_reg msg_end = offset(message, vector_elements);
+
+ /* Messages other than sample and ld require all three components */
+ if (has_lod || shadow_c.file != BAD_FILE) {
+ for (int i = vector_elements; i < 3; i++) {
+ emit(MOV(offset(message, i), fs_reg(0.0f)));
+ }
+ }
+
+ if (has_lod) {
+ fs_reg msg_lod = retype(offset(message, 3), op == ir_txf ?
+ BRW_REGISTER_TYPE_UD : BRW_REGISTER_TYPE_F);
+ emit(MOV(msg_lod, lod));
+ msg_end = offset(msg_lod, 1);
+ }
+
+ if (shadow_c.file != BAD_FILE) {
+ fs_reg msg_ref = offset(message, 3 + has_lod);
+ emit(MOV(msg_ref, shadow_c));
+ msg_end = offset(msg_ref, 1);
+ }
+
+ enum opcode opcode;
+ switch (op) {
+ case ir_tex: opcode = SHADER_OPCODE_TEX; break;
+ case ir_txb: opcode = FS_OPCODE_TXB; break;
+ case ir_txd: opcode = SHADER_OPCODE_TXD; break;
+ case ir_txl: opcode = SHADER_OPCODE_TXL; break;
+ case ir_txs: opcode = SHADER_OPCODE_TXS; break;
+ case ir_txf: opcode = SHADER_OPCODE_TXF; break;
+ default: unreachable("not reached");
+ }
+
+ fs_inst *inst = emit(opcode, dst, reg_undef, fs_reg(sampler));
+ inst->base_mrf = message.reg - 1;
+ inst->mlen = msg_end.reg - inst->base_mrf;
+ inst->header_present = true;
+ inst->regs_written = 8;
+
+ return inst;
+}
+
/* gen5's sampler has slots for u, v, r, array index, then optional
* parameters like shadow comparitor or LOD bias. If optional
* parameters aren't present, those base slots are optional and don't
* surprising in the disassembly.
*/
fs_inst *
-fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg lod2,
+fs_visitor::emit_texture_gen5(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int vector_elements,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg lod2, int grad_components,
fs_reg sample_index, uint32_t sampler,
bool has_offset)
{
int reg_width = dispatch_width / 8;
bool header_present = false;
- const int vector_elements =
- ir->coordinate ? ir->coordinate->type->vector_elements : 0;
fs_reg message(MRF, 2, BRW_REGISTER_TYPE_F, dispatch_width);
fs_reg msg_coords = message;
}
enum opcode opcode;
- switch (ir->op) {
+ switch (op) {
case ir_tex:
opcode = SHADER_OPCODE_TEX;
break;
* - dPdx.x dPdy.x dPdx.y dPdy.y dPdx.z dPdy.z
*/
msg_end = msg_lod;
- for (int i = 0; i < ir->lod_info.grad.dPdx->type->vector_elements; i++) {
+ for (int i = 0; i < grad_components; i++) {
emit(MOV(msg_end, lod));
lod = offset(lod, 1);
msg_end = offset(msg_end, 1);
}
static bool
-is_high_sampler(struct brw_context *brw, fs_reg sampler)
+is_high_sampler(const struct brw_device_info *devinfo, fs_reg sampler)
{
- if (brw->gen < 8 && !brw->is_haswell)
+ if (devinfo->gen < 8 && !devinfo->is_haswell)
return false;
return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
}
fs_inst *
-fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg lod2,
+fs_visitor::emit_texture_gen7(ir_texture_opcode op, fs_reg dst,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg lod2, int grad_components,
fs_reg sample_index, fs_reg mcs, fs_reg sampler,
fs_reg offset_value)
{
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, MAX_SAMPLER_MESSAGE_SIZE);
for (int i = 0; i < MAX_SAMPLER_MESSAGE_SIZE; i++) {
- sources[i] = fs_reg(this, glsl_type::float_type);
+ sources[i] = vgrf(glsl_type::float_type);
}
int length = 0;
- if (ir->op == ir_tg4 || offset_value.file != BAD_FILE ||
- is_high_sampler(brw, sampler)) {
+ if (op == ir_tg4 || offset_value.file != BAD_FILE ||
+ is_high_sampler(devinfo, sampler)) {
/* For general texture offsets (no txf workaround), we need a header to
* put them in. Note that for SIMD16 we're making space for two actual
* hardware registers here, so the emit will have to fix up for this.
* need to offset the Sampler State Pointer in the header.
*/
header_present = true;
- sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
+ sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
length++;
}
offset_value.file != BAD_FILE && offset_value.file != IMM;
bool coordinate_done = false;
+ /* The sampler can only meaningfully compute LOD for fragment shader
+ * messages. For all other stages, we change the opcode to ir_txl and
+ * hardcode the LOD to 0.
+ */
+ if (stage != MESA_SHADER_FRAGMENT && op == ir_tex) {
+ op = ir_txl;
+ lod = fs_reg(0.0f);
+ }
+
/* Set up the LOD info */
- switch (ir->op) {
+ switch (op) {
case ir_tex:
case ir_lod:
break;
/* Load dPdx and the coordinate together:
* [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
*/
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(sources[length], coordinate));
coordinate = offset(coordinate, 1);
length++;
/* For cube map array, the coordinate is (u,v,r,ai) but there are
* only derivatives for (u, v, r).
*/
- if (i < ir->lod_info.grad.dPdx->type->vector_elements) {
+ if (i < grad_components) {
emit(MOV(sources[length], lod));
lod = offset(lod, 1);
length++;
length++;
break;
case ir_txf:
- /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
+ /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r.
+ * On Gen9 they are u, v, lod, r
+ */
+
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
coordinate = offset(coordinate, 1);
length++;
+ if (devinfo->gen >= 9) {
+ if (coord_components >= 2) {
+ emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
+ coordinate = offset(coordinate, 1);
+ }
+ length++;
+ }
+
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), lod));
length++;
- for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = devinfo->gen >= 9 ? 2 : 1; i < coord_components; i++) {
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
coordinate = offset(coordinate, 1);
length++;
/* there is no offsetting for this message; just copy in the integer
* texture coordinates
*/
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(retype(sources[length], BRW_REGISTER_TYPE_D), coordinate));
coordinate = offset(coordinate, 1);
length++;
length++;
}
- if (ir->coordinate->type->vector_elements == 3) { /* r if present */
+ if (coord_components == 3) { /* r if present */
emit(MOV(sources[length], coordinate));
coordinate = offset(coordinate, 1);
length++;
}
/* Set up the coordinate (except for cases where it was done above) */
- if (ir->coordinate && !coordinate_done) {
- for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ if (!coordinate_done) {
+ for (int i = 0; i < coord_components; i++) {
emit(MOV(sources[length], coordinate));
coordinate = offset(coordinate, 1);
length++;
else
mlen = length * reg_width;
- fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
+ fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
BRW_REGISTER_TYPE_F);
emit(LOAD_PAYLOAD(src_payload, sources, length));
/* Generate the SEND */
enum opcode opcode;
- switch (ir->op) {
+ switch (op) {
case ir_tex: opcode = SHADER_OPCODE_TEX; break;
case ir_txb: opcode = FS_OPCODE_TXB; break;
case ir_txl: opcode = SHADER_OPCODE_TXL; break;
}
fs_reg
-fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg coordinate,
+fs_visitor::rescale_texcoord(fs_reg coordinate, int coord_components,
bool is_rect, uint32_t sampler, int texunit)
{
fs_inst *inst = NULL;
bool needs_gl_clamp = true;
fs_reg scale_x, scale_y;
- const struct brw_sampler_prog_key_data *tex =
- (stage == MESA_SHADER_FRAGMENT) ?
- &((brw_wm_prog_key*) this->key)->tex : NULL;
- assert(tex);
/* The 965 requires the EU to do the normalization of GL rectangle
* texture coordinates. We use the program parameter state
* tracking to get the scaling factor.
*/
if (is_rect &&
- (brw->gen < 6 ||
- (brw->gen >= 6 && (tex->gl_clamp_mask[0] & (1 << sampler) ||
- tex->gl_clamp_mask[1] & (1 << sampler))))) {
+ (devinfo->gen < 6 ||
+ (devinfo->gen >= 6 && (key_tex->gl_clamp_mask[0] & (1 << sampler) ||
+ key_tex->gl_clamp_mask[1] & (1 << sampler))))) {
struct gl_program_parameter_list *params = prog->Parameters;
int tokens[STATE_LENGTH] = {
STATE_INTERNAL,
* texture coordinates. We use the program parameter state
* tracking to get the scaling factor.
*/
- if (brw->gen < 6 && is_rect) {
- fs_reg dst = fs_reg(this, ir->coordinate->type);
+ if (devinfo->gen < 6 && is_rect) {
+ fs_reg dst = fs_reg(GRF, alloc.allocate(coord_components));
fs_reg src = coordinate;
coordinate = dst;
needs_gl_clamp = false;
for (int i = 0; i < 2; i++) {
- if (tex->gl_clamp_mask[i] & (1 << sampler)) {
+ if (key_tex->gl_clamp_mask[i] & (1 << sampler)) {
fs_reg chan = coordinate;
chan = offset(chan, i);
inst = emit(BRW_OPCODE_SEL, chan, chan, fs_reg(0.0f));
- inst->conditional_mod = BRW_CONDITIONAL_G;
+ inst->conditional_mod = BRW_CONDITIONAL_GE;
/* Our parameter comes in as 1.0/width or 1.0/height,
* because that's what people normally want for doing
* for clamping, but we don't care enough to make a new
* parameter type, so just invert back.
*/
- fs_reg limit = fs_reg(this, glsl_type::float_type);
+ fs_reg limit = vgrf(glsl_type::float_type);
emit(MOV(limit, i == 0 ? scale_x : scale_y));
emit(SHADER_OPCODE_RCP, limit, limit);
}
}
- if (ir->coordinate && needs_gl_clamp) {
- for (unsigned int i = 0;
- i < MIN2(ir->coordinate->type->vector_elements, 3); i++) {
- if (tex->gl_clamp_mask[i] & (1 << sampler)) {
+ if (coord_components > 0 && needs_gl_clamp) {
+ for (int i = 0; i < MIN2(coord_components, 3); i++) {
+ if (key_tex->gl_clamp_mask[i] & (1 << sampler)) {
fs_reg chan = coordinate;
chan = offset(chan, i);
/* Sample from the MCS surface attached to this multisample texture. */
fs_reg
-fs_visitor::emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler)
+fs_visitor::emit_mcs_fetch(fs_reg coordinate, int components, fs_reg sampler)
{
int reg_width = dispatch_width / 8;
- int length = ir->coordinate->type->vector_elements;
- fs_reg payload = fs_reg(GRF, virtual_grf_alloc(length * reg_width),
+ fs_reg payload = fs_reg(GRF, alloc.allocate(components * reg_width),
BRW_REGISTER_TYPE_F);
- fs_reg dest = fs_reg(this, glsl_type::uvec4_type);
- fs_reg *sources = ralloc_array(mem_ctx, fs_reg, length);
+ fs_reg dest = vgrf(glsl_type::uvec4_type);
+ fs_reg *sources = ralloc_array(mem_ctx, fs_reg, components);
/* parameters are: u, v, r; missing parameters are treated as zero */
- for (int i = 0; i < length; i++) {
- sources[i] = fs_reg(this, glsl_type::float_type);
+ for (int i = 0; i < components; i++) {
+ sources[i] = vgrf(glsl_type::float_type);
emit(MOV(retype(sources[i], BRW_REGISTER_TYPE_D), coordinate));
coordinate = offset(coordinate, 1);
}
- emit(LOAD_PAYLOAD(payload, sources, length));
+ emit(LOAD_PAYLOAD(payload, sources, components));
fs_inst *inst = emit(SHADER_OPCODE_TXF_MCS, dest, payload, sampler);
inst->base_mrf = -1;
- inst->mlen = length * reg_width;
+ inst->mlen = components * reg_width;
inst->header_present = false;
inst->regs_written = 4 * reg_width; /* we only care about one reg of
* response, but the sampler always
}
void
-fs_visitor::visit(ir_texture *ir)
+fs_visitor::emit_texture(ir_texture_opcode op,
+ const glsl_type *dest_type,
+ fs_reg coordinate, int coord_components,
+ fs_reg shadow_c,
+ fs_reg lod, fs_reg lod2, int grad_components,
+ fs_reg sample_index,
+ fs_reg offset_value,
+ fs_reg mcs,
+ int gather_component,
+ bool is_cube_array,
+ bool is_rect,
+ uint32_t sampler,
+ fs_reg sampler_reg, int texunit)
{
- const struct brw_sampler_prog_key_data *tex =
- (stage == MESA_SHADER_FRAGMENT) ?
- &((brw_wm_prog_key*) this->key)->tex : NULL;
- assert(tex);
fs_inst *inst = NULL;
+ if (op == ir_tg4) {
+ /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
+ * emitting anything other than setting up the constant result.
+ */
+ int swiz = GET_SWZ(key_tex->swizzles[sampler], gather_component);
+ if (swiz == SWIZZLE_ZERO || swiz == SWIZZLE_ONE) {
+
+ fs_reg res = vgrf(glsl_type::vec4_type);
+ this->result = res;
+
+ for (int i=0; i<4; i++) {
+ emit(MOV(res, fs_reg(swiz == SWIZZLE_ZERO ? 0.0f : 1.0f)));
+ res = offset(res, 1);
+ }
+ return;
+ }
+ }
+
+ if (coordinate.file != BAD_FILE) {
+ /* FINISHME: Texture coordinate rescaling doesn't work with non-constant
+ * samplers. This should only be a problem with GL_CLAMP on Gen7.
+ */
+ coordinate = rescale_texcoord(coordinate, coord_components, is_rect,
+ sampler, texunit);
+ }
+
+ /* Writemasking doesn't eliminate channels on SIMD8 texture
+ * samples, so don't worry about them.
+ */
+ fs_reg dst = vgrf(glsl_type::get_instance(dest_type->base_type, 4, 1));
+
+ if (devinfo->gen >= 7) {
+ inst = emit_texture_gen7(op, dst, coordinate, coord_components,
+ shadow_c, lod, lod2, grad_components,
+ sample_index, mcs, sampler_reg,
+ offset_value);
+ } else if (devinfo->gen >= 5) {
+ inst = emit_texture_gen5(op, dst, coordinate, coord_components,
+ shadow_c, lod, lod2, grad_components,
+ sample_index, sampler,
+ offset_value.file != BAD_FILE);
+ } else if (dispatch_width == 16) {
+ inst = emit_texture_gen4_simd16(op, dst, coordinate, coord_components,
+ shadow_c, lod, sampler);
+ } else {
+ inst = emit_texture_gen4(op, dst, coordinate, coord_components,
+ shadow_c, lod, lod2, grad_components,
+ sampler);
+ }
+
+ if (shadow_c.file != BAD_FILE)
+ inst->shadow_compare = true;
+
+ if (offset_value.file == IMM)
+ inst->offset = offset_value.fixed_hw_reg.dw1.ud;
+
+ if (op == ir_tg4) {
+ inst->offset |=
+ gather_channel(gather_component, sampler) << 16; /* M0.2:16-17 */
+
+ if (devinfo->gen == 6)
+ emit_gen6_gather_wa(key_tex->gen6_gather_wa[sampler], dst);
+ }
+
+ /* fixup #layers for cube map arrays */
+ if (op == ir_txs && is_cube_array) {
+ fs_reg depth = offset(dst, 2);
+ fs_reg fixed_depth = vgrf(glsl_type::int_type);
+ emit_math(SHADER_OPCODE_INT_QUOTIENT, fixed_depth, depth, fs_reg(6));
+
+ fs_reg *fixed_payload = ralloc_array(mem_ctx, fs_reg, inst->regs_written);
+ int components = inst->regs_written / (dst.width / 8);
+ for (int i = 0; i < components; i++) {
+ if (i == 2) {
+ fixed_payload[i] = fixed_depth;
+ } else {
+ fixed_payload[i] = offset(dst, i);
+ }
+ }
+ emit(LOAD_PAYLOAD(dst, fixed_payload, components));
+ }
+
+ swizzle_result(op, dest_type->vector_elements, dst, sampler);
+}
+
+void
+fs_visitor::visit(ir_texture *ir)
+{
uint32_t sampler =
_mesa_get_sampler_uniform_value(ir->sampler, shader_prog, prog);
->array->type->array_size();
uint32_t max_used = sampler + array_size - 1;
- if (ir->op == ir_tg4 && brw->gen < 8) {
+ if (ir->op == ir_tg4 && devinfo->gen < 8) {
max_used += stage_prog_data->binding_table.gather_texture_start;
} else {
max_used += stage_prog_data->binding_table.texture_start;
/* Emit code to evaluate the actual indexing expression */
nonconst_sampler_index->accept(this);
- fs_reg temp(this, glsl_type::uint_type);
+ fs_reg temp = vgrf(glsl_type::uint_type);
emit(ADD(temp, this->result, fs_reg(sampler)))
->force_writemask_all = true;
sampler_reg = temp;
*/
int texunit = prog->SamplerUnits[sampler];
- if (ir->op == ir_tg4) {
- /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
- * emitting anything other than setting up the constant result.
- */
- ir_constant *chan = ir->lod_info.component->as_constant();
- int swiz = GET_SWZ(tex->swizzles[sampler], chan->value.i[0]);
- if (swiz == SWIZZLE_ZERO || swiz == SWIZZLE_ONE) {
-
- fs_reg res = fs_reg(this, glsl_type::vec4_type);
- this->result = res;
-
- for (int i=0; i<4; i++) {
- emit(MOV(res, fs_reg(swiz == SWIZZLE_ZERO ? 0.0f : 1.0f)));
- res = offset(res, 1);
- }
- return;
- }
- }
-
/* Should be lowered by do_lower_texture_projection */
assert(!ir->projector);
* generating these values may involve SEND messages that need the MRFs.
*/
fs_reg coordinate;
+ int coord_components = 0;
if (ir->coordinate) {
+ coord_components = ir->coordinate->type->vector_elements;
ir->coordinate->accept(this);
-
- coordinate = rescale_texcoord(ir, this->result,
- ir->sampler->type->sampler_dimensionality ==
- GLSL_SAMPLER_DIM_RECT,
- sampler, texunit);
+ coordinate = this->result;
}
fs_reg shadow_comparitor;
* use offset_value.file to distinguish between no offset, a constant
* offset, and a non-constant offset.
*/
- offset_value = fs_reg(brw_texture_offset(ctx, const_offset));
+ offset_value =
+ fs_reg(brw_texture_offset(const_offset->value.i,
+ const_offset->type->vector_elements));
} else {
ir->offset->accept(this);
offset_value = this->result;
}
fs_reg lod, lod2, sample_index, mcs;
+ int grad_components = 0;
switch (ir->op) {
case ir_tex:
case ir_lod:
ir->lod_info.grad.dPdy->accept(this);
lod2 = this->result;
+
+ grad_components = ir->lod_info.grad.dPdx->type->vector_elements;
break;
case ir_txf:
case ir_txl:
ir->lod_info.sample_index->accept(this);
sample_index = this->result;
- if (brw->gen >= 7 && tex->compressed_multisample_layout_mask & (1<<sampler))
- mcs = emit_mcs_fetch(ir, coordinate, sampler_reg);
- else
+ if (devinfo->gen >= 7 &&
+ key_tex->compressed_multisample_layout_mask & (1 << sampler)) {
+ mcs = emit_mcs_fetch(coordinate, ir->coordinate->type->vector_elements,
+ sampler_reg);
+ } else {
mcs = fs_reg(0u);
+ }
break;
default:
unreachable("Unrecognized texture opcode");
};
- /* Writemasking doesn't eliminate channels on SIMD8 texture
- * samples, so don't worry about them.
- */
- fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
-
- if (brw->gen >= 7) {
- inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
- lod, lod2, sample_index, mcs, sampler_reg,
- offset_value);
- } else if (brw->gen >= 5) {
- inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
- lod, lod2, sample_index, sampler,
- ir->offset != NULL);
- } else {
- inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
- lod, lod2, sampler);
- }
-
- if (offset_value.file == IMM)
- inst->texture_offset = offset_value.fixed_hw_reg.dw1.ud;
-
+ int gather_component = 0;
if (ir->op == ir_tg4)
- inst->texture_offset |= gather_channel(ir, sampler) << 16; // M0.2:16-17
+ gather_component = ir->lod_info.component->as_constant()->value.i[0];
- if (ir->shadow_comparitor)
- inst->shadow_compare = true;
+ bool is_rect =
+ ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_RECT;
- /* fixup #layers for cube map arrays */
- if (ir->op == ir_txs) {
- glsl_type const *type = ir->sampler->type;
- if (type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
- type->sampler_array) {
- fs_reg depth = offset(dst, 2);
- fs_reg fixed_depth = fs_reg(this, glsl_type::int_type);
- emit_math(SHADER_OPCODE_INT_QUOTIENT, fixed_depth, depth, fs_reg(6));
-
- fs_reg *fixed_payload = ralloc_array(mem_ctx, fs_reg, inst->regs_written);
- int components = inst->regs_written / (dst.width / 8);
- for (int i = 0; i < components; i++) {
- if (i == 2) {
- fixed_payload[i] = fixed_depth;
- } else {
- fixed_payload[i] = offset(dst, i);
- }
- }
- emit(LOAD_PAYLOAD(dst, fixed_payload, components));
- }
- }
-
- if (brw->gen == 6 && ir->op == ir_tg4) {
- emit_gen6_gather_wa(tex->gen6_gather_wa[sampler], dst);
- }
+ bool is_cube_array =
+ ir->sampler->type->sampler_dimensionality == GLSL_SAMPLER_DIM_CUBE &&
+ ir->sampler->type->sampler_array;
- swizzle_result(ir, dst, sampler);
+ emit_texture(ir->op, ir->type, coordinate, coord_components,
+ shadow_comparitor, lod, lod2, grad_components,
+ sample_index, offset_value, mcs,
+ gather_component, is_cube_array, is_rect, sampler,
+ sampler_reg, texunit);
}
/**
* Set up the gather channel based on the swizzle, for gather4.
*/
uint32_t
-fs_visitor::gather_channel(ir_texture *ir, uint32_t sampler)
-{
- const struct brw_sampler_prog_key_data *tex =
- (stage == MESA_SHADER_FRAGMENT) ?
- &((brw_wm_prog_key*) this->key)->tex : NULL;
- assert(tex);
- ir_constant *chan = ir->lod_info.component->as_constant();
- int swiz = GET_SWZ(tex->swizzles[sampler], chan->value.i[0]);
+fs_visitor::gather_channel(int orig_chan, uint32_t sampler)
+{
+ int swiz = GET_SWZ(key_tex->swizzles[sampler], orig_chan);
switch (swiz) {
case SWIZZLE_X: return 0;
case SWIZZLE_Y:
/* gather4 sampler is broken for green channel on RG32F --
* we must ask for blue instead.
*/
- if (tex->gather_channel_quirk_mask & (1<<sampler))
+ if (key_tex->gather_channel_quirk_mask & (1 << sampler))
return 2;
return 1;
case SWIZZLE_Z: return 2;
* EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
*/
void
-fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler)
+fs_visitor::swizzle_result(ir_texture_opcode op, int dest_components,
+ fs_reg orig_val, uint32_t sampler)
{
- if (ir->op == ir_query_levels) {
+ if (op == ir_query_levels) {
/* # levels is in .w */
this->result = offset(orig_val, 3);
return;
/* txs,lod don't actually sample the texture, so swizzling the result
* makes no sense.
*/
- if (ir->op == ir_txs || ir->op == ir_lod || ir->op == ir_tg4)
+ if (op == ir_txs || op == ir_lod || op == ir_tg4)
return;
- const struct brw_sampler_prog_key_data *tex =
- (stage == MESA_SHADER_FRAGMENT) ?
- &((brw_wm_prog_key*) this->key)->tex : NULL;
- assert(tex);
-
- if (ir->type == glsl_type::float_type) {
+ if (dest_components == 1) {
/* Ignore DEPTH_TEXTURE_MODE swizzling. */
- assert(ir->sampler->type->sampler_shadow);
- } else if (tex->swizzles[sampler] != SWIZZLE_NOOP) {
- fs_reg swizzled_result = fs_reg(this, glsl_type::vec4_type);
+ } else if (key_tex->swizzles[sampler] != SWIZZLE_NOOP) {
+ fs_reg swizzled_result = vgrf(glsl_type::vec4_type);
+ swizzled_result.type = orig_val.type;
for (int i = 0; i < 4; i++) {
- int swiz = GET_SWZ(tex->swizzles[sampler], i);
+ int swiz = GET_SWZ(key_tex->swizzles[sampler], i);
fs_reg l = swizzled_result;
l = offset(l, i);
emit(MOV(l, fs_reg(1.0f)));
} else {
emit(MOV(l, offset(orig_val,
- GET_SWZ(tex->swizzles[sampler], i))));
+ GET_SWZ(key_tex->swizzles[sampler], i))));
}
}
this->result = swizzled_result;
return;
}
- fs_reg result = fs_reg(this, ir->type);
+ fs_reg result = vgrf(ir->type);
this->result = result;
for (unsigned int i = 0; i < ir->type->vector_elements; i++) {
void
fs_visitor::visit(ir_discard *ir)
{
- assert(ir->condition == NULL); /* FINISHME */
-
/* We track our discarded pixels in f0.1. By predicating on it, we can
- * update just the flag bits that aren't yet discarded. By emitting a
- * CMP of g0 != g0, all our currently executing channels will get turned
- * off.
+ * update just the flag bits that aren't yet discarded. If there's no
+ * condition, we emit a CMP of g0 != g0, so all currently executing
+ * channels will get turned off.
*/
- fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
- BRW_REGISTER_TYPE_UW));
- fs_inst *cmp = emit(CMP(reg_null_f, some_reg, some_reg,
- BRW_CONDITIONAL_NZ));
+ fs_inst *cmp;
+ if (ir->condition) {
+ emit_bool_to_cond_code(ir->condition);
+ cmp = (fs_inst *) this->instructions.get_tail();
+ cmp->conditional_mod = brw_negate_cmod(cmp->conditional_mod);
+ } else {
+ fs_reg some_reg = fs_reg(retype(brw_vec8_grf(0, 0),
+ BRW_REGISTER_TYPE_UW));
+ cmp = emit(CMP(reg_null_f, some_reg, some_reg, BRW_CONDITIONAL_NZ));
+ }
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
- if (brw->gen >= 6) {
- /* For performance, after a discard, jump to the end of the shader.
- * Only jump if all relevant channels have been discarded.
- */
- fs_inst *discard_jump = emit(FS_OPCODE_DISCARD_JUMP);
- discard_jump->flag_subreg = 1;
-
- discard_jump->predicate = (dispatch_width == 8)
- ? BRW_PREDICATE_ALIGN1_ANY8H
- : BRW_PREDICATE_ALIGN1_ANY16H;
- discard_jump->predicate_inverse = true;
+ if (devinfo->gen >= 6) {
+ emit_discard_jump();
}
}
* Make reg constant so that it doesn't get accidentally modified along the
* way. Yes, I actually had this problem. :(
*/
- const fs_reg reg(this, ir->type);
+ const fs_reg reg = vgrf(ir->type);
fs_reg dst_reg = reg;
if (ir->type->is_array()) {
emit(MOV(dst_reg, fs_reg(ir->value.i[i])));
break;
case GLSL_TYPE_BOOL:
- emit(MOV(dst_reg,
- fs_reg(ir->value.b[i] != 0 ? ctx->Const.UniformBooleanTrue
- : 0)));
+ emit(MOV(dst_reg, fs_reg(ir->value.b[i] != 0 ? ~0 : 0)));
break;
default:
unreachable("Non-float/uint/int/bool constant");
}
fs_reg op[3];
- fs_inst *inst;
assert(expr->get_num_operands() <= 3);
for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
resolve_ud_negate(&op[i]);
}
+ emit_bool_to_cond_code_of_reg(expr, op);
+}
+
+void
+fs_visitor::emit_bool_to_cond_code_of_reg(ir_expression *expr, fs_reg op[3])
+{
+ fs_inst *inst;
+
switch (expr->operation) {
case ir_unop_logic_not:
inst = emit(AND(reg_null_d, op[0], fs_reg(1)));
break;
case ir_binop_logic_xor:
- if (ctx->Const.UniformBooleanTrue == 1) {
- fs_reg dst = fs_reg(this, glsl_type::uint_type);
- emit(XOR(dst, op[0], op[1]));
- inst = emit(AND(reg_null_d, dst, fs_reg(1)));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ if (devinfo->gen <= 5) {
+ fs_reg temp = vgrf(expr->type);
+ emit(XOR(temp, op[0], op[1]));
+ inst = emit(AND(reg_null_d, temp, fs_reg(1)));
} else {
inst = emit(XOR(reg_null_d, op[0], op[1]));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
}
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
break;
case ir_binop_logic_or:
- if (ctx->Const.UniformBooleanTrue == 1) {
- fs_reg dst = fs_reg(this, glsl_type::uint_type);
- emit(OR(dst, op[0], op[1]));
- inst = emit(AND(reg_null_d, dst, fs_reg(1)));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ if (devinfo->gen <= 5) {
+ fs_reg temp = vgrf(expr->type);
+ emit(OR(temp, op[0], op[1]));
+ inst = emit(AND(reg_null_d, temp, fs_reg(1)));
} else {
inst = emit(OR(reg_null_d, op[0], op[1]));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
}
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
break;
case ir_binop_logic_and:
- if (ctx->Const.UniformBooleanTrue == 1) {
- fs_reg dst = fs_reg(this, glsl_type::uint_type);
- emit(AND(dst, op[0], op[1]));
- inst = emit(AND(reg_null_d, dst, fs_reg(1)));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
+ if (devinfo->gen <= 5) {
+ fs_reg temp = vgrf(expr->type);
+ emit(AND(temp, op[0], op[1]));
+ inst = emit(AND(reg_null_d, temp, fs_reg(1)));
} else {
inst = emit(AND(reg_null_d, op[0], op[1]));
- inst->conditional_mod = BRW_CONDITIONAL_NZ;
}
+ inst->conditional_mod = BRW_CONDITIONAL_NZ;
break;
case ir_unop_f2b:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_f, op[0]));
break;
case ir_unop_i2b:
- if (brw->gen >= 6) {
+ if (devinfo->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_d, op[0]));
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- if (ctx->Const.UniformBooleanTrue == 1) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
inst->conditional_mod = BRW_CONDITIONAL_NZ;
/* Select which boolean to return. */
- fs_reg temp(this, expr->operands[1]->type);
+ fs_reg temp = vgrf(expr->operands[1]->type);
inst = emit(SEL(temp, op[1], op[2]));
inst->predicate = BRW_PREDICATE_NORMAL;
return;
case ir_binop_logic_or:
- temp = fs_reg(this, glsl_type::bool_type);
+ temp = vgrf(glsl_type::bool_type);
emit(OR(temp, op[0], op[1]));
emit(IF(temp, fs_reg(0), BRW_CONDITIONAL_NZ));
return;
case ir_binop_logic_and:
- temp = fs_reg(this, glsl_type::bool_type);
+ temp = vgrf(glsl_type::bool_type);
emit(AND(temp, op[0], op[1]));
emit(IF(temp, fs_reg(0), BRW_CONDITIONAL_NZ));
return;
case ir_binop_all_equal:
case ir_binop_nequal:
case ir_binop_any_nequal:
- if (ctx->Const.UniformBooleanTrue == 1) {
+ if (devinfo->gen <= 5) {
resolve_bool_comparison(expr->operands[0], &op[0]);
resolve_bool_comparison(expr->operands[1], &op[1]);
}
inst->conditional_mod = BRW_CONDITIONAL_NZ;
/* Select which boolean to use as the result. */
- fs_reg temp(this, expr->operands[1]->type);
+ fs_reg temp = vgrf(expr->operands[1]->type);
inst = emit(SEL(temp, op[1], op[2]));
inst->predicate = BRW_PREDICATE_NORMAL;
emit(IF(this->result, fs_reg(0), BRW_CONDITIONAL_NZ));
}
+bool
+fs_visitor::try_opt_frontfacing_ternary(ir_if *ir)
+{
+ ir_dereference_variable *deref = ir->condition->as_dereference_variable();
+ if (!deref || strcmp(deref->var->name, "gl_FrontFacing") != 0)
+ return false;
+
+ if (ir->then_instructions.length() != 1 ||
+ ir->else_instructions.length() != 1)
+ return false;
+
+ ir_assignment *then_assign =
+ ((ir_instruction *)ir->then_instructions.head)->as_assignment();
+ ir_assignment *else_assign =
+ ((ir_instruction *)ir->else_instructions.head)->as_assignment();
+
+ if (!then_assign || then_assign->condition ||
+ !else_assign || else_assign->condition ||
+ then_assign->write_mask != else_assign->write_mask ||
+ !then_assign->lhs->equals(else_assign->lhs))
+ return false;
+
+ ir_constant *then_rhs = then_assign->rhs->as_constant();
+ ir_constant *else_rhs = else_assign->rhs->as_constant();
+
+ if (!then_rhs || !else_rhs)
+ return false;
+
+ if (then_rhs->type->base_type != GLSL_TYPE_FLOAT)
+ return false;
+
+ if ((then_rhs->is_one() && else_rhs->is_negative_one()) ||
+ (else_rhs->is_one() && then_rhs->is_negative_one())) {
+ then_assign->lhs->accept(this);
+ fs_reg dst = this->result;
+ dst.type = BRW_REGISTER_TYPE_D;
+ fs_reg tmp = vgrf(glsl_type::int_type);
+
+ if (devinfo->gen >= 6) {
+ /* Bit 15 of g0.0 is 0 if the polygon is front facing. */
+ fs_reg g0 = fs_reg(retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_W));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp.1<2>W g0.0<0,1,0>W 0x00003f80W
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g0.0<0,1,0>W for (gl_FrontFacing ? -1.0 : 1.0).
+ */
+
+ if (then_rhs->is_negative_one()) {
+ assert(else_rhs->is_one());
+ g0.negate = true;
+ }
+
+ tmp.type = BRW_REGISTER_TYPE_W;
+ tmp.subreg_offset = 2;
+ tmp.stride = 2;
+
+ fs_inst *or_inst = emit(OR(tmp, g0, fs_reg(0x3f80)));
+ or_inst->src[1].type = BRW_REGISTER_TYPE_UW;
+
+ tmp.type = BRW_REGISTER_TYPE_D;
+ tmp.subreg_offset = 0;
+ tmp.stride = 1;
+ } else {
+ /* Bit 31 of g1.6 is 0 if the polygon is front facing. */
+ fs_reg g1_6 = fs_reg(retype(brw_vec1_grf(1, 6), BRW_REGISTER_TYPE_D));
+
+ /* For (gl_FrontFacing ? 1.0 : -1.0), emit:
+ *
+ * or(8) tmp<1>D g1.6<0,1,0>D 0x3f800000D
+ * and(8) dst<1>D tmp<8,8,1>D 0xbf800000D
+ *
+ * and negate g1.6<0,1,0>D for (gl_FrontFacing ? -1.0 : 1.0).
+ */
+
+ if (then_rhs->is_negative_one()) {
+ assert(else_rhs->is_one());
+ g1_6.negate = true;
+ }
+
+ emit(OR(tmp, g1_6, fs_reg(0x3f800000)));
+ }
+ emit(AND(dst, tmp, fs_reg(0xbf800000)));
+ return true;
+ }
+
+ return false;
+}
+
/**
* Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
*
*
* If src0 is an immediate value, we promote it to a temporary GRF.
*/
-void
+bool
fs_visitor::try_replace_with_sel()
{
fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
fs_inst *match = (fs_inst *) endif_inst->prev;
for (int i = 0; i < 4; i++) {
if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
- return;
+ return false;
match = (fs_inst *) match->prev;
}
*/
fs_reg src0(then_mov->src[0]);
if (src0.file == IMM) {
- src0 = fs_reg(this, glsl_type::float_type);
+ src0 = vgrf(glsl_type::float_type);
src0.type = then_mov->src[0].type;
emit(MOV(src0, then_mov->src[0]));
}
sel->predicate = if_inst->predicate;
sel->predicate_inverse = if_inst->predicate_inverse;
}
+
+ return true;
}
+
+ return false;
}
void
fs_visitor::visit(ir_if *ir)
{
- if (brw->gen < 6) {
- no16("Can't support (non-uniform) control flow on SIMD16\n");
- }
+ if (try_opt_frontfacing_ternary(ir))
+ return;
/* Don't point the annotation at the if statement, because then it plus
* the then and else blocks get printed.
*/
this->base_ir = ir->condition;
- if (brw->gen == 6) {
+ if (devinfo->gen == 6) {
emit_if_gen6(ir);
} else {
emit_bool_to_cond_code(ir->condition);
emit(BRW_OPCODE_ENDIF);
- try_replace_with_sel();
+ if (!try_replace_with_sel() && devinfo->gen < 6) {
+ no16("Can't support (non-uniform) control flow on SIMD16\n");
+ }
}
void
fs_visitor::visit(ir_loop *ir)
{
- if (brw->gen < 6) {
+ if (devinfo->gen < 6) {
no16("Can't support (non-uniform) control flow on SIMD16\n");
}
location->data.binding);
/* Calculate the surface offset */
- fs_reg offset(this, glsl_type::uint_type);
+ fs_reg offset = vgrf(glsl_type::uint_type);
ir_dereference_array *deref_array = deref->as_dereference_array();
if (deref_array) {
deref_array->array_index->accept(this);
- fs_reg tmp(this, glsl_type::uint_type);
+ fs_reg tmp = vgrf(glsl_type::uint_type);
emit(MUL(tmp, this->result, fs_reg(ATOMIC_COUNTER_SIZE)));
emit(ADD(offset, tmp, fs_reg(location->data.atomic.offset)));
} else {
fs_reg dst, fs_reg offset, fs_reg src0,
fs_reg src1)
{
- bool uses_kill =
- (stage == MESA_SHADER_FRAGMENT) &&
- ((brw_wm_prog_data*) this->prog_data)->uses_kill;
int reg_width = dispatch_width / 8;
int length = 0;
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 4);
- sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
+ sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
/* Initialize the sample mask in the message header. */
emit(MOV(sources[0], fs_reg(0u)))
->force_writemask_all = true;
- if (uses_kill) {
- emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
- ->force_writemask_all = true;
+ if (stage == MESA_SHADER_FRAGMENT) {
+ if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
+ emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
+ ->force_writemask_all = true;
+ } else {
+ emit(MOV(component(sources[0], 7),
+ retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
+ ->force_writemask_all = true;
+ }
} else {
+ /* The execution mask is part of the side-band information sent together with
+ * the message payload to the data port. It's implicitly ANDed with the sample
+ * mask sent in the header to compute the actual set of channels that execute
+ * the atomic operation.
+ */
+ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
emit(MOV(component(sources[0], 7),
- retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
- ->force_writemask_all = true;
+ fs_reg(0xffffu)))->force_writemask_all = true;
}
length++;
/* Set the atomic operation offset. */
- sources[1] = fs_reg(this, glsl_type::uint_type);
+ sources[1] = vgrf(glsl_type::uint_type);
emit(MOV(sources[1], offset));
length++;
/* Set the atomic operation arguments. */
if (src0.file != BAD_FILE) {
- sources[length] = fs_reg(this, glsl_type::uint_type);
+ sources[length] = vgrf(glsl_type::uint_type);
emit(MOV(sources[length], src0));
length++;
}
if (src1.file != BAD_FILE) {
- sources[length] = fs_reg(this, glsl_type::uint_type);
+ sources[length] = vgrf(glsl_type::uint_type);
emit(MOV(sources[length], src1));
length++;
}
int mlen = 1 + (length - 1) * reg_width;
- fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
+ fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
BRW_REGISTER_TYPE_UD);
emit(LOAD_PAYLOAD(src_payload, sources, length));
/* Emit the instruction. */
fs_inst *inst = emit(SHADER_OPCODE_UNTYPED_ATOMIC, dst, src_payload,
- fs_reg(atomic_op), fs_reg(surf_index));
+ fs_reg(surf_index), fs_reg(atomic_op));
inst->mlen = mlen;
}
fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
fs_reg offset)
{
- bool uses_kill =
- (stage == MESA_SHADER_FRAGMENT) &&
- ((brw_wm_prog_data*) this->prog_data)->uses_kill;
int reg_width = dispatch_width / 8;
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
- sources[0] = fs_reg(GRF, virtual_grf_alloc(1), BRW_REGISTER_TYPE_UD);
+ sources[0] = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
/* Initialize the sample mask in the message header. */
emit(MOV(sources[0], fs_reg(0u)))
->force_writemask_all = true;
- if (uses_kill) {
- emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
- ->force_writemask_all = true;
+ if (stage == MESA_SHADER_FRAGMENT) {
+ if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
+ emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
+ ->force_writemask_all = true;
+ } else {
+ emit(MOV(component(sources[0], 7),
+ retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
+ ->force_writemask_all = true;
+ }
} else {
+ /* The execution mask is part of the side-band information sent together with
+ * the message payload to the data port. It's implicitly ANDed with the sample
+ * mask sent in the header to compute the actual set of channels that execute
+ * the atomic operation.
+ */
+ assert(stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_COMPUTE);
emit(MOV(component(sources[0], 7),
- retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
- ->force_writemask_all = true;
+ fs_reg(0xffffu)))->force_writemask_all = true;
}
/* Set the surface read offset. */
- sources[1] = fs_reg(this, glsl_type::uint_type);
+ sources[1] = vgrf(glsl_type::uint_type);
emit(MOV(sources[1], offset));
int mlen = 1 + reg_width;
- fs_reg src_payload = fs_reg(GRF, virtual_grf_alloc(mlen),
+ fs_reg src_payload = fs_reg(GRF, alloc.allocate(mlen),
BRW_REGISTER_TYPE_UD);
fs_inst *inst = emit(LOAD_PAYLOAD(src_payload, sources, 2));
/* Emit the instruction. */
inst = emit(SHADER_OPCODE_UNTYPED_SURFACE_READ, dst, src_payload,
- fs_reg(surf_index));
+ fs_reg(surf_index), fs_reg(1));
inst->mlen = mlen;
}
fs_inst *
fs_visitor::emit(fs_inst *inst)
{
- if (force_uncompressed_stack > 0)
- inst->exec_size = 8;
-
if (dispatch_width == 16 && inst->exec_size == 8)
inst->force_uncompressed = true;
int reg_width = dispatch_width / 8;
/* Everyone's favorite color. */
- emit(MOV(fs_reg(MRF, 2 + 0 * reg_width), fs_reg(1.0f)));
- emit(MOV(fs_reg(MRF, 2 + 1 * reg_width), fs_reg(0.0f)));
- emit(MOV(fs_reg(MRF, 2 + 2 * reg_width), fs_reg(1.0f)));
- emit(MOV(fs_reg(MRF, 2 + 3 * reg_width), fs_reg(0.0f)));
+ const float color[4] = { 1.0, 0.0, 1.0, 0.0 };
+ for (int i = 0; i < 4; i++) {
+ emit(MOV(fs_reg(MRF, 2 + i * reg_width, BRW_REGISTER_TYPE_F,
+ dispatch_width), fs_reg(color[i])));
+ }
fs_inst *write;
- write = emit(FS_OPCODE_FB_WRITE, fs_reg(0), fs_reg(0));
- write->base_mrf = 2;
- write->mlen = 4 * reg_width;
+ write = emit(FS_OPCODE_FB_WRITE);
write->eot = true;
+ if (devinfo->gen >= 6) {
+ write->base_mrf = 2;
+ write->mlen = 4 * reg_width;
+ } else {
+ write->header_present = true;
+ write->base_mrf = 0;
+ write->mlen = 2 + 4 * reg_width;
+ }
+
+ /* Tell the SF we don't have any inputs. Gen4-5 require at least one
+ * varying to avoid GPU hangs, so set that.
+ */
+ brw_wm_prog_data *wm_prog_data = (brw_wm_prog_data *) this->prog_data;
+ wm_prog_data->num_varying_inputs = devinfo->gen < 6 ? 1 : 0;
+ memset(wm_prog_data->urb_setup, -1,
+ sizeof(wm_prog_data->urb_setup[0]) * VARYING_SLOT_MAX);
+
+ /* We don't have any uniforms. */
+ stage_prog_data->nr_params = 0;
+ stage_prog_data->nr_pull_params = 0;
+ stage_prog_data->curb_read_length = 0;
+ stage_prog_data->dispatch_grf_start_reg = 2;
+ wm_prog_data->dispatch_grf_start_reg_16 = 2;
+ grf_used = 1; /* Gen4-5 don't allow zero GRF blocks */
+
+ calculate_cfg();
}
/* The register location here is relative to the start of the URB
void
fs_visitor::emit_interpolation_setup_gen4()
{
+ struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
+
this->current_annotation = "compute pixel centers";
- this->pixel_x = fs_reg(this, glsl_type::uint_type);
- this->pixel_y = fs_reg(this, glsl_type::uint_type);
+ this->pixel_x = vgrf(glsl_type::uint_type);
+ this->pixel_y = vgrf(glsl_type::uint_type);
this->pixel_x.type = BRW_REGISTER_TYPE_UW;
this->pixel_y.type = BRW_REGISTER_TYPE_UW;
-
- emit(FS_OPCODE_PIXEL_X, this->pixel_x);
- emit(FS_OPCODE_PIXEL_Y, this->pixel_y);
+ emit(ADD(this->pixel_x,
+ fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x10101010))));
+ emit(ADD(this->pixel_y,
+ fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x11001100))));
this->current_annotation = "compute pixel deltas from v0";
- if (brw->has_pln) {
- this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- fs_reg(this, glsl_type::vec2_type);
- this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- offset(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC], 1);
+
+ this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
+ vgrf(glsl_type::vec2_type);
+ const fs_reg &delta_xy = this->delta_xy[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC];
+ const fs_reg xstart(negate(brw_vec1_grf(1, 0)));
+ const fs_reg ystart(negate(brw_vec1_grf(1, 1)));
+
+ if (devinfo->has_pln && dispatch_width == 16) {
+ emit(ADD(half(offset(delta_xy, 0), 0), half(this->pixel_x, 0), xstart));
+ emit(ADD(half(offset(delta_xy, 0), 1), half(this->pixel_y, 0), ystart));
+ emit(ADD(half(offset(delta_xy, 1), 0), half(this->pixel_x, 1), xstart))
+ ->force_sechalf = true;
+ emit(ADD(half(offset(delta_xy, 1), 1), half(this->pixel_y, 1), ystart))
+ ->force_sechalf = true;
} else {
- this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- fs_reg(this, glsl_type::float_type);
- this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC] =
- fs_reg(this, glsl_type::float_type);
+ emit(ADD(offset(delta_xy, 0), this->pixel_x, xstart));
+ emit(ADD(offset(delta_xy, 1), this->pixel_y, ystart));
}
- emit(ADD(this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- this->pixel_x, fs_reg(negate(brw_vec1_grf(1, 0)))));
- emit(ADD(this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- this->pixel_y, fs_reg(negate(brw_vec1_grf(1, 1)))));
this->current_annotation = "compute pos.w and 1/pos.w";
/* Compute wpos.w. It's always in our setup, since it's needed to
* interpolate the other attributes.
*/
- this->wpos_w = fs_reg(this, glsl_type::float_type);
- emit(FS_OPCODE_LINTERP, wpos_w,
- this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- interp_reg(VARYING_SLOT_POS, 3));
+ this->wpos_w = vgrf(glsl_type::float_type);
+ emit(FS_OPCODE_LINTERP, wpos_w, delta_xy, interp_reg(VARYING_SLOT_POS, 3));
/* Compute the pixel 1/W value from wpos.w. */
- this->pixel_w = fs_reg(this, glsl_type::float_type);
+ this->pixel_w = vgrf(glsl_type::float_type);
emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
this->current_annotation = NULL;
}
{
struct brw_reg g1_uw = retype(brw_vec1_grf(1, 0), BRW_REGISTER_TYPE_UW);
- /* If the pixel centers end up used, the setup is the same as for gen4. */
this->current_annotation = "compute pixel centers";
- fs_reg int_pixel_x = fs_reg(this, glsl_type::uint_type);
- fs_reg int_pixel_y = fs_reg(this, glsl_type::uint_type);
- int_pixel_x.type = BRW_REGISTER_TYPE_UW;
- int_pixel_y.type = BRW_REGISTER_TYPE_UW;
- emit(ADD(int_pixel_x,
- fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
- fs_reg(brw_imm_v(0x10101010))));
- emit(ADD(int_pixel_y,
- fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
- fs_reg(brw_imm_v(0x11001100))));
+ if (brw->gen >= 8 || dispatch_width == 8) {
+ /* The "Register Region Restrictions" page says for BDW (and newer,
+ * presumably):
+ *
+ * "When destination spans two registers, the source may be one or
+ * two registers. The destination elements must be evenly split
+ * between the two registers."
+ *
+ * Thus we can do a single add(16) in SIMD8 or an add(32) in SIMD16 to
+ * compute our pixel centers.
+ */
+ fs_reg int_pixel_xy(GRF, alloc.allocate(dispatch_width / 8),
+ BRW_REGISTER_TYPE_UW, dispatch_width * 2);
+ emit(ADD(int_pixel_xy,
+ fs_reg(stride(suboffset(g1_uw, 4), 1, 4, 0)),
+ fs_reg(brw_imm_v(0x11001010))))
+ ->force_writemask_all = true;
- /* As of gen6, we can no longer mix float and int sources. We have
- * to turn the integer pixel centers into floats for their actual
- * use.
- */
- this->pixel_x = fs_reg(this, glsl_type::float_type);
- this->pixel_y = fs_reg(this, glsl_type::float_type);
- emit(MOV(this->pixel_x, int_pixel_x));
- emit(MOV(this->pixel_y, int_pixel_y));
+ this->pixel_x = vgrf(glsl_type::float_type);
+ this->pixel_y = vgrf(glsl_type::float_type);
+ emit(FS_OPCODE_PIXEL_X, this->pixel_x, int_pixel_xy);
+ emit(FS_OPCODE_PIXEL_Y, this->pixel_y, int_pixel_xy);
+ } else {
+ /* The "Register Region Restrictions" page says for SNB, IVB, HSW:
+ *
+ * "When destination spans two registers, the source MUST span two
+ * registers."
+ *
+ * Since the GRF source of the ADD will only read a single register, we
+ * must do two separate ADDs in SIMD16.
+ */
+ fs_reg int_pixel_x = vgrf(glsl_type::uint_type);
+ fs_reg int_pixel_y = vgrf(glsl_type::uint_type);
+ int_pixel_x.type = BRW_REGISTER_TYPE_UW;
+ int_pixel_y.type = BRW_REGISTER_TYPE_UW;
+ emit(ADD(int_pixel_x,
+ fs_reg(stride(suboffset(g1_uw, 4), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x10101010))));
+ emit(ADD(int_pixel_y,
+ fs_reg(stride(suboffset(g1_uw, 5), 2, 4, 0)),
+ fs_reg(brw_imm_v(0x11001100))));
+
+ /* As of gen6, we can no longer mix float and int sources. We have
+ * to turn the integer pixel centers into floats for their actual
+ * use.
+ */
+ this->pixel_x = vgrf(glsl_type::float_type);
+ this->pixel_y = vgrf(glsl_type::float_type);
+ emit(MOV(this->pixel_x, int_pixel_x));
+ emit(MOV(this->pixel_y, int_pixel_y));
+ }
this->current_annotation = "compute pos.w";
this->pixel_w = fs_reg(brw_vec8_grf(payload.source_w_reg, 0));
- this->wpos_w = fs_reg(this, glsl_type::float_type);
+ this->wpos_w = vgrf(glsl_type::float_type);
emit_math(SHADER_OPCODE_RCP, this->wpos_w, this->pixel_w);
for (int i = 0; i < BRW_WM_BARYCENTRIC_INTERP_MODE_COUNT; ++i) {
uint8_t reg = payload.barycentric_coord_reg[i];
- this->delta_x[i] = fs_reg(brw_vec8_grf(reg, 0));
- this->delta_y[i] = fs_reg(brw_vec8_grf(reg + 1, 0));
+ this->delta_xy[i] = fs_reg(brw_vec16_grf(reg, 0));
}
this->current_annotation = NULL;
}
int
-fs_visitor::setup_color_payload(fs_reg *dst, fs_reg color, unsigned components)
+fs_visitor::setup_color_payload(fs_reg *dst, fs_reg color, unsigned components,
+ bool use_2nd_half)
{
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
fs_inst *inst;
colors_enabled = (1 << components) - 1;
}
- if (dispatch_width == 8 || brw->gen >= 6) {
+ if (dispatch_width == 8 || (devinfo->gen >= 6 && !do_dual_src)) {
/* SIMD8 write looks like:
* m + 0: r0
* m + 1: r1
int len = 0;
for (unsigned i = 0; i < 4; ++i) {
if (colors_enabled & (1 << i)) {
- dst[len] = fs_reg(GRF, virtual_grf_alloc(color.width / 8),
+ dst[len] = fs_reg(GRF, alloc.allocate(color.width / 8),
color.type, color.width);
inst = emit(MOV(dst[len], offset(color, i)));
inst->saturate = key->clamp_fragment_color;
len++;
}
return len;
+ } else if (devinfo->gen >= 6 && do_dual_src) {
+ /* SIMD16 dual source blending for gen6+.
+ *
+ * From the SNB PRM, volume 4, part 1, page 193:
+ *
+ * "The dual source render target messages only have SIMD8 forms due to
+ * maximum message length limitations. SIMD16 pixel shaders must send two
+ * of these messages to cover all of the pixels. Each message contains
+ * two colors (4 channels each) for each pixel in the message payload."
+ *
+ * So in SIMD16 dual source blending we will send 2 SIMD8 messages,
+ * each one will call this function twice (one for each color involved),
+ * so in each pass we only write 4 registers. Notice that the second
+ * SIMD8 message needs to read color data from the 2nd half of the color
+ * registers, so it needs to call this with use_2nd_half = true.
+ */
+ for (unsigned i = 0; i < 4; ++i) {
+ if (colors_enabled & (1 << i)) {
+ dst[i] = fs_reg(GRF, alloc.allocate(1), color.type);
+ inst = emit(MOV(dst[i], half(offset(color, i),
+ use_2nd_half ? 1 : 0)));
+ inst->saturate = key->clamp_fragment_color;
+ if (use_2nd_half)
+ inst->force_sechalf = true;
+ }
+ }
+ return 4;
} else {
/* pre-gen6 SIMD16 single source DP write looks like:
* m + 0: r0
*/
for (unsigned i = 0; i < 4; ++i) {
if (colors_enabled & (1 << i)) {
- dst[i] = fs_reg(GRF, virtual_grf_alloc(1), color.type);
+ dst[i] = fs_reg(GRF, alloc.allocate(1), color.type);
inst = emit(MOV(dst[i], half(offset(color, i), 0)));
inst->saturate = key->clamp_fragment_color;
- dst[i + 4] = fs_reg(GRF, virtual_grf_alloc(1), color.type);
+ dst[i + 4] = fs_reg(GRF, alloc.allocate(1), color.type);
inst = emit(MOV(dst[i + 4], half(offset(color, i), 1)));
inst->saturate = key->clamp_fragment_color;
inst->force_sechalf = true;
fs_inst *
fs_visitor::emit_single_fb_write(fs_reg color0, fs_reg color1,
- fs_reg src0_alpha, unsigned components)
+ fs_reg src0_alpha, unsigned components,
+ bool use_2nd_half)
{
assert(stage == MESA_SHADER_FRAGMENT);
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
* dispatched. This field is only required for the end-of-
* thread message and on all dual-source messages."
*/
- if (brw->gen >= 6 &&
- (brw->is_haswell || brw->gen >= 8 || !prog_data->uses_kill) &&
+ if (devinfo->gen >= 6 &&
+ (devinfo->is_haswell || devinfo->gen >= 8 || !prog_data->uses_kill) &&
color1.file == BAD_FILE &&
key->nr_color_regions == 1) {
header_present = false;
length += 2;
if (payload.aa_dest_stencil_reg) {
- sources[length] = fs_reg(GRF, virtual_grf_alloc(1));
+ sources[length] = fs_reg(GRF, alloc.allocate(1));
emit(MOV(sources[length],
fs_reg(brw_vec8_grf(payload.aa_dest_stencil_reg, 0))));
length++;
/* Hand over gl_SampleMask. Only lower 16 bits are relevant. Since
* it's unsinged single words, one vgrf is always 16-wide.
*/
- sources[length] = fs_reg(GRF, virtual_grf_alloc(1),
+ sources[length] = fs_reg(GRF, alloc.allocate(1),
BRW_REGISTER_TYPE_UW, 16);
emit(FS_OPCODE_SET_OMASK, sources[length], this->sample_mask);
length++;
* alpha out the pipeline to our null renderbuffer to support
* alpha-testing, alpha-to-coverage, and so on.
*/
- length += setup_color_payload(sources + length, this->outputs[0], 0);
+ length += setup_color_payload(sources + length, this->outputs[0], 0,
+ false);
} else if (color1.file == BAD_FILE) {
if (src0_alpha.file != BAD_FILE) {
- sources[length] = fs_reg(GRF, virtual_grf_alloc(reg_size),
+ sources[length] = fs_reg(GRF, alloc.allocate(reg_size),
src0_alpha.type, src0_alpha.width);
fs_inst *inst = emit(MOV(sources[length], src0_alpha));
inst->saturate = key->clamp_fragment_color;
length++;
}
- length += setup_color_payload(sources + length, color0, components);
+ length += setup_color_payload(sources + length, color0, components,
+ false);
} else {
- length += setup_color_payload(sources + length, color0, components);
- length += setup_color_payload(sources + length, color1, components);
+ length += setup_color_payload(sources + length, color0, components,
+ use_2nd_half);
+ length += setup_color_payload(sources + length, color1, components,
+ use_2nd_half);
}
if (source_depth_to_render_target) {
- if (brw->gen == 6) {
+ if (devinfo->gen == 6) {
/* For outputting oDepth on gen6, SIMD8 writes have to be
* used. This would require SIMD8 moves of each half to
* message regs, kind of like pre-gen5 SIMD16 FB writes.
no16("Missing support for simd16 depth writes on gen6\n");
}
- sources[length] = fs_reg(this, glsl_type::float_type);
+ sources[length] = vgrf(glsl_type::float_type);
if (prog->OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
/* Hand over gl_FragDepth. */
assert(this->frag_depth.file != BAD_FILE);
}
if (payload.dest_depth_reg) {
- sources[length] = fs_reg(this, glsl_type::float_type);
+ sources[length] = vgrf(glsl_type::float_type);
emit(MOV(sources[length],
fs_reg(brw_vec8_grf(payload.dest_depth_reg, 0))));
length++;
fs_inst *load;
fs_inst *write;
- if (brw->gen >= 7) {
+ if (devinfo->gen >= 7) {
/* Send from the GRF */
fs_reg payload = fs_reg(GRF, -1, BRW_REGISTER_TYPE_F);
load = emit(LOAD_PAYLOAD(payload, sources, length));
- payload.reg = virtual_grf_alloc(load->regs_written);
+ payload.reg = alloc.allocate(load->regs_written);
+ payload.width = dispatch_width;
load->dst = payload;
write = emit(FS_OPCODE_FB_WRITE, reg_undef, payload);
write->base_mrf = -1;
load = emit(LOAD_PAYLOAD(fs_reg(MRF, 1, BRW_REGISTER_TYPE_F),
sources, length));
write = emit(FS_OPCODE_FB_WRITE);
+ write->exec_size = dispatch_width;
write->base_mrf = 1;
}
write->mlen = load->regs_written;
write->header_present = header_present;
- if ((brw->gen >= 8 || brw->is_haswell) && prog_data->uses_kill) {
+ if (prog_data->uses_kill) {
write->predicate = BRW_PREDICATE_NORMAL;
write->flag_subreg = 1;
}
brw_wm_prog_data *prog_data = (brw_wm_prog_data*) this->prog_data;
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+ fs_inst *inst = NULL;
if (do_dual_src) {
- no16("GL_ARB_blend_func_extended not yet supported in SIMD16.");
- if (dispatch_width == 16)
- do_dual_src = false;
- }
-
- fs_inst *inst;
- if (do_dual_src) {
- if (INTEL_DEBUG & DEBUG_SHADER_TIME)
- emit_shader_time_end();
-
this->current_annotation = ralloc_asprintf(this->mem_ctx,
"FB dual-source write");
inst = emit_single_fb_write(this->outputs[0], this->dual_src_output,
reg_undef, 4);
inst->target = 0;
+
+ /* SIMD16 dual source blending requires to send two SIMD8 dual source
+ * messages, where each message contains color data for 8 pixels. Color
+ * data for the first group of pixels is stored in the "lower" half of
+ * the color registers, so in SIMD16, the previous message did:
+ * m + 0: r0
+ * m + 1: g0
+ * m + 2: b0
+ * m + 3: a0
+ *
+ * Here goes the second message, which packs color data for the
+ * remaining 8 pixels. Color data for these pixels is stored in the
+ * "upper" half of the color registers, so we need to do:
+ * m + 0: r1
+ * m + 1: g1
+ * m + 2: b1
+ * m + 3: a1
+ */
+ if (dispatch_width == 16) {
+ inst = emit_single_fb_write(this->outputs[0], this->dual_src_output,
+ reg_undef, 4, true);
+ inst->target = 0;
+ }
+
prog_data->dual_src_blend = true;
- } else if (key->nr_color_regions > 0) {
+ } else {
for (int target = 0; target < key->nr_color_regions; target++) {
+ /* Skip over outputs that weren't written. */
+ if (this->outputs[target].file == BAD_FILE)
+ continue;
+
this->current_annotation = ralloc_asprintf(this->mem_ctx,
"FB write target %d",
target);
fs_reg src0_alpha;
- if (brw->gen >= 6 && key->replicate_alpha && target != 0)
+ if (devinfo->gen >= 6 && key->replicate_alpha && target != 0)
src0_alpha = offset(outputs[0], 3);
- if (target == key->nr_color_regions - 1 &&
- (INTEL_DEBUG & DEBUG_SHADER_TIME))
- emit_shader_time_end();
-
inst = emit_single_fb_write(this->outputs[target], reg_undef,
src0_alpha,
this->output_components[target]);
inst->target = target;
}
- } else {
- if (INTEL_DEBUG & DEBUG_SHADER_TIME)
- emit_shader_time_end();
+ }
+ if (inst == NULL) {
/* Even if there's no color buffers enabled, we still need to send
* alpha out the pipeline to our null renderbuffer to support
* alpha-testing, alpha-to-coverage, and so on.
this->current_annotation = NULL;
}
+void
+fs_visitor::setup_uniform_clipplane_values()
+{
+ gl_clip_plane *clip_planes = brw_select_clip_planes(ctx);
+ const struct brw_vue_prog_key *key =
+ (const struct brw_vue_prog_key *) this->key;
+
+ for (int i = 0; i < key->nr_userclip_plane_consts; i++) {
+ this->userplane[i] = fs_reg(UNIFORM, uniforms);
+ for (int j = 0; j < 4; ++j) {
+ stage_prog_data->param[uniforms + j] =
+ (gl_constant_value *) &clip_planes[i][j];
+ }
+ uniforms += 4;
+ }
+}
+
+void fs_visitor::compute_clip_distance()
+{
+ struct brw_vue_prog_data *vue_prog_data =
+ (struct brw_vue_prog_data *) prog_data;
+ const struct brw_vue_prog_key *key =
+ (const struct brw_vue_prog_key *) this->key;
+
+ /* From the GLSL 1.30 spec, section 7.1 (Vertex Shader Special Variables):
+ *
+ * "If a linked set of shaders forming the vertex stage contains no
+ * static write to gl_ClipVertex or gl_ClipDistance, but the
+ * application has requested clipping against user clip planes through
+ * the API, then the coordinate written to gl_Position is used for
+ * comparison against the user clip planes."
+ *
+ * This function is only called if the shader didn't write to
+ * gl_ClipDistance. Accordingly, we use gl_ClipVertex to perform clipping
+ * if the user wrote to it; otherwise we use gl_Position.
+ */
+
+ gl_varying_slot clip_vertex = VARYING_SLOT_CLIP_VERTEX;
+ if (!(vue_prog_data->vue_map.slots_valid & VARYING_BIT_CLIP_VERTEX))
+ clip_vertex = VARYING_SLOT_POS;
+
+ /* If the clip vertex isn't written, skip this. Typically this means
+ * the GS will set up clipping. */
+ if (outputs[clip_vertex].file == BAD_FILE)
+ return;
+
+ setup_uniform_clipplane_values();
+
+ current_annotation = "user clip distances";
+
+ this->outputs[VARYING_SLOT_CLIP_DIST0] = vgrf(glsl_type::vec4_type);
+ this->outputs[VARYING_SLOT_CLIP_DIST1] = vgrf(glsl_type::vec4_type);
+
+ for (int i = 0; i < key->nr_userclip_plane_consts; i++) {
+ fs_reg u = userplane[i];
+ fs_reg output = outputs[VARYING_SLOT_CLIP_DIST0 + i / 4];
+ output.reg_offset = i & 3;
+
+ emit(MUL(output, outputs[clip_vertex], u));
+ for (int j = 1; j < 4; j++) {
+ u.reg = userplane[i].reg + j;
+ emit(MAD(output, output, offset(outputs[clip_vertex], j), u));
+ }
+ }
+}
+
+void
+fs_visitor::emit_urb_writes()
+{
+ int slot, urb_offset, length;
+ struct brw_vs_prog_data *vs_prog_data =
+ (struct brw_vs_prog_data *) prog_data;
+ const struct brw_vs_prog_key *key =
+ (const struct brw_vs_prog_key *) this->key;
+ const GLbitfield64 psiz_mask =
+ VARYING_BIT_LAYER | VARYING_BIT_VIEWPORT | VARYING_BIT_PSIZ;
+ const struct brw_vue_map *vue_map = &vs_prog_data->base.vue_map;
+ bool flush;
+ fs_reg sources[8];
+
+ /* Lower legacy ff and ClipVertex clipping to clip distances */
+ if (key->base.userclip_active && !prog->UsesClipDistanceOut)
+ compute_clip_distance();
+
+ /* If we don't have any valid slots to write, just do a minimal urb write
+ * send to terminate the shader. */
+ if (vue_map->slots_valid == 0) {
+
+ fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ fs_inst *inst = emit(MOV(payload, fs_reg(retype(brw_vec8_grf(1, 0),
+ BRW_REGISTER_TYPE_UD))));
+ inst->force_writemask_all = true;
+
+ inst = emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
+ inst->eot = true;
+ inst->mlen = 1;
+ inst->offset = 1;
+ return;
+ }
+
+ length = 0;
+ urb_offset = 0;
+ flush = false;
+ for (slot = 0; slot < vue_map->num_slots; slot++) {
+ fs_reg reg, src, zero;
+
+ int varying = vue_map->slot_to_varying[slot];
+ switch (varying) {
+ case VARYING_SLOT_PSIZ:
+
+ /* The point size varying slot is the vue header and is always in the
+ * vue map. But often none of the special varyings that live there
+ * are written and in that case we can skip writing to the vue
+ * header, provided the corresponding state properly clamps the
+ * values further down the pipeline. */
+ if ((vue_map->slots_valid & psiz_mask) == 0) {
+ assert(length == 0);
+ urb_offset++;
+ break;
+ }
+
+ zero = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ emit(MOV(zero, fs_reg(0u)));
+
+ sources[length++] = zero;
+ if (vue_map->slots_valid & VARYING_BIT_LAYER)
+ sources[length++] = this->outputs[VARYING_SLOT_LAYER];
+ else
+ sources[length++] = zero;
+
+ if (vue_map->slots_valid & VARYING_BIT_VIEWPORT)
+ sources[length++] = this->outputs[VARYING_SLOT_VIEWPORT];
+ else
+ sources[length++] = zero;
+
+ if (vue_map->slots_valid & VARYING_BIT_PSIZ)
+ sources[length++] = this->outputs[VARYING_SLOT_PSIZ];
+ else
+ sources[length++] = zero;
+ break;
+
+ case BRW_VARYING_SLOT_NDC:
+ case VARYING_SLOT_EDGE:
+ unreachable("unexpected scalar vs output");
+ break;
+
+ case BRW_VARYING_SLOT_PAD:
+ break;
+
+ default:
+ /* gl_Position is always in the vue map, but isn't always written by
+ * the shader. Other varyings (clip distances) get added to the vue
+ * map but don't always get written. In those cases, the
+ * corresponding this->output[] slot will be invalid we and can skip
+ * the urb write for the varying. If we've already queued up a vue
+ * slot for writing we flush a mlen 5 urb write, otherwise we just
+ * advance the urb_offset.
+ */
+ if (this->outputs[varying].file == BAD_FILE) {
+ if (length > 0)
+ flush = true;
+ else
+ urb_offset++;
+ break;
+ }
+
+ if ((varying == VARYING_SLOT_COL0 ||
+ varying == VARYING_SLOT_COL1 ||
+ varying == VARYING_SLOT_BFC0 ||
+ varying == VARYING_SLOT_BFC1) &&
+ key->clamp_vertex_color) {
+ /* We need to clamp these guys, so do a saturating MOV into a
+ * temp register and use that for the payload.
+ */
+ for (int i = 0; i < 4; i++) {
+ reg = fs_reg(GRF, alloc.allocate(1), outputs[varying].type);
+ src = offset(this->outputs[varying], i);
+ fs_inst *inst = emit(MOV(reg, src));
+ inst->saturate = true;
+ sources[length++] = reg;
+ }
+ } else {
+ for (int i = 0; i < 4; i++)
+ sources[length++] = offset(this->outputs[varying], i);
+ }
+ break;
+ }
+
+ current_annotation = "URB write";
+
+ /* If we've queued up 8 registers of payload (2 VUE slots), if this is
+ * the last slot or if we need to flush (see BAD_FILE varying case
+ * above), emit a URB write send now to flush out the data.
+ */
+ int last = slot == vue_map->num_slots - 1;
+ if (length == 8 || last)
+ flush = true;
+ if (flush) {
+ fs_reg *payload_sources = ralloc_array(mem_ctx, fs_reg, length + 1);
+ fs_reg payload = fs_reg(GRF, alloc.allocate(length + 1),
+ BRW_REGISTER_TYPE_F);
+
+ /* We need WE_all on the MOV for the message header (the URB handles)
+ * so do a MOV to a dummy register and set force_writemask_all on the
+ * MOV. LOAD_PAYLOAD will preserve that.
+ */
+ fs_reg dummy = fs_reg(GRF, alloc.allocate(1),
+ BRW_REGISTER_TYPE_UD);
+ fs_inst *inst = emit(MOV(dummy, fs_reg(retype(brw_vec8_grf(1, 0),
+ BRW_REGISTER_TYPE_UD))));
+ inst->force_writemask_all = true;
+ payload_sources[0] = dummy;
+
+ memcpy(&payload_sources[1], sources, length * sizeof sources[0]);
+ emit(LOAD_PAYLOAD(payload, payload_sources, length + 1));
+
+ inst = emit(SHADER_OPCODE_URB_WRITE_SIMD8, reg_undef, payload);
+ inst->eot = last;
+ inst->mlen = length + 1;
+ inst->offset = urb_offset;
+ urb_offset = slot + 1;
+ length = 0;
+ flush = false;
+ }
+ }
+}
+
void
fs_visitor::resolve_ud_negate(fs_reg *reg)
{
!reg->negate)
return;
- fs_reg temp = fs_reg(this, glsl_type::uint_type);
+ fs_reg temp = vgrf(glsl_type::uint_type);
emit(MOV(temp, *reg));
*reg = temp;
}
+void
+fs_visitor::emit_cs_terminate()
+{
+ assert(brw->gen >= 7);
+
+ /* We are getting the thread ID from the compute shader header */
+ assert(stage == MESA_SHADER_COMPUTE);
+
+ /* We can't directly send from g0, since sends with EOT have to use
+ * g112-127. So, copy it to a virtual register, The register allocator will
+ * make sure it uses the appropriate register range.
+ */
+ struct brw_reg g0 = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD);
+ fs_reg payload = fs_reg(GRF, alloc.allocate(1), BRW_REGISTER_TYPE_UD);
+ fs_inst *inst = emit(MOV(payload, g0));
+ inst->force_writemask_all = true;
+
+ /* Send a message to the thread spawner to terminate the thread. */
+ inst = emit(CS_OPCODE_CS_TERMINATE, reg_undef, payload);
+ inst->eot = true;
+}
+
+/**
+ * Resolve the result of a Gen4-5 CMP instruction to a proper boolean.
+ *
+ * CMP on Gen4-5 only sets the LSB of the result; the rest are undefined.
+ * If we need a proper boolean value, we have to fix it up to be 0 or ~0.
+ */
void
fs_visitor::resolve_bool_comparison(ir_rvalue *rvalue, fs_reg *reg)
{
- assert(ctx->Const.UniformBooleanTrue == 1);
+ assert(devinfo->gen <= 5);
if (rvalue->type != glsl_type::bool_type)
return;
- fs_reg temp = fs_reg(this, glsl_type::bool_type);
- emit(AND(temp, *reg, fs_reg(1)));
- *reg = temp;
+ fs_reg and_result = vgrf(glsl_type::bool_type);
+ fs_reg neg_result = vgrf(glsl_type::bool_type);
+ emit(AND(and_result, *reg, fs_reg(1)));
+ emit(MOV(neg_result, negate(and_result)));
+ *reg = neg_result;
}
fs_visitor::fs_visitor(struct brw_context *brw,
reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),
key(key), prog_data(&prog_data->base),
+ dispatch_width(dispatch_width), promoted_constants(0)
+{
+ this->mem_ctx = mem_ctx;
+ init();
+}
+
+fs_visitor::fs_visitor(struct brw_context *brw,
+ void *mem_ctx,
+ const struct brw_vs_prog_key *key,
+ struct brw_vs_prog_data *prog_data,
+ struct gl_shader_program *shader_prog,
+ struct gl_vertex_program *cp,
+ unsigned dispatch_width)
+ : backend_visitor(brw, shader_prog, &cp->Base, &prog_data->base.base,
+ MESA_SHADER_VERTEX),
+ reg_null_f(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_F)),
+ reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
+ reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),
+ key(key), prog_data(&prog_data->base.base),
+ dispatch_width(dispatch_width), promoted_constants(0)
+{
+ this->mem_ctx = mem_ctx;
+ init();
+}
+
+fs_visitor::fs_visitor(struct brw_context *brw,
+ void *mem_ctx,
+ const struct brw_cs_prog_key *key,
+ struct brw_cs_prog_data *prog_data,
+ struct gl_shader_program *shader_prog,
+ struct gl_compute_program *cp,
+ unsigned dispatch_width)
+ : backend_visitor(brw, shader_prog, &cp->Base, &prog_data->base,
+ MESA_SHADER_COMPUTE),
+ reg_null_f(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_F)),
+ reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
+ reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),
+ key(key), prog_data(&prog_data->base),
dispatch_width(dispatch_width)
{
this->mem_ctx = mem_ctx;
void
fs_visitor::init()
{
+ switch (stage) {
+ case MESA_SHADER_FRAGMENT:
+ key_tex = &((const brw_wm_prog_key *) key)->tex;
+ break;
+ case MESA_SHADER_VERTEX:
+ case MESA_SHADER_GEOMETRY:
+ key_tex = &((const brw_vue_prog_key *) key)->tex;
+ break;
+ case MESA_SHADER_COMPUTE:
+ key_tex = &((const brw_cs_prog_key*) key)->tex;
+ break;
+ default:
+ unreachable("unhandled shader stage");
+ }
+
this->failed = false;
this->simd16_unsupported = false;
this->no16_msg = NULL;
hash_table_pointer_hash,
hash_table_pointer_compare);
+ this->nir_locals = NULL;
+ this->nir_globals = NULL;
+
memset(&this->payload, 0, sizeof(this->payload));
memset(this->outputs, 0, sizeof(this->outputs));
memset(this->output_components, 0, sizeof(this->output_components));
this->source_depth_to_render_target = false;
this->runtime_check_aads_emit = false;
this->first_non_payload_grf = 0;
- this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+ this->max_grf = devinfo->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->current_annotation = NULL;
this->base_ir = NULL;
- this->virtual_grf_sizes = NULL;
- this->virtual_grf_count = 0;
- this->virtual_grf_array_size = 0;
this->virtual_grf_start = NULL;
this->virtual_grf_end = NULL;
this->live_intervals = NULL;
this->pull_constant_loc = NULL;
this->push_constant_loc = NULL;
- this->force_uncompressed_stack = 0;
-
this->spilled_any_registers = false;
this->do_dual_src = false;
projects / mesa.git / blobdiff