}
#include "brw_shader.h"
#include "brw_fs.h"
-#include "../glsl/glsl_types.h"
-#include "../glsl/ir_optimization.h"
-#include "../glsl/ir_print_visitor.h"
+#include "glsl/glsl_types.h"
+#include "glsl/ir_optimization.h"
+#include "glsl/ir_print_visitor.h"
void
fs_visitor::visit(ir_variable *ir)
if (!sat_val)
return false;
- this->result = reg_undef;
sat_val->accept(this);
fs_reg src = this->result;
if (try_emit_saturate(ir))
return;
- /* This is where our caller would like us to put the result, if possible. */
- fs_reg saved_result_storage = this->result;
-
for (operand = 0; operand < ir->get_num_operands(); operand++) {
- this->result = reg_undef;
ir->operands[operand]->accept(this);
if (this->result.file == BAD_FILE) {
ir_print_visitor v;
assert(!ir->operands[operand]->type->is_vector());
}
- /* Inherit storage from our parent if possible, and otherwise we
- * alloc a temporary.
+ /* Storage for our result. If our result goes into an assignment, it will
+ * just get copy-propagated out, so no worries.
*/
- if (saved_result_storage.file == BAD_FILE) {
- this->result = fs_reg(this, ir->type);
- } else {
- this->result = saved_result_storage;
- }
+ this->result = fs_reg(this, ir->type);
switch (ir->operation) {
case ir_unop_logic_not:
case ir_unop_sign:
temp = fs_reg(this, ir->type);
- /* Unalias the destination. (imagine a = sign(a)) */
- this->result = fs_reg(this, ir->type);
-
emit(BRW_OPCODE_MOV, this->result, fs_reg(0.0f));
inst = emit(BRW_OPCODE_CMP, reg_null_f, op[0], fs_reg(0.0f));
this->result = op[0];
break;
case ir_unop_i2f:
+ case ir_unop_u2f:
case ir_unop_b2f:
case ir_unop_b2i:
case ir_unop_f2i:
inst = emit(BRW_OPCODE_OR, this->result, op[0], op[1]);
break;
- case ir_unop_u2f:
case ir_binop_lshift:
case ir_binop_rshift:
assert(!"GLSL 1.30 features unsupported");
}
}
+/* If the RHS processing resulted in an instruction generating a
+ * temporary value, and it would be easy to rewrite the instruction to
+ * generate its result right into the LHS instead, do so. This ends
+ * up reliably removing instructions where it can be tricky to do so
+ * later without real UD chain information.
+ */
+bool
+fs_visitor::try_rewrite_rhs_to_dst(ir_assignment *ir,
+ fs_reg dst,
+ fs_reg src,
+ fs_inst *pre_rhs_inst,
+ fs_inst *last_rhs_inst)
+{
+ if (pre_rhs_inst == last_rhs_inst)
+ return false; /* No instructions generated to work with. */
+
+ /* Only attempt if we're doing a direct assignment. */
+ if (ir->condition ||
+ !(ir->lhs->type->is_scalar() ||
+ (ir->lhs->type->is_vector() &&
+ ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1)))
+ return false;
+
+ /* Make sure the last instruction generated our source reg. */
+ if (last_rhs_inst->predicated ||
+ last_rhs_inst->force_uncompressed ||
+ last_rhs_inst->force_sechalf ||
+ !src.equals(&last_rhs_inst->dst))
+ return false;
+
+ /* Success! Rewrite the instruction. */
+ last_rhs_inst->dst = dst;
+
+ return true;
+}
+
void
fs_visitor::visit(ir_assignment *ir)
{
fs_inst *inst;
/* FINISHME: arrays on the lhs */
- this->result = reg_undef;
ir->lhs->accept(this);
l = this->result;
- /* If we're doing a direct assignment, an RHS expression could
- * drop its result right into our destination. Otherwise, tell it
- * not to.
- */
- if (ir->condition ||
- !(ir->lhs->type->is_scalar() ||
- (ir->lhs->type->is_vector() &&
- ir->write_mask == (1 << ir->lhs->type->vector_elements) - 1))) {
- this->result = reg_undef;
- }
+ fs_inst *pre_rhs_inst = (fs_inst *) this->instructions.get_tail();
ir->rhs->accept(this);
r = this->result;
+ fs_inst *last_rhs_inst = (fs_inst *) this->instructions.get_tail();
+
assert(l.file != BAD_FILE);
assert(r.file != BAD_FILE);
+ if (try_rewrite_rhs_to_dst(ir, l, r, pre_rhs_inst, last_rhs_inst))
+ return;
+
if (ir->condition) {
emit_bool_to_cond_code(ir->condition);
}
ir->lhs->type->is_vector()) {
for (int i = 0; i < ir->lhs->type->vector_elements; i++) {
if (ir->write_mask & (1 << i)) {
- if (ir->condition) {
- inst = emit(BRW_OPCODE_MOV, l, r);
+ inst = emit(BRW_OPCODE_MOV, l, r);
+ if (ir->condition)
inst->predicated = true;
- } else if (!l.equals(&r)) {
- inst = emit(BRW_OPCODE_MOV, l, r);
- }
-
r.reg_offset++;
}
l.reg_offset++;
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), fs_reg(0.0f));
mlen++;
} else if (ir->op == ir_txb) {
- this->result = reg_undef;
ir->lod_info.bias->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
} else {
assert(ir->op == ir_txl);
- this->result = reg_undef;
ir->lod_info.lod->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
}
- this->result = reg_undef;
ir->shadow_comparitor->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
mlen += 3;
} else if (ir->op == ir_txd) {
- this->result = reg_undef;
ir->lod_info.grad.dPdx->accept(this);
fs_reg dPdx = this->result;
- this->result = reg_undef;
ir->lod_info.grad.dPdy->accept(this);
fs_reg dPdy = this->result;
} else if (ir->op == ir_txs) {
/* There's no SIMD8 resinfo message on Gen4. Use SIMD16 instead. */
simd16 = true;
- this->result = reg_undef;
ir->lod_info.lod->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result);
mlen += 2;
mlen += 6;
if (ir->op == ir_txb) {
- this->result = reg_undef;
ir->lod_info.bias->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
} else {
- this->result = reg_undef;
ir->lod_info.lod->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen++;
for (int i = 0; i < vector_elements; i++) {
fs_inst *inst = emit(BRW_OPCODE_MOV,
- fs_reg(MRF, base_mrf + mlen + i * reg_width),
+ fs_reg(MRF, base_mrf + mlen + i * reg_width,
+ coordinate.type),
coordinate);
if (i < 3 && c->key.gl_clamp_mask[i] & (1 << sampler))
inst->saturate = true;
if (ir->shadow_comparitor && ir->op != ir_txd) {
mlen = MAX2(mlen, header_present + 4 * reg_width);
- this->result = reg_undef;
ir->shadow_comparitor->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen += reg_width;
inst = emit(FS_OPCODE_TEX, dst);
break;
case ir_txb:
- this->result = reg_undef;
ir->lod_info.bias->accept(this);
mlen = MAX2(mlen, header_present + 4 * reg_width);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
break;
case ir_txl:
- this->result = reg_undef;
ir->lod_info.lod->accept(this);
mlen = MAX2(mlen, header_present + 4 * reg_width);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
inst = emit(FS_OPCODE_TXL, dst);
break;
case ir_txd: {
- this->result = reg_undef;
ir->lod_info.grad.dPdx->accept(this);
fs_reg dPdx = this->result;
- this->result = reg_undef;
ir->lod_info.grad.dPdy->accept(this);
fs_reg dPdy = this->result;
break;
}
case ir_txs:
- this->result = reg_undef;
ir->lod_info.lod->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result);
mlen += reg_width;
inst = emit(FS_OPCODE_TXS, dst);
break;
case ir_txf:
- assert(!"GLSL 1.30 features unsupported");
+ mlen = header_present + 4 * reg_width;
+
+ ir->lod_info.lod->accept(this);
+ emit(BRW_OPCODE_MOV,
+ fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD),
+ this->result);
+ inst = emit(FS_OPCODE_TXF, dst);
break;
}
inst->base_mrf = base_mrf;
}
if (ir->shadow_comparitor && ir->op != ir_txd) {
- this->result = reg_undef;
ir->shadow_comparitor->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen += reg_width;
case ir_tex:
break;
case ir_txb:
- this->result = reg_undef;
ir->lod_info.bias->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen += reg_width;
break;
case ir_txl:
- this->result = reg_undef;
ir->lod_info.lod->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), this->result);
mlen += reg_width;
if (c->dispatch_width == 16)
fail("Gen7 does not support sample_d/sample_d_c in SIMD16 mode.");
- this->result = reg_undef;
ir->lod_info.grad.dPdx->accept(this);
fs_reg dPdx = this->result;
- this->result = reg_undef;
ir->lod_info.grad.dPdy->accept(this);
fs_reg dPdy = this->result;
break;
}
case ir_txs:
- this->result = reg_undef;
ir->lod_info.lod->accept(this);
emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), this->result);
mlen += reg_width;
break;
case ir_txf:
- assert(!"GLSL 1.30 features unsupported");
+ /* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
+ fs_inst *inst = emit(BRW_OPCODE_MOV,
+ fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
+ coordinate);
+ coordinate.reg_offset++;
+ mlen += reg_width;
+
+ ir->lod_info.lod->accept(this);
+ emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), this->result);
+ mlen += reg_width;
+
+ for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
+ fs_inst *inst = emit(BRW_OPCODE_MOV,
+ fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
+ coordinate);
+ coordinate.reg_offset++;
+ mlen += reg_width;
+ }
break;
}
- /* Set up the coordinate (except for TXD where it was done earlier) */
- if (ir->op != ir_txd && ir->op != ir_txs) {
+ /* Set up the coordinate (except for cases where it was done above) */
+ if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) {
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
fs_inst *inst = emit(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
coordinate);
case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break;
case ir_txl: inst = emit(FS_OPCODE_TXL, dst); break;
case ir_txd: inst = emit(FS_OPCODE_TXD, dst); break;
- case ir_txf: assert(!"TXF unsupported."); break;
+ case ir_txf: inst = emit(FS_OPCODE_TXF, dst); break;
case ir_txs: inst = emit(FS_OPCODE_TXS, dst); break;
}
inst->base_mrf = base_mrf;
return swizzle_result(ir, fs_reg(0.0f), sampler);
}
- this->result = reg_undef;
if (ir->coordinate)
ir->coordinate->accept(this);
fs_reg coordinate = this->result;
if (hw_compare_supported) {
inst->shadow_compare = true;
} else {
- this->result = reg_undef;
ir->shadow_comparitor->accept(this);
fs_reg ref = this->result;
void
fs_visitor::visit(ir_swizzle *ir)
{
- this->result = reg_undef;
ir->val->accept(this);
fs_reg val = this->result;
const unsigned size = type_size(ir->type->fields.array);
for (unsigned i = 0; i < ir->type->length; i++) {
- this->result = reg_undef;
ir->array_elements[i]->accept(this);
fs_reg src_reg = this->result;
ir_instruction *const field = (ir_instruction *) node;
const unsigned size = type_size(field->type);
- this->result = reg_undef;
field->accept(this);
fs_reg src_reg = this->result;
for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
assert(expr->operands[i]->type->is_scalar());
- this->result = reg_undef;
expr->operands[i]->accept(this);
op[i] = this->result;
}
return;
}
- this->result = reg_undef;
ir->accept(this);
if (intel->gen >= 6) {
for (unsigned int i = 0; i < expr->get_num_operands(); i++) {
assert(expr->operands[i]->type->is_scalar());
- this->result = reg_undef;
expr->operands[i]->accept(this);
op[i] = this->result;
}
return;
}
- this->result = reg_undef;
ir->condition->accept(this);
fs_inst *inst = emit(BRW_OPCODE_IF, reg_null_d, this->result, fs_reg(0));
foreach_list(node, &ir->then_instructions) {
ir_instruction *ir = (ir_instruction *)node;
this->base_ir = ir;
- this->result = reg_undef;
+
ir->accept(this);
}
foreach_list(node, &ir->else_instructions) {
ir_instruction *ir = (ir_instruction *)node;
this->base_ir = ir;
- this->result = reg_undef;
+
ir->accept(this);
}
}
counter = *(variable_storage(ir->counter));
if (ir->from) {
- this->result = counter;
-
this->base_ir = ir->from;
- this->result = counter;
ir->from->accept(this);
- if (!this->result.equals(&counter))
- emit(BRW_OPCODE_MOV, counter, this->result);
+ emit(BRW_OPCODE_MOV, counter, this->result);
}
}
if (ir->to) {
this->base_ir = ir->to;
- this->result = reg_undef;
ir->to->accept(this);
fs_inst *inst = emit(BRW_OPCODE_CMP, reg_null_cmp, counter, this->result);
ir_instruction *ir = (ir_instruction *)node;
this->base_ir = ir;
- this->result = reg_undef;
ir->accept(this);
}
if (ir->increment) {
this->base_ir = ir->increment;
- this->result = reg_undef;
ir->increment->accept(this);
emit(BRW_OPCODE_ADD, counter, counter, this->result);
}
foreach_list(node, &sig->body) {
ir_instruction *ir = (ir_instruction *)node;
this->base_ir = ir;
- this->result = reg_undef;
+
ir->accept(this);
}
}
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