#include "main/macros.h"
#include "main/shaderobj.h"
-#include "main/uniforms.h"
#include "program/prog_parameter.h"
#include "program/prog_print.h"
#include "program/prog_optimize.h"
#include "brw_wm.h"
}
#include "brw_fs.h"
+#include "main/uniforms.h"
#include "glsl/glsl_types.h"
#include "glsl/ir_optimization.h"
-#include "glsl/ir_print_visitor.h"
void
fs_visitor::visit(ir_variable *ir)
if (variable_storage(ir))
return;
- if (ir->mode == ir_var_in) {
+ if (ir->mode == ir_var_shader_in) {
if (!strcmp(ir->name, "gl_FragCoord")) {
reg = emit_fragcoord_interpolation(ir);
} else if (!strcmp(ir->name, "gl_FrontFacing")) {
assert(reg);
hash_table_insert(this->variable_ht, reg, ir);
return;
- } else if (ir->mode == ir_var_out) {
+ } else if (ir->mode == ir_var_shader_out) {
reg = new(this->mem_ctx) fs_reg(this, ir->type);
if (ir->index > 0) {
* ir_binop_ubo_load expressions and not ir_dereference_variable for UBO
* variables, so no need for them to be in variable_ht.
*/
- if (ir->uniform_block != -1)
+ if (ir->is_in_uniform_block())
return;
if (dispatch_width == 16) {
this->result = src;
}
+void
+fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
+{
+ if (brw->gen < 6 ||
+ !x.is_valid_3src() ||
+ !y.is_valid_3src() ||
+ !a.is_valid_3src()) {
+ /* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
+ fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
+ fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
+ fs_reg x_times_one_minus_a = fs_reg(this, glsl_type::float_type);
+
+ emit(MUL(y_times_a, y, a));
+
+ a.negate = !a.negate;
+ emit(ADD(one_minus_a, a, fs_reg(1.0f)));
+ emit(MUL(x_times_one_minus_a, x, one_minus_a));
+
+ emit(ADD(dst, x_times_one_minus_a, y_times_a));
+ } else {
+ /* The LRP instruction actually does op1 * op0 + op2 * (1 - op0), so
+ * we need to reorder the operands.
+ */
+ emit(LRP(dst, a, y, x));
+ }
+}
+
void
fs_visitor::emit_minmax(uint32_t conditionalmod, fs_reg dst,
fs_reg src0, fs_reg src1)
{
fs_inst *inst;
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->conditional_mod = conditionalmod;
} else {
* src, generate a saturated MOV
*/
fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src);
- if (!modify || modify->regs_written() != 1) {
+ if (!modify || modify->regs_written != 1) {
this->result = fs_reg(this, ir->type);
fs_inst *inst = emit(MOV(this->result, src));
inst->saturate = true;
fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg)
{
/* 3-src instructions were introduced in gen6. */
- if (intel->gen < 6)
+ if (brw->gen < 6)
return false;
/* MAD can only handle floating-point data. */
fs_visitor::visit(ir_expression *ir)
{
unsigned int operand;
- fs_reg op[2], temp;
+ fs_reg op[3], temp;
fs_inst *inst;
- assert(ir->get_num_operands() <= 2);
+ assert(ir->get_num_operands() <= 3);
if (try_emit_saturate(ir))
return;
for (operand = 0; operand < ir->get_num_operands(); operand++) {
ir->operands[operand]->accept(this);
if (this->result.file == BAD_FILE) {
- ir_print_visitor v;
fail("Failed to get tree for expression operand:\n");
- ir->operands[operand]->accept(&v);
+ ir->operands[operand]->print();
+ printf("\n");
}
+ assert(this->result.is_valid_3src());
op[operand] = this->result;
/* Matrix expression operands should have been broken down to vector
break;
case ir_unop_neg:
op[0].negate = !op[0].negate;
- this->result = op[0];
+ emit(MOV(this->result, op[0]));
break;
case ir_unop_abs:
op[0].abs = true;
op[0].negate = false;
- this->result = op[0];
+ emit(MOV(this->result, op[0]));
break;
case ir_unop_sign:
temp = fs_reg(this, ir->type);
* FINISHME: Emit just the MUL if we know an operand is small
* enough.
*/
- if (intel->gen >= 7 && dispatch_width == 16)
+ if (brw->gen >= 7 && dispatch_width == 16)
fail("16-wide explicit accumulator operands unsupported\n");
- struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D);
+ struct brw_reg acc = retype(brw_acc_reg(), this->result.type);
emit(MUL(acc, op[0], op[1]));
emit(MACH(reg_null_d, op[0], op[1]));
emit(MUL(this->result, op[0], op[1]));
}
break;
+ case ir_binop_imul_high: {
+ if (brw->gen >= 7 && dispatch_width == 16)
+ fail("16-wide explicit accumulator operands unsupported\n");
+
+ struct brw_reg acc = retype(brw_acc_reg(), this->result.type);
+
+ emit(MUL(acc, op[0], op[1]));
+ emit(MACH(this->result, op[0], op[1]));
+ break;
+ }
case ir_binop_div:
/* Floating point should be lowered by DIV_TO_MUL_RCP in the compiler. */
assert(ir->type->is_integer());
emit_math(SHADER_OPCODE_INT_QUOTIENT, this->result, op[0], op[1]);
break;
+ case ir_binop_carry: {
+ if (brw->gen >= 7 && dispatch_width == 16)
+ fail("16-wide explicit accumulator operands unsupported\n");
+
+ struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD);
+
+ emit(ADDC(reg_null_ud, op[0], op[1]));
+ emit(MOV(this->result, fs_reg(acc)));
+ break;
+ }
+ case ir_binop_borrow: {
+ if (brw->gen >= 7 && dispatch_width == 16)
+ fail("16-wide explicit accumulator operands unsupported\n");
+
+ struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_UD);
+
+ emit(SUBB(reg_null_ud, op[0], op[1]));
+ emit(MOV(this->result, fs_reg(acc)));
+ break;
+ }
case ir_binop_mod:
/* Floating point should be lowered by MOD_TO_FRACT in the compiler. */
assert(ir->type->is_integer());
assert(!"not reached: should be handled by lower_quadop_vector");
break;
+ case ir_binop_vector_extract:
+ assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
+ break;
+
+ case ir_triop_vector_insert:
+ assert(!"not reached: should be handled by lower_vector_insert()");
+ break;
+
+ case ir_binop_ldexp:
+ assert(!"not reached: should be handled by ldexp_to_arith()");
+ break;
+
case ir_unop_sqrt:
emit_math(SHADER_OPCODE_SQRT, this->result, op[0]);
break;
break;
case ir_unop_b2i:
- inst = emit(AND(this->result, op[0], fs_reg(1)));
+ emit(AND(this->result, op[0], fs_reg(1)));
break;
case ir_unop_b2f:
temp = fs_reg(this, glsl_type::int_type);
break;
case ir_unop_ceil:
op[0].negate = !op[0].negate;
- inst = emit(RNDD(this->result, op[0]));
+ emit(RNDD(this->result, op[0]));
this->result.negate = true;
break;
case ir_unop_floor:
- inst = emit(RNDD(this->result, op[0]));
+ emit(RNDD(this->result, op[0]));
break;
case ir_unop_fract:
- inst = emit(FRC(this->result, op[0]));
+ emit(FRC(this->result, op[0]));
break;
case ir_unop_round_even:
emit(RNDE(this->result, op[0]));
BRW_CONDITIONAL_L : BRW_CONDITIONAL_GE,
this->result, op[0], op[1]);
break;
-
+ case ir_unop_pack_snorm_2x16:
+ case ir_unop_pack_snorm_4x8:
+ case ir_unop_pack_unorm_2x16:
+ case ir_unop_pack_unorm_4x8:
+ case ir_unop_unpack_snorm_2x16:
+ case ir_unop_unpack_snorm_4x8:
+ case ir_unop_unpack_unorm_2x16:
+ case ir_unop_unpack_unorm_4x8:
+ case ir_unop_unpack_half_2x16:
+ case ir_unop_pack_half_2x16:
+ assert(!"not reached: should be handled by lower_packing_builtins");
+ break;
+ case ir_unop_unpack_half_2x16_split_x:
+ emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X, this->result, op[0]);
+ break;
+ case ir_unop_unpack_half_2x16_split_y:
+ emit(FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y, this->result, op[0]);
+ break;
case ir_binop_pow:
emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]);
break;
+ case ir_unop_bitfield_reverse:
+ emit(BFREV(this->result, op[0]));
+ break;
+ case ir_unop_bit_count:
+ emit(CBIT(this->result, op[0]));
+ break;
+ case ir_unop_find_msb:
+ temp = fs_reg(this, glsl_type::uint_type);
+ emit(FBH(temp, op[0]));
+
+ /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
+ * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
+ * subtract the result from 31 to convert the MSB count into an LSB count.
+ */
+
+ /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
+ emit(MOV(this->result, temp));
+ emit(CMP(reg_null_d, this->result, fs_reg(-1), BRW_CONDITIONAL_NZ));
+
+ temp.negate = true;
+ inst = emit(ADD(this->result, temp, fs_reg(31)));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ break;
+ case ir_unop_find_lsb:
+ emit(FBL(this->result, op[0]));
+ break;
+ case ir_triop_bitfield_extract:
+ /* Note that the instruction's argument order is reversed from GLSL
+ * and the IR.
+ */
+ emit(BFE(this->result, op[2], op[1], op[0]));
+ break;
+ case ir_binop_bfm:
+ emit(BFI1(this->result, op[0], op[1]));
+ break;
+ case ir_triop_bfi:
+ emit(BFI2(this->result, op[0], op[1], op[2]));
+ break;
+ case ir_quadop_bitfield_insert:
+ assert(!"not reached: should be handled by "
+ "lower_instructions::bitfield_insert_to_bfm_bfi");
+ break;
+
case ir_unop_bit_not:
- inst = emit(NOT(this->result, op[0]));
+ emit(NOT(this->result, op[0]));
break;
case ir_binop_bit_and:
- inst = emit(AND(this->result, op[0], op[1]));
+ emit(AND(this->result, op[0], op[1]));
break;
case ir_binop_bit_xor:
- inst = emit(XOR(this->result, op[0], op[1]));
+ emit(XOR(this->result, op[0], op[1]));
break;
case ir_binop_bit_or:
- inst = emit(OR(this->result, op[0], op[1]));
+ emit(OR(this->result, op[0], op[1]));
break;
case ir_binop_lshift:
- inst = emit(SHL(this->result, op[0], op[1]));
+ emit(SHL(this->result, op[0], op[1]));
break;
case ir_binop_rshift:
if (ir->type->base_type == GLSL_TYPE_INT)
- inst = emit(ASR(this->result, op[0], op[1]));
+ emit(ASR(this->result, op[0], op[1]));
else
- inst = emit(SHR(this->result, op[0], op[1]));
+ emit(SHR(this->result, op[0], op[1]));
break;
-
- case ir_binop_ubo_load:
+ case ir_binop_pack_half_2x16_split:
+ emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, this->result, op[0], op[1]);
+ break;
+ case ir_binop_ubo_load: {
/* This IR node takes a constant uniform block and a constant or
* variable byte offset within the block and loads a vector from that.
*/
ir_constant *uniform_block = ir->operands[0]->as_constant();
ir_constant *const_offset = ir->operands[1]->as_constant();
- fs_reg surf_index = fs_reg((unsigned)SURF_INDEX_WM_UBO(uniform_block->value.u[0]));
+ fs_reg surf_index = fs_reg(c->prog_data.base.binding_table.ubo_start +
+ uniform_block->value.u[0]);
if (const_offset) {
fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
packed_consts.type = result.type;
- if (intel->gen >= 7) {
- fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] / 16);
- fs_reg payload = fs_reg(this, glsl_type::uint_type);
- struct brw_reg g0 = retype(brw_vec8_grf(0, 0),
- BRW_REGISTER_TYPE_UD);
- fs_inst *setup = emit(MOV(payload, fs_reg(g0)));
- setup->force_writemask_all = true;
- /* We don't need the second half of this vgrf to be filled with g1
- * in the 16-wide case, but if we use force_uncompressed then live
- * variable analysis won't consider this a def!
- */
-
- emit(FS_OPCODE_SET_GLOBAL_OFFSET, payload,
- payload, const_offset_reg);
- emit(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7, packed_consts,
- surf_index, payload);
- } else {
- fs_reg const_offset_reg = fs_reg(const_offset->value.u[0]);
- fs_inst *pull = emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
- packed_consts,
- surf_index,
- const_offset_reg));
- pull->base_mrf = 14;
- pull->mlen = 1;
- }
+ fs_reg const_offset_reg = fs_reg(const_offset->value.u[0] & ~15);
+ emit(fs_inst(FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
+ packed_consts, surf_index, const_offset_reg));
packed_consts.smear = const_offset->value.u[0] % 16 / 4;
for (int i = 0; i < ir->type->vector_elements; i++) {
emit(SHR(base_offset, op[1], fs_reg(2)));
for (int i = 0; i < ir->type->vector_elements; i++) {
- fs_reg offset = fs_reg(this, glsl_type::int_type);
- emit(ADD(offset, base_offset, fs_reg(i)));
- emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index, offset));
+ emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index,
+ base_offset, i));
if (ir->type->base_type == GLSL_TYPE_BOOL)
emit(CMP(result, result, fs_reg(0), BRW_CONDITIONAL_NZ));
result.reg_offset = 0;
break;
}
+
+ case ir_triop_fma:
+ /* Note that the instruction's argument order is reversed from GLSL
+ * and the IR.
+ */
+ emit(MAD(this->result, op[2], op[1], op[0]));
+ break;
+
+ case ir_triop_lrp:
+ emit_lrp(this->result, op[0], op[1], op[2]);
+ break;
+
+ case ir_triop_csel:
+ emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
+ inst = emit(BRW_OPCODE_SEL, this->result, op[1], op[2]);
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ break;
+ }
}
void
case GLSL_TYPE_SAMPLER:
break;
- default:
+ case GLSL_TYPE_VOID:
+ case GLSL_TYPE_ERROR:
+ case GLSL_TYPE_INTERFACE:
assert(!"not reached");
break;
}
/* If last_rhs_inst wrote a different number of components than our LHS,
* we can't safely rewrite it.
*/
- if (virtual_grf_sizes[dst.reg] != modify->regs_written())
+ if (virtual_grf_sizes[dst.reg] != modify->regs_written)
return false;
/* Success! Rewrite the instruction. */
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
coordinate.reg_offset++;
}
- /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
+
+ /* gen4's SIMD8 sampler always has the slots for u,v,r present.
+ * the unused slots must be zeroed.
+ */
+ for (int i = ir->coordinate->type->vector_elements; i < 3; i++) {
+ emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
+ }
mlen += 3;
if (ir->op == ir_tex) {
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
coordinate.reg_offset++;
}
+ /* zero the others. */
+ for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
+ emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
+ }
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
mlen += 3;
} else if (ir->op == ir_txd) {
* this weirdness around to the expected layout.
*/
orig_dst = dst;
- const glsl_type *vec_type =
- glsl_type::get_instance(ir->type->base_type, 4, 1);
- dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2));
- dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type)
- : BRW_REGISTER_TYPE_F;
+ dst = fs_reg(GRF, virtual_grf_alloc(8),
+ (brw->is_g4x ?
+ brw_type_for_base_type(ir->type) :
+ BRW_REGISTER_TYPE_F));
}
fs_inst *inst = NULL;
case ir_txf:
inst = emit(SHADER_OPCODE_TXF, dst);
break;
+ default:
+ fail("unrecognized texture opcode");
}
inst->base_mrf = base_mrf;
inst->mlen = mlen;
inst->header_present = true;
+ inst->regs_written = simd16 ? 8 : 4;
if (simd16) {
for (int i = 0; i < 4; i++) {
*/
fs_inst *
fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg lod2)
+ fs_reg shadow_c, fs_reg lod, fs_reg lod2,
+ fs_reg sample_index)
{
int mlen = 0;
int base_mrf = 2;
mlen += reg_width;
inst = emit(SHADER_OPCODE_TXS, dst);
break;
+ case ir_query_levels:
+ emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
+ mlen += reg_width;
+ inst = emit(SHADER_OPCODE_TXS, dst);
+ break;
case ir_txf:
mlen = header_present + 4 * reg_width;
-
- emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD),
- lod));
+ emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
inst = emit(SHADER_OPCODE_TXF, dst);
break;
+ case ir_txf_ms:
+ mlen = header_present + 4 * reg_width;
+
+ /* lod */
+ emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0)));
+ /* sample index */
+ emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
+ mlen += reg_width;
+ inst = emit(SHADER_OPCODE_TXF_MS, dst);
+ break;
+ case ir_lod:
+ inst = emit(SHADER_OPCODE_LOD, dst);
+ break;
+ case ir_tg4:
+ inst = emit(SHADER_OPCODE_TG4, dst);
+ break;
+ default:
+ fail("unrecognized texture opcode");
+ break;
}
inst->base_mrf = base_mrf;
inst->mlen = mlen;
inst->header_present = header_present;
+ inst->regs_written = 4;
if (mlen > 11) {
fail("Message length >11 disallowed by hardware\n");
fs_inst *
fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg lod2)
+ fs_reg shadow_c, fs_reg lod, fs_reg lod2,
+ fs_reg sample_index)
{
- int mlen = 0;
- int base_mrf = 2;
int reg_width = dispatch_width / 8;
bool header_present = false;
int offsets[3];
- if (ir->offset && ir->op != ir_txf) {
- /* The offsets set up by the ir_texture visitor are in the
- * m1 header, so we can't go headerless.
+ fs_reg payload = fs_reg(this, glsl_type::float_type);
+ fs_reg next = payload;
+
+ if (ir->op == ir_tg4 || (ir->offset && ir->op != ir_txf)) {
+ /* For general texture offsets (no txf workaround), we need a header to
+ * put them in. Note that for 16-wide we're making space for two actual
+ * hardware registers here, so the emit will have to fix up for this.
+ *
+ * * ir4_tg4 needs to place its channel select in the header,
+ * for interaction with ARB_texture_swizzle
*/
header_present = true;
- mlen++;
- base_mrf--;
+ next.reg_offset++;
}
if (ir->shadow_comparitor) {
- emit(MOV(fs_reg(MRF, base_mrf + mlen), shadow_c));
- mlen += reg_width;
+ emit(MOV(next, shadow_c));
+ next.reg_offset++;
}
/* Set up the LOD info */
switch (ir->op) {
case ir_tex:
+ case ir_lod:
+ case ir_tg4:
break;
case ir_txb:
- emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
- mlen += reg_width;
+ emit(MOV(next, lod));
+ next.reg_offset++;
break;
case ir_txl:
- emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
- mlen += reg_width;
+ emit(MOV(next, lod));
+ next.reg_offset++;
break;
case ir_txd: {
if (dispatch_width == 16)
* [hdr], [ref], x, dPdx.x, dPdy.x, y, dPdx.y, dPdy.y, z, dPdx.z, dPdy.z
*/
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
- emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
+ emit(MOV(next, coordinate));
coordinate.reg_offset++;
- mlen += reg_width;
+ next.reg_offset++;
/* For cube map array, the coordinate is (u,v,r,ai) but there are
* only derivatives for (u, v, r).
*/
if (i < ir->lod_info.grad.dPdx->type->vector_elements) {
- emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
+ emit(MOV(next, lod));
lod.reg_offset++;
- mlen += reg_width;
+ next.reg_offset++;
- emit(MOV(fs_reg(MRF, base_mrf + mlen), lod2));
+ emit(MOV(next, lod2));
lod2.reg_offset++;
- mlen += reg_width;
+ next.reg_offset++;
}
}
break;
}
case ir_txs:
- emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
- mlen += reg_width;
+ emit(MOV(next.retype(BRW_REGISTER_TYPE_UD), lod));
+ next.reg_offset++;
+ break;
+ case ir_query_levels:
+ emit(MOV(next.retype(BRW_REGISTER_TYPE_UD), fs_reg(0u)));
+ next.reg_offset++;
break;
case ir_txf:
/* It appears that the ld instruction used for txf does its
}
/* Unfortunately, the parameters for LD are intermixed: u, lod, v, r. */
- emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
- coordinate, offsets[0]));
+ emit(ADD(next.retype(BRW_REGISTER_TYPE_D), coordinate, offsets[0]));
coordinate.reg_offset++;
- mlen += reg_width;
+ next.reg_offset++;
- emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D), lod));
- mlen += reg_width;
+ emit(MOV(next.retype(BRW_REGISTER_TYPE_D), lod));
+ next.reg_offset++;
for (int i = 1; i < ir->coordinate->type->vector_elements; i++) {
- emit(ADD(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
- coordinate, offsets[i]));
+ emit(ADD(next.retype(BRW_REGISTER_TYPE_D), coordinate, offsets[i]));
coordinate.reg_offset++;
- mlen += reg_width;
+ next.reg_offset++;
+ }
+ break;
+ case ir_txf_ms:
+ emit(MOV(next.retype(BRW_REGISTER_TYPE_UD), sample_index));
+ next.reg_offset++;
+
+ /* constant zero MCS; we arrange to never actually have a compressed
+ * multisample surface here for now. TODO: issue ld_mcs to get this first,
+ * if we ever support texturing from compressed multisample surfaces
+ */
+ emit(MOV(next.retype(BRW_REGISTER_TYPE_UD), fs_reg(0u)));
+ next.reg_offset++;
+
+ /* there is no offsetting for this message; just copy in the integer
+ * texture coordinates
+ */
+ for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ emit(MOV(next.retype(BRW_REGISTER_TYPE_D), coordinate));
+ coordinate.reg_offset++;
+ next.reg_offset++;
}
break;
}
/* Set up the coordinate (except for cases where it was done above) */
- if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) {
+ if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf && ir->op != ir_txf_ms && ir->op != ir_query_levels) {
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
- emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
+ emit(MOV(next, coordinate));
coordinate.reg_offset++;
- mlen += reg_width;
+ next.reg_offset++;
}
}
/* Generate the SEND */
fs_inst *inst = NULL;
switch (ir->op) {
- case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst); break;
- case ir_txb: inst = emit(FS_OPCODE_TXB, dst); break;
- case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break;
- case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break;
- case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break;
- case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break;
- }
- inst->base_mrf = base_mrf;
- inst->mlen = mlen;
+ case ir_tex: inst = emit(SHADER_OPCODE_TEX, dst, payload); break;
+ case ir_txb: inst = emit(FS_OPCODE_TXB, dst, payload); break;
+ case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst, payload); break;
+ case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst, payload); break;
+ case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst, payload); break;
+ case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst, payload); break;
+ case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst, payload); break;
+ case ir_query_levels: inst = emit(SHADER_OPCODE_TXS, dst, payload); break;
+ case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst, payload); break;
+ case ir_tg4: inst = emit(SHADER_OPCODE_TG4, dst, payload); break;
+ }
+ inst->base_mrf = -1;
+ if (reg_width == 2)
+ inst->mlen = next.reg_offset * reg_width - header_present;
+ else
+ inst->mlen = next.reg_offset * reg_width;
+
inst->header_present = header_present;
+ inst->regs_written = 4;
- if (mlen > 11) {
+ virtual_grf_sizes[payload.reg] = next.reg_offset;
+ if (inst->mlen > 11) {
fail("Message length >11 disallowed by hardware\n");
}
* tracking to get the scaling factor.
*/
if (is_rect &&
- (intel->gen < 6 ||
- (intel->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
+ (brw->gen < 6 ||
+ (brw->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) {
- struct gl_program_parameter_list *params = fp->Base.Parameters;
+ struct gl_program_parameter_list *params = prog->Parameters;
int tokens[STATE_LENGTH] = {
STATE_INTERNAL,
STATE_TEXRECT_SCALE,
GLuint index = _mesa_add_state_reference(params,
(gl_state_index *)tokens);
c->prog_data.param[c->prog_data.nr_params++] =
- &fp->Base.Parameters->ParameterValues[index][0].f;
+ &prog->Parameters->ParameterValues[index][0].f;
c->prog_data.param[c->prog_data.nr_params++] =
- &fp->Base.Parameters->ParameterValues[index][1].f;
+ &prog->Parameters->ParameterValues[index][1].f;
}
/* The 965 requires the EU to do the normalization of GL rectangle
* texture coordinates. We use the program parameter state
* tracking to get the scaling factor.
*/
- if (intel->gen < 6 && is_rect) {
+ if (brw->gen < 6 && is_rect) {
fs_reg dst = fs_reg(this, ir->coordinate->type);
fs_reg src = coordinate;
coordinate = dst;
{
fs_inst *inst = NULL;
- int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base);
+ int sampler =
+ _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, prog);
/* FINISHME: We're failing to recompile our programs when the sampler is
* updated. This only matters for the texture rectangle scale parameters
* (pre-gen6, or gen6+ with GL_CLAMP).
*/
- int texunit = fp->Base.SamplerUnits[sampler];
+ int texunit = prog->SamplerUnits[sampler];
+
+ if (ir->op == ir_tg4) {
+ /* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
+ * emitting anything other than setting up the constant result.
+ */
+ ir_constant *chan = ir->lod_info.component->as_constant();
+ int swiz = GET_SWZ(c->key.tex.swizzles[sampler], chan->value.i[0]);
+ if (swiz == SWIZZLE_ZERO || swiz == SWIZZLE_ONE) {
+
+ fs_reg res = fs_reg(this, glsl_type::vec4_type);
+ this->result = res;
+
+ for (int i=0; i<4; i++) {
+ emit(MOV(res, fs_reg(swiz == SWIZZLE_ZERO ? 0.0f : 1.0f)));
+ res.reg_offset++;
+ }
+ return;
+ }
+ }
/* Should be lowered by do_lower_texture_projection */
assert(!ir->projector);
shadow_comparitor = this->result;
}
- fs_reg lod, lod2;
+ fs_reg lod, lod2, sample_index;
switch (ir->op) {
case ir_tex:
+ case ir_lod:
+ case ir_tg4:
+ case ir_query_levels:
break;
case ir_txb:
ir->lod_info.bias->accept(this);
ir->lod_info.lod->accept(this);
lod = this->result;
break;
+ case ir_txf_ms:
+ ir->lod_info.sample_index->accept(this);
+ sample_index = this->result;
+ break;
+ default:
+ assert(!"Unrecognized texture opcode");
};
/* Writemasking doesn't eliminate channels on SIMD8 texture
*/
fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
- if (intel->gen >= 7) {
+ if (brw->gen >= 7) {
inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
- lod, lod2);
- } else if (intel->gen >= 5) {
+ lod, lod2, sample_index);
+ } else if (brw->gen >= 5) {
inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
- lod, lod2);
+ lod, lod2, sample_index);
} else {
inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
lod, lod2);
}
- /* The header is set up by generate_tex() when necessary. */
- inst->src[0] = reg_undef;
-
if (ir->offset != NULL && ir->op != ir_txf)
- inst->texture_offset = brw_texture_offset(ir->offset->as_constant());
+ inst->texture_offset = brw_texture_offset(ctx, ir->offset->as_constant());
+
+ if (ir->op == ir_tg4)
+ inst->texture_offset |= gather_channel(ir, sampler) << 16; // M0.2:16-17
inst->sampler = sampler;
swizzle_result(ir, dst, sampler);
}
+/**
+ * Set up the gather channel based on the swizzle, for gather4.
+ */
+uint32_t
+fs_visitor::gather_channel(ir_texture *ir, int sampler)
+{
+ ir_constant *chan = ir->lod_info.component->as_constant();
+ int swiz = GET_SWZ(c->key.tex.swizzles[sampler], chan->value.i[0]);
+ switch (swiz) {
+ case SWIZZLE_X: return 0;
+ case SWIZZLE_Y:
+ /* gather4 sampler is broken for green channel on RG32F --
+ * we must ask for blue instead.
+ */
+ if (c->key.tex.gather_channel_quirk_mask & (1<<sampler))
+ return 2;
+ return 1;
+ case SWIZZLE_Z: return 2;
+ case SWIZZLE_W: return 3;
+ default:
+ assert(!"Not reached"); /* zero, one swizzles handled already */
+ return 0;
+ }
+}
+
/**
* Swizzle the result of a texture result. This is necessary for
* EXT_texture_swizzle as well as DEPTH_TEXTURE_MODE for shadow comparisons.
void
fs_visitor::swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler)
{
+ if (ir->op == ir_query_levels) {
+ /* # levels is in .w */
+ orig_val.reg_offset += 3;
+ this->result = orig_val;
+ return;
+ }
+
this->result = orig_val;
- if (ir->op == ir_txs)
+ /* txs,lod don't actually sample the texture, so swizzling the result
+ * makes no sense.
+ */
+ if (ir->op == ir_txs || ir->op == ir_lod || ir->op == ir_tg4)
return;
if (ir->type == glsl_type::float_type) {
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
/* For performance, after a discard, jump to the end of the shader.
* However, many people will do foliage by discarding based on a
* texture's alpha mask, and then continue on to texture with the
{
ir_expression *expr = ir->as_expression();
- if (expr) {
+ if (expr &&
+ expr->operation != ir_binop_logic_and &&
+ expr->operation != ir_binop_logic_or &&
+ expr->operation != ir_binop_logic_xor) {
fs_reg op[2];
fs_inst *inst;
inst->conditional_mod = BRW_CONDITIONAL_Z;
break;
- case ir_binop_logic_xor:
- case ir_binop_logic_or:
- case ir_binop_logic_and:
- goto out;
-
case ir_unop_f2b:
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_f, op[0]));
break;
case ir_unop_i2b:
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_d, op[0]));
return;
}
-out:
ir->accept(this);
fs_inst *inst = emit(AND(reg_null_d, this->result, fs_reg(1)));
inst->predicate = BRW_PREDICATE_NORMAL;
}
+/**
+ * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
+ *
+ * Many GLSL shaders contain the following pattern:
+ *
+ * x = condition ? foo : bar
+ *
+ * The compiler emits an ir_if tree for this, since each subexpression might be
+ * a complex tree that could have side-effects or short-circuit logic.
+ *
+ * However, the common case is to simply select one of two constants or
+ * variable values---which is exactly what SEL is for. In this case, the
+ * assembly looks like:
+ *
+ * (+f0) IF
+ * MOV dst src0
+ * ELSE
+ * MOV dst src1
+ * ENDIF
+ *
+ * which can be easily translated into:
+ *
+ * (+f0) SEL dst src0 src1
+ *
+ * If src0 is an immediate value, we promote it to a temporary GRF.
+ */
+void
+fs_visitor::try_replace_with_sel()
+{
+ fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
+ assert(endif_inst->opcode == BRW_OPCODE_ENDIF);
+
+ /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
+ int opcodes[] = {
+ BRW_OPCODE_IF, BRW_OPCODE_MOV, BRW_OPCODE_ELSE, BRW_OPCODE_MOV,
+ };
+
+ fs_inst *match = (fs_inst *) endif_inst->prev;
+ for (int i = 0; i < 4; i++) {
+ if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
+ return;
+ match = (fs_inst *) match->prev;
+ }
+
+ /* The opcodes match; it looks like the right sequence of instructions. */
+ fs_inst *else_mov = (fs_inst *) endif_inst->prev;
+ fs_inst *then_mov = (fs_inst *) else_mov->prev->prev;
+ fs_inst *if_inst = (fs_inst *) then_mov->prev;
+
+ /* Check that the MOVs are the right form. */
+ if (then_mov->dst.equals(else_mov->dst) &&
+ !then_mov->is_partial_write() &&
+ !else_mov->is_partial_write()) {
+
+ /* Remove the matched instructions; we'll emit a SEL to replace them. */
+ while (!if_inst->next->is_tail_sentinel())
+ if_inst->next->remove();
+ if_inst->remove();
+
+ /* Only the last source register can be a constant, so if the MOV in
+ * the "then" clause uses a constant, we need to put it in a temporary.
+ */
+ fs_reg src0(then_mov->src[0]);
+ if (src0.file == IMM) {
+ src0 = fs_reg(this, glsl_type::float_type);
+ src0.type = then_mov->src[0].type;
+ emit(MOV(src0, then_mov->src[0]));
+ }
+
+ fs_inst *sel;
+ if (if_inst->conditional_mod) {
+ /* Sandybridge-specific IF with embedded comparison */
+ emit(CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
+ if_inst->conditional_mod));
+ sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
+ sel->predicate = BRW_PREDICATE_NORMAL;
+ } else {
+ /* Separate CMP and IF instructions */
+ sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
+ sel->predicate = if_inst->predicate;
+ sel->predicate_inverse = if_inst->predicate_inverse;
+ }
+ }
+}
+
void
fs_visitor::visit(ir_if *ir)
{
- if (intel->gen < 6 && dispatch_width == 16) {
+ if (brw->gen < 6 && dispatch_width == 16) {
fail("Can't support (non-uniform) control flow on 16-wide\n");
}
*/
this->base_ir = ir->condition;
- if (intel->gen == 6) {
+ if (brw->gen == 6) {
emit_if_gen6(ir);
} else {
emit_bool_to_cond_code(ir->condition);
}
emit(BRW_OPCODE_ENDIF);
+
+ try_replace_with_sel();
}
void
{
fs_reg counter = reg_undef;
- if (intel->gen < 6 && dispatch_width == 16) {
+ if (brw->gen < 6 && dispatch_width == 16) {
fail("Can't support (non-uniform) control flow on 16-wide\n");
}
const ir_function_signature *sig;
exec_list empty;
- sig = ir->matching_signature(&empty);
+ sig = ir->matching_signature(NULL, &empty);
assert(sig);
(void)ir;
}
+void
+fs_visitor::visit(ir_emit_vertex *)
+{
+ assert(!"not reached");
+}
+
+void
+fs_visitor::visit(ir_end_primitive *)
+{
+ assert(!"not reached");
+}
+
fs_inst *
fs_visitor::emit(fs_inst inst)
{
struct brw_reg
fs_visitor::interp_reg(int location, int channel)
{
- int regnr = urb_setup[location] * 2 + channel / 2;
+ int regnr = c->prog_data.urb_setup[location] * 2 + channel / 2;
int stride = (channel & 1) * 4;
- assert(urb_setup[location] != -1);
+ assert(c->prog_data.urb_setup[location] != -1);
return brw_vec1_grf(regnr, stride);
}
emit(FS_OPCODE_LINTERP, wpos_w,
this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- interp_reg(FRAG_ATTRIB_WPOS, 3));
+ interp_reg(VARYING_SLOT_POS, 3));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = fs_reg(this, glsl_type::float_type);
emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
color.reg_offset += index;
- if (dispatch_width == 8 || intel->gen >= 6) {
+ if (dispatch_width == 8 || brw->gen >= 6) {
/* SIMD8 write looks like:
* m + 0: r0
* m + 1: r1
* dispatched. This field is only required for the end-of-
* thread message and on all dual-source messages."
*/
- if (intel->gen >= 6 &&
+ if (brw->gen >= 6 &&
!this->fp->UsesKill &&
!do_dual_src &&
c->key.nr_color_regions == 1) {
}
if (header_present) {
- src0_alpha_to_render_target = intel->gen >= 6 &&
+ src0_alpha_to_render_target = brw->gen >= 6 &&
!do_dual_src &&
- c->key.nr_color_regions > 1 &&
- c->key.sample_alpha_to_coverage;
+ c->key.replicate_alpha;
/* m2, m3 header */
nr += 2;
}
nr += reg_width;
if (c->source_depth_to_render_target) {
- if (intel->gen == 6 && dispatch_width == 16) {
+ if (brw->gen == 6 && dispatch_width == 16) {
/* For outputting oDepth on gen6, SIMD8 writes have to be
* used. This would require 8-wide moves of each half to
* message regs, kind of like pre-gen5 SIMD16 FB writes.
fail("Missing support for simd16 depth writes on gen6\n");
}
- if (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
+ if (prog->OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DEPTH)) {
/* Hand over gl_FragDepth. */
assert(this->frag_depth.file != BAD_FILE);
emit(MOV(fs_reg(MRF, nr), this->frag_depth));
inst->saturate = c->key.clamp_fragment_color;
}
+ if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ emit_shader_time_end();
+
fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
inst->target = 0;
inst->base_mrf = base_mrf;
for (unsigned i = 0; i < this->output_components[target]; i++)
emit_color_write(target, i, write_color_mrf);
+ bool eot = false;
+ if (target == c->key.nr_color_regions - 1) {
+ eot = true;
+
+ if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ emit_shader_time_end();
+ }
+
fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
inst->target = target;
inst->base_mrf = base_mrf;
inst->mlen = nr - base_mrf - reg_width;
else
inst->mlen = nr - base_mrf;
- if (target == c->key.nr_color_regions - 1)
- inst->eot = true;
+ inst->eot = eot;
inst->header_present = header_present;
}
*/
emit_color_write(0, 3, color_mrf);
+ if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ emit_shader_time_end();
+
fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
inst->base_mrf = base_mrf;
inst->mlen = nr - base_mrf;
fs_visitor::fs_visitor(struct brw_context *brw,
struct brw_wm_compile *c,
- struct gl_shader_program *prog,
+ struct gl_shader_program *shader_prog,
struct gl_fragment_program *fp,
unsigned dispatch_width)
: dispatch_width(dispatch_width)
this->c = c;
this->brw = brw;
this->fp = fp;
- this->prog = prog;
- this->intel = &brw->intel;
- this->ctx = &intel->ctx;
+ this->prog = &fp->Base;
+ this->shader_prog = shader_prog;
+ this->prog = &fp->Base;
+ this->stage_prog_data = &c->prog_data.base;
+ this->ctx = &brw->ctx;
this->mem_ctx = ralloc_context(NULL);
- if (prog)
- shader = (struct brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
+ if (shader_prog)
+ shader = (struct brw_shader *)
+ shader_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
else
shader = NULL;
this->failed = false;
memset(this->outputs, 0, sizeof(this->outputs));
memset(this->output_components, 0, sizeof(this->output_components));
this->first_non_payload_grf = 0;
- this->max_grf = intel->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+ this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->current_annotation = NULL;
this->base_ir = NULL;
this->virtual_grf_sizes = NULL;
this->virtual_grf_count = 0;
this->virtual_grf_array_size = 0;
- this->virtual_grf_def = NULL;
- this->virtual_grf_use = NULL;
- this->live_intervals_valid = false;
+ this->virtual_grf_start = NULL;
+ this->virtual_grf_end = NULL;
+ this->live_intervals = NULL;
+
+ this->params_remap = NULL;
+ this->nr_params_remap = 0;
this->force_uncompressed_stack = 0;
this->force_sechalf_stack = 0;
projects / mesa.git / blobdiff