#include "brw_fs.h"
#include "glsl/glsl_types.h"
#include "glsl/ir_optimization.h"
-#include "glsl/ir_print_visitor.h"
void
fs_visitor::visit(ir_variable *ir)
void
fs_visitor::emit_lrp(fs_reg dst, fs_reg x, fs_reg y, fs_reg a)
{
- if (intel->gen < 6 || x.file != GRF || y.file != GRF || a.file != GRF) {
+ if (brw->gen < 6 ||
+ !x.is_valid_3src() ||
+ !y.is_valid_3src() ||
+ !a.is_valid_3src()) {
/* We can't use the LRP instruction. Emit x*(1-a) + y*a. */
fs_reg y_times_a = fs_reg(this, glsl_type::float_type);
fs_reg one_minus_a = fs_reg(this, glsl_type::float_type);
{
fs_inst *inst;
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
inst = emit(BRW_OPCODE_SEL, dst, src0, src1);
inst->conditional_mod = conditionalmod;
} else {
* src, generate a saturated MOV
*/
fs_inst *modify = get_instruction_generating_reg(pre_inst, last_inst, src);
- if (!modify || modify->regs_written() != 1) {
+ if (!modify || modify->regs_written != 1) {
this->result = fs_reg(this, ir->type);
fs_inst *inst = emit(MOV(this->result, src));
inst->saturate = true;
fs_visitor::try_emit_mad(ir_expression *ir, int mul_arg)
{
/* 3-src instructions were introduced in gen6. */
- if (intel->gen < 6)
+ if (brw->gen < 6)
return false;
/* MAD can only handle floating-point data. */
for (operand = 0; operand < ir->get_num_operands(); operand++) {
ir->operands[operand]->accept(this);
if (this->result.file == BAD_FILE) {
- ir_print_visitor v;
fail("Failed to get tree for expression operand:\n");
- ir->operands[operand]->accept(&v);
+ ir->operands[operand]->print();
+ printf("\n");
}
op[operand] = this->result;
break;
case ir_unop_neg:
op[0].negate = !op[0].negate;
- this->result = op[0];
+ emit(MOV(this->result, op[0]));
break;
case ir_unop_abs:
op[0].abs = true;
op[0].negate = false;
- this->result = op[0];
+ emit(MOV(this->result, op[0]));
break;
case ir_unop_sign:
temp = fs_reg(this, ir->type);
* FINISHME: Emit just the MUL if we know an operand is small
* enough.
*/
- if (intel->gen >= 7 && dispatch_width == 16)
+ if (brw->gen >= 7 && dispatch_width == 16)
fail("16-wide explicit accumulator operands unsupported\n");
struct brw_reg acc = retype(brw_acc_reg(), BRW_REGISTER_TYPE_D);
assert(!"not reached: should be handled by lower_quadop_vector");
break;
+ case ir_binop_vector_extract:
+ assert(!"not reached: should be handled by lower_vec_index_to_cond_assign()");
+ break;
+
+ case ir_triop_vector_insert:
+ assert(!"not reached: should be handled by lower_vector_insert()");
+ break;
+
case ir_unop_sqrt:
emit_math(SHADER_OPCODE_SQRT, this->result, op[0]);
break;
break;
case ir_unop_b2i:
- inst = emit(AND(this->result, op[0], fs_reg(1)));
+ emit(AND(this->result, op[0], fs_reg(1)));
break;
case ir_unop_b2f:
temp = fs_reg(this, glsl_type::int_type);
break;
case ir_unop_ceil:
op[0].negate = !op[0].negate;
- inst = emit(RNDD(this->result, op[0]));
+ emit(RNDD(this->result, op[0]));
this->result.negate = true;
break;
case ir_unop_floor:
- inst = emit(RNDD(this->result, op[0]));
+ emit(RNDD(this->result, op[0]));
break;
case ir_unop_fract:
- inst = emit(FRC(this->result, op[0]));
+ emit(FRC(this->result, op[0]));
break;
case ir_unop_round_even:
emit(RNDE(this->result, op[0]));
emit_math(SHADER_OPCODE_POW, this->result, op[0], op[1]);
break;
+ case ir_unop_bitfield_reverse:
+ emit(BFREV(this->result, op[0]));
+ break;
+ case ir_unop_bit_count:
+ emit(CBIT(this->result, op[0]));
+ break;
+ case ir_unop_find_msb:
+ temp = fs_reg(this, glsl_type::uint_type);
+ emit(FBH(temp, op[0]));
+
+ /* FBH counts from the MSB side, while GLSL's findMSB() wants the count
+ * from the LSB side. If FBH didn't return an error (0xFFFFFFFF), then
+ * subtract the result from 31 to convert the MSB count into an LSB count.
+ */
+
+ /* FBH only supports UD type for dst, so use a MOV to convert UD to D. */
+ emit(MOV(this->result, temp));
+ emit(CMP(reg_null_d, this->result, fs_reg(-1), BRW_CONDITIONAL_NZ));
+
+ temp.negate = true;
+ inst = emit(ADD(this->result, temp, fs_reg(31)));
+ inst->predicate = BRW_PREDICATE_NORMAL;
+ break;
+ case ir_unop_find_lsb:
+ emit(FBL(this->result, op[0]));
+ break;
+ case ir_triop_bitfield_extract:
+ /* Note that the instruction's argument order is reversed from GLSL
+ * and the IR.
+ */
+ emit(BFE(this->result, op[2], op[1], op[0]));
+ break;
+ case ir_binop_bfm:
+ emit(BFI1(this->result, op[0], op[1]));
+ break;
+ case ir_triop_bfi:
+ emit(BFI2(this->result, op[0], op[1], op[2]));
+ break;
+ case ir_quadop_bitfield_insert:
+ assert(!"not reached: should be handled by "
+ "lower_instructions::bitfield_insert_to_bfm_bfi");
+ break;
+
case ir_unop_bit_not:
- inst = emit(NOT(this->result, op[0]));
+ emit(NOT(this->result, op[0]));
break;
case ir_binop_bit_and:
- inst = emit(AND(this->result, op[0], op[1]));
+ emit(AND(this->result, op[0], op[1]));
break;
case ir_binop_bit_xor:
- inst = emit(XOR(this->result, op[0], op[1]));
+ emit(XOR(this->result, op[0], op[1]));
break;
case ir_binop_bit_or:
- inst = emit(OR(this->result, op[0], op[1]));
+ emit(OR(this->result, op[0], op[1]));
break;
case ir_binop_lshift:
- inst = emit(SHL(this->result, op[0], op[1]));
+ emit(SHL(this->result, op[0], op[1]));
break;
case ir_binop_rshift:
if (ir->type->base_type == GLSL_TYPE_INT)
- inst = emit(ASR(this->result, op[0], op[1]));
+ emit(ASR(this->result, op[0], op[1]));
else
- inst = emit(SHR(this->result, op[0], op[1]));
+ emit(SHR(this->result, op[0], op[1]));
break;
case ir_binop_pack_half_2x16_split:
emit(FS_OPCODE_PACK_HALF_2x16_SPLIT, this->result, op[0], op[1]);
emit(SHR(base_offset, op[1], fs_reg(2)));
for (int i = 0; i < ir->type->vector_elements; i++) {
- fs_reg offset = fs_reg(this, glsl_type::int_type);
- emit(ADD(offset, base_offset, fs_reg(i)));
- emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index, offset));
+ emit(VARYING_PULL_CONSTANT_LOAD(result, surf_index,
+ base_offset, i));
if (ir->type->base_type == GLSL_TYPE_BOOL)
emit(CMP(result, result, fs_reg(0), BRW_CONDITIONAL_NZ));
/* If last_rhs_inst wrote a different number of components than our LHS,
* we can't safely rewrite it.
*/
- if (virtual_grf_sizes[dst.reg] != modify->regs_written())
+ if (virtual_grf_sizes[dst.reg] != modify->regs_written)
return false;
/* Success! Rewrite the instruction. */
emit(MOV(fs_reg(MRF, base_mrf + mlen + i), coordinate));
coordinate.reg_offset++;
}
+ /* zero the others. */
+ for (int i = ir->coordinate->type->vector_elements; i<3; i++) {
+ emit(MOV(fs_reg(MRF, base_mrf + mlen + i), fs_reg(0.0f)));
+ }
/* gen4's SIMD8 sampler always has the slots for u,v,r present. */
mlen += 3;
} else if (ir->op == ir_txd) {
* this weirdness around to the expected layout.
*/
orig_dst = dst;
- const glsl_type *vec_type =
- glsl_type::get_instance(ir->type->base_type, 4, 1);
- dst = fs_reg(this, glsl_type::get_array_instance(vec_type, 2));
- dst.type = intel->is_g4x ? brw_type_for_base_type(ir->type)
- : BRW_REGISTER_TYPE_F;
+ dst = fs_reg(GRF, virtual_grf_alloc(8),
+ (brw->is_g4x ?
+ brw_type_for_base_type(ir->type) :
+ BRW_REGISTER_TYPE_F));
}
fs_inst *inst = NULL;
case ir_txf:
inst = emit(SHADER_OPCODE_TXF, dst);
break;
+ default:
+ fail("unrecognized texture opcode");
}
inst->base_mrf = base_mrf;
inst->mlen = mlen;
inst->header_present = true;
+ inst->regs_written = simd16 ? 8 : 4;
if (simd16) {
for (int i = 0; i < 4; i++) {
*/
fs_inst *
fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg lod2)
+ fs_reg shadow_c, fs_reg lod, fs_reg lod2,
+ fs_reg sample_index)
{
int mlen = 0;
int base_mrf = 2;
break;
case ir_txf:
mlen = header_present + 4 * reg_width;
-
- emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD),
- lod));
+ emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), lod));
inst = emit(SHADER_OPCODE_TXF, dst);
break;
+ case ir_txf_ms:
+ mlen = header_present + 4 * reg_width;
+
+ /* lod */
+ emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), fs_reg(0)));
+ /* sample index */
+ emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
+ mlen += reg_width;
+ inst = emit(SHADER_OPCODE_TXF_MS, dst);
+ break;
+ case ir_lod:
+ inst = emit(SHADER_OPCODE_LOD, dst);
+ break;
}
inst->base_mrf = base_mrf;
inst->mlen = mlen;
inst->header_present = header_present;
+ inst->regs_written = 4;
if (mlen > 11) {
fail("Message length >11 disallowed by hardware\n");
fs_inst *
fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg lod2)
+ fs_reg shadow_c, fs_reg lod, fs_reg lod2,
+ fs_reg sample_index)
{
int mlen = 0;
int base_mrf = 2;
/* Set up the LOD info */
switch (ir->op) {
case ir_tex:
+ case ir_lod:
break;
case ir_txb:
emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
mlen += reg_width;
}
break;
+ case ir_txf_ms:
+ emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), sample_index));
+ mlen += reg_width;
+
+ /* constant zero MCS; we arrange to never actually have a compressed
+ * multisample surface here for now. TODO: issue ld_mcs to get this first,
+ * if we ever support texturing from compressed multisample surfaces
+ */
+ emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), fs_reg(0u)));
+ mlen += reg_width;
+
+ /* there is no offsetting for this message; just copy in the integer
+ * texture coordinates
+ */
+ for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
+ emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_D),
+ coordinate));
+ coordinate.reg_offset++;
+ mlen += reg_width;
+ }
+ break;
}
/* Set up the coordinate (except for cases where it was done above) */
- if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf) {
+ if (ir->op != ir_txd && ir->op != ir_txs && ir->op != ir_txf && ir->op != ir_txf_ms) {
for (int i = 0; i < ir->coordinate->type->vector_elements; i++) {
emit(MOV(fs_reg(MRF, base_mrf + mlen), coordinate));
coordinate.reg_offset++;
case ir_txl: inst = emit(SHADER_OPCODE_TXL, dst); break;
case ir_txd: inst = emit(SHADER_OPCODE_TXD, dst); break;
case ir_txf: inst = emit(SHADER_OPCODE_TXF, dst); break;
+ case ir_txf_ms: inst = emit(SHADER_OPCODE_TXF_MS, dst); break;
case ir_txs: inst = emit(SHADER_OPCODE_TXS, dst); break;
+ case ir_lod: inst = emit(SHADER_OPCODE_LOD, dst); break;
}
inst->base_mrf = base_mrf;
inst->mlen = mlen;
inst->header_present = header_present;
+ inst->regs_written = 4;
if (mlen > 11) {
fail("Message length >11 disallowed by hardware\n");
* tracking to get the scaling factor.
*/
if (is_rect &&
- (intel->gen < 6 ||
- (intel->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
+ (brw->gen < 6 ||
+ (brw->gen >= 6 && (c->key.tex.gl_clamp_mask[0] & (1 << sampler) ||
c->key.tex.gl_clamp_mask[1] & (1 << sampler))))) {
struct gl_program_parameter_list *params = fp->Base.Parameters;
int tokens[STATE_LENGTH] = {
* texture coordinates. We use the program parameter state
* tracking to get the scaling factor.
*/
- if (intel->gen < 6 && is_rect) {
+ if (brw->gen < 6 && is_rect) {
fs_reg dst = fs_reg(this, ir->coordinate->type);
fs_reg src = coordinate;
coordinate = dst;
{
fs_inst *inst = NULL;
- int sampler = _mesa_get_sampler_uniform_value(ir->sampler, prog, &fp->Base);
+ int sampler =
+ _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, &fp->Base);
/* FINISHME: We're failing to recompile our programs when the sampler is
* updated. This only matters for the texture rectangle scale parameters
* (pre-gen6, or gen6+ with GL_CLAMP).
shadow_comparitor = this->result;
}
- fs_reg lod, lod2;
+ fs_reg lod, lod2, sample_index;
switch (ir->op) {
case ir_tex:
+ case ir_lod:
break;
case ir_txb:
ir->lod_info.bias->accept(this);
ir->lod_info.lod->accept(this);
lod = this->result;
break;
+ case ir_txf_ms:
+ ir->lod_info.sample_index->accept(this);
+ sample_index = this->result;
+ break;
};
/* Writemasking doesn't eliminate channels on SIMD8 texture
*/
fs_reg dst = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 4, 1));
- if (intel->gen >= 7) {
+ if (brw->gen >= 7) {
inst = emit_texture_gen7(ir, dst, coordinate, shadow_comparitor,
- lod, lod2);
- } else if (intel->gen >= 5) {
+ lod, lod2, sample_index);
+ } else if (brw->gen >= 5) {
inst = emit_texture_gen5(ir, dst, coordinate, shadow_comparitor,
- lod, lod2);
+ lod, lod2, sample_index);
} else {
inst = emit_texture_gen4(ir, dst, coordinate, shadow_comparitor,
lod, lod2);
{
this->result = orig_val;
- if (ir->op == ir_txs)
+ if (ir->op == ir_txs || ir->op == ir_lod)
return;
if (ir->type == glsl_type::float_type) {
cmp->predicate = BRW_PREDICATE_NORMAL;
cmp->flag_subreg = 1;
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
/* For performance, after a discard, jump to the end of the shader.
* However, many people will do foliage by discarding based on a
* texture's alpha mask, and then continue on to texture with the
goto out;
case ir_unop_f2b:
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0.0f), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_f, op[0]));
break;
case ir_unop_i2b:
- if (intel->gen >= 6) {
+ if (brw->gen >= 6) {
emit(CMP(reg_null_d, op[0], fs_reg(0), BRW_CONDITIONAL_NZ));
} else {
inst = emit(MOV(reg_null_d, op[0]));
inst->predicate = BRW_PREDICATE_NORMAL;
}
+/**
+ * Try to replace IF/MOV/ELSE/MOV/ENDIF with SEL.
+ *
+ * Many GLSL shaders contain the following pattern:
+ *
+ * x = condition ? foo : bar
+ *
+ * The compiler emits an ir_if tree for this, since each subexpression might be
+ * a complex tree that could have side-effects or short-circuit logic.
+ *
+ * However, the common case is to simply select one of two constants or
+ * variable values---which is exactly what SEL is for. In this case, the
+ * assembly looks like:
+ *
+ * (+f0) IF
+ * MOV dst src0
+ * ELSE
+ * MOV dst src1
+ * ENDIF
+ *
+ * which can be easily translated into:
+ *
+ * (+f0) SEL dst src0 src1
+ *
+ * If src0 is an immediate value, we promote it to a temporary GRF.
+ */
+void
+fs_visitor::try_replace_with_sel()
+{
+ fs_inst *endif_inst = (fs_inst *) instructions.get_tail();
+ assert(endif_inst->opcode == BRW_OPCODE_ENDIF);
+
+ /* Pattern match in reverse: IF, MOV, ELSE, MOV, ENDIF. */
+ int opcodes[] = {
+ BRW_OPCODE_IF, BRW_OPCODE_MOV, BRW_OPCODE_ELSE, BRW_OPCODE_MOV,
+ };
+
+ fs_inst *match = (fs_inst *) endif_inst->prev;
+ for (int i = 0; i < 4; i++) {
+ if (match->is_head_sentinel() || match->opcode != opcodes[4-i-1])
+ return;
+ match = (fs_inst *) match->prev;
+ }
+
+ /* The opcodes match; it looks like the right sequence of instructions. */
+ fs_inst *else_mov = (fs_inst *) endif_inst->prev;
+ fs_inst *then_mov = (fs_inst *) else_mov->prev->prev;
+ fs_inst *if_inst = (fs_inst *) then_mov->prev;
+
+ /* Check that the MOVs are the right form. */
+ if (then_mov->dst.equals(else_mov->dst) &&
+ !then_mov->is_partial_write() &&
+ !else_mov->is_partial_write()) {
+
+ /* Remove the matched instructions; we'll emit a SEL to replace them. */
+ while (!if_inst->next->is_tail_sentinel())
+ if_inst->next->remove();
+ if_inst->remove();
+
+ /* Only the last source register can be a constant, so if the MOV in
+ * the "then" clause uses a constant, we need to put it in a temporary.
+ */
+ fs_reg src0(then_mov->src[0]);
+ if (src0.file == IMM) {
+ src0 = fs_reg(this, glsl_type::float_type);
+ src0.type = then_mov->src[0].type;
+ emit(MOV(src0, then_mov->src[0]));
+ }
+
+ fs_inst *sel;
+ if (if_inst->conditional_mod) {
+ /* Sandybridge-specific IF with embedded comparison */
+ emit(CMP(reg_null_d, if_inst->src[0], if_inst->src[1],
+ if_inst->conditional_mod));
+ sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
+ sel->predicate = BRW_PREDICATE_NORMAL;
+ } else {
+ /* Separate CMP and IF instructions */
+ sel = emit(BRW_OPCODE_SEL, then_mov->dst, src0, else_mov->src[0]);
+ sel->predicate = if_inst->predicate;
+ sel->predicate_inverse = if_inst->predicate_inverse;
+ }
+ }
+}
+
void
fs_visitor::visit(ir_if *ir)
{
- if (intel->gen < 6 && dispatch_width == 16) {
+ if (brw->gen < 6 && dispatch_width == 16) {
fail("Can't support (non-uniform) control flow on 16-wide\n");
}
*/
this->base_ir = ir->condition;
- if (intel->gen == 6) {
+ if (brw->gen == 6) {
emit_if_gen6(ir);
} else {
emit_bool_to_cond_code(ir->condition);
}
emit(BRW_OPCODE_ENDIF);
+
+ try_replace_with_sel();
}
void
{
fs_reg counter = reg_undef;
- if (intel->gen < 6 && dispatch_width == 16) {
+ if (brw->gen < 6 && dispatch_width == 16) {
fail("Can't support (non-uniform) control flow on 16-wide\n");
}
(void)ir;
}
+void
+fs_visitor::visit(ir_emit_vertex *)
+{
+ assert(!"not reached");
+}
+
+void
+fs_visitor::visit(ir_end_primitive *)
+{
+ assert(!"not reached");
+}
+
fs_inst *
fs_visitor::emit(fs_inst inst)
{
emit(FS_OPCODE_LINTERP, wpos_w,
this->delta_x[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
this->delta_y[BRW_WM_PERSPECTIVE_PIXEL_BARYCENTRIC],
- interp_reg(FRAG_ATTRIB_WPOS, 3));
+ interp_reg(VARYING_SLOT_POS, 3));
/* Compute the pixel 1/W value from wpos.w. */
this->pixel_w = fs_reg(this, glsl_type::float_type);
emit_math(SHADER_OPCODE_RCP, this->pixel_w, wpos_w);
color.reg_offset += index;
- if (dispatch_width == 8 || intel->gen >= 6) {
+ if (dispatch_width == 8 || brw->gen >= 6) {
/* SIMD8 write looks like:
* m + 0: r0
* m + 1: r1
* dispatched. This field is only required for the end-of-
* thread message and on all dual-source messages."
*/
- if (intel->gen >= 6 &&
+ if (brw->gen >= 6 &&
!this->fp->UsesKill &&
!do_dual_src &&
c->key.nr_color_regions == 1) {
}
if (header_present) {
- src0_alpha_to_render_target = intel->gen >= 6 &&
+ src0_alpha_to_render_target = brw->gen >= 6 &&
!do_dual_src &&
- c->key.nr_color_regions > 1 &&
- c->key.sample_alpha_to_coverage;
+ c->key.replicate_alpha;
/* m2, m3 header */
nr += 2;
}
nr += reg_width;
if (c->source_depth_to_render_target) {
- if (intel->gen == 6 && dispatch_width == 16) {
+ if (brw->gen == 6 && dispatch_width == 16) {
/* For outputting oDepth on gen6, SIMD8 writes have to be
* used. This would require 8-wide moves of each half to
* message regs, kind of like pre-gen5 SIMD16 FB writes.
inst->saturate = c->key.clamp_fragment_color;
}
+ if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ emit_shader_time_end();
+
fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
inst->target = 0;
inst->base_mrf = base_mrf;
for (unsigned i = 0; i < this->output_components[target]; i++)
emit_color_write(target, i, write_color_mrf);
+ bool eot = false;
+ if (target == c->key.nr_color_regions - 1) {
+ eot = true;
+
+ if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ emit_shader_time_end();
+ }
+
fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
inst->target = target;
inst->base_mrf = base_mrf;
inst->mlen = nr - base_mrf - reg_width;
else
inst->mlen = nr - base_mrf;
- if (target == c->key.nr_color_regions - 1)
- inst->eot = true;
+ inst->eot = eot;
inst->header_present = header_present;
}
*/
emit_color_write(0, 3, color_mrf);
+ if (INTEL_DEBUG & DEBUG_SHADER_TIME)
+ emit_shader_time_end();
+
fs_inst *inst = emit(FS_OPCODE_FB_WRITE);
inst->base_mrf = base_mrf;
inst->mlen = nr - base_mrf;
fs_visitor::fs_visitor(struct brw_context *brw,
struct brw_wm_compile *c,
- struct gl_shader_program *prog,
+ struct gl_shader_program *shader_prog,
struct gl_fragment_program *fp,
unsigned dispatch_width)
: dispatch_width(dispatch_width)
this->c = c;
this->brw = brw;
this->fp = fp;
- this->prog = prog;
- this->intel = &brw->intel;
- this->ctx = &intel->ctx;
+ this->shader_prog = shader_prog;
+ this->ctx = &brw->ctx;
this->mem_ctx = ralloc_context(NULL);
- if (prog)
- shader = (struct brw_shader *) prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
+ if (shader_prog)
+ shader = (struct brw_shader *)
+ shader_prog->_LinkedShaders[MESA_SHADER_FRAGMENT];
else
shader = NULL;
this->failed = false;
memset(this->outputs, 0, sizeof(this->outputs));
memset(this->output_components, 0, sizeof(this->output_components));
this->first_non_payload_grf = 0;
- this->max_grf = intel->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+ this->max_grf = brw->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
this->current_annotation = NULL;
this->base_ir = NULL;
this->virtual_grf_sizes = NULL;
this->virtual_grf_count = 0;
this->virtual_grf_array_size = 0;
- this->virtual_grf_def = NULL;
- this->virtual_grf_use = NULL;
+ this->virtual_grf_start = NULL;
+ this->virtual_grf_end = NULL;
this->live_intervals_valid = false;
+ this->params_remap = NULL;
+ this->nr_params_remap = 0;
+
this->force_uncompressed_stack = 0;
this->force_sechalf_stack = 0;
projects / mesa.git / blobdiff